Lines Matching +full:0 +full:x5
36 #define SUCCESS 0
53 jbc = 0,
79 #define PIC0_EVT_SEL_SHIFT 0
85 #define JBC01_EVT_MASK 0xFF
86 #define IMU01_EVT_MASK 0xFF
87 #define MMU01_EVT_MASK 0xFF
88 #define TLU01_EVT_MASK 0xFF
89 #define TLU2_EVT_MASK 0x3
90 #define LPU12_EVT_MASK 0xFFFF
116 #define JBUS_REGS_AVAIL 0x1 /* JBUS regs avail */
117 #define PCIE_A_REGS_AVAIL 0x2
118 #define PCIE_B_REGS_AVAIL 0x4
152 * For example, JBC01 means the JBC performance counters 0 and 1
181 #define JBC01_EVT_NONE 0x0
182 #define JBC01_EVT_CLK 0x1
183 #define JBC01_EVT_IDLE 0x2
184 #define JBC01_EVT_FIRE 0x3
185 #define JBC01_EVT_READ_LATENCY 0x4
186 #define JBC01_EVT_READ_SAMPLE 0x5
187 #define JBC01_EVT_I2C_PIO 0x6
188 #define JBC01_EVT_EBUS_PIO 0x7
189 #define JBC01_EVT_RINGA_PIO 0x8
190 #define JBC01_EVT_RINGB_PIO 0x9
191 #define JBC01_EVT_PARTIAL_WR 0xA
192 #define JBC01_EVT_TOTAL_WR 0xB
193 #define JBC01_EVT_TOTAL_RD 0xC
194 #define JBC01_EVT_AOKOFF 0xD
195 #define JBC01_EVT_DOKOFF 0xE
196 #define JBC01_EVT_DAOKOFF 0xF
197 #define JBC01_EVT_JBUS_COH_XACT 0x10
198 #define JBC01_EVT_FIRE_COH_XACT 0x11
199 #define JBC01_EVT_JBUS_NCOH_XACT 0x12
200 #define JBC01_EVT_FGN_IO_HIT 0x13
201 #define JBC01_EVT_FIRE_WBS 0x14
202 #define JBC01_EVT_PCIEA_PIO_WR 0x15
203 #define JBC01_EVT_PCIEA_PIO_RD 0x16
204 #define JBC01_EVT_PCIEB_PIO_WR 0x17
205 #define JBC01_EVT_PCIEB_PIO_RD 0x18
215 #define IMU01_EVT_NONE 0x0
216 #define IMU01_EVT_CLK 0x1
217 #define IMU01_EVT_MONDO 0x2
218 #define IMU01_EVT_MSI 0x3
219 #define IMU01_EVT_MONDO_NAKS 0x4
220 #define IMU01_EVT_EQ_WR 0x5
221 #define IMU01_EVT_EQ_MONDO 0x6
234 #define MMU01_EVT_NONE 0x0
235 #define MMU01_EVT_CLK 0x1
236 #define MMU01_EVT_TRANSL 0x2
237 #define MMU01_EVT_STALL 0x3
238 #define MMU01_EVT_TRANSL_MISS 0x4
239 #define MMU01_EVT_TBLWLK_STALL 0x5
240 #define MMU01_EVT_BYPASS_TRANSL 0x6
241 #define MMU01_EVT_TRANSL_TRANSL 0x7
242 #define MMU01_EVT_FLOW_CNTL_STALL 0x8
243 #define MMU01_EVT_FLUSH_CACHE_ENT 0x9
269 #define TLU01_EVT_NONE 0x0
270 #define TLU01_EVT_CLK 0x1
271 #define TLU01_EVT_COMPL 0x2
272 #define TLU01_EVT_XMT_POST_CR_UNAV 0x10
273 #define TLU01_EVT_XMT_NPOST_CR_UNAV 0x11
274 #define TLU01_EVT_XMT_CMPL_CR_UNAV 0x12
275 #define TLU01_EVT_XMT_ANY_CR_UNAV 0x13
276 #define TLU01_EVT_RETRY_CR_UNAV 0x14
277 #define TLU01_EVT_MEMRD_PKT_RCVD 0x20
278 #define TLU01_EVT_MEMWR_PKT_RCVD 0x21
279 #define TLU01_EVT_RCV_CR_THRESH 0x22
280 #define TLU01_EVT_RCV_PST_HDR_CR_EXH 0x23
281 #define TLU01_EVT_RCV_PST_DA_CR_MPS 0x24
282 #define TLU01_EVT_RCV_NPST_HDR_CR_EXH 0x25
283 #define TLU01_EVT_RCVR_L0S 0x30
284 #define TLU01_EVT_RCVR_L0S_TRANS 0x31
285 #define TLU01_EVT_XMTR_L0S 0x32
286 #define TLU01_EVT_XMTR_L0S_TRANS 0x33
287 #define TLU01_EVT_RCVR_ERR 0x40
288 #define TLU01_EVT_BAD_TLP 0x42
289 #define TLU01_EVT_BAD_DLLP 0x43
290 #define TLU01_EVT_REPLAY_ROLLOVER 0x44
291 #define TLU01_EVT_REPLAY_TMO 0x47
298 #define TLU2_EVT_NONE 0x0
299 #define TLU2_EVT_NON_POST_COMPL_TIME 0x1
300 #define TLU2_EVT_XMT_DATA_WORD 0x2
301 #define TLU2_EVT_RCVD_DATA_WORD 0x3
323 #define LPU12_EVT_RESET 0x0
324 #define LPU12_EVT_TLP_RCVD 0x1
325 #define LPU12_EVT_DLLP_RCVD 0x2
326 #define LPU12_EVT_ACK_DLLP_RCVD 0x3
327 #define LPU12_EVT_NAK_DLLP_RCVD 0x4
328 #define LPU12_EVT_RETRY_START 0x5
329 #define LPU12_EVT_REPLAY_TMO 0x6
330 #define LPU12_EVT_ACK_NAK_LAT_TMO 0x7
331 #define LPU12_EVT_BAD_DLLP 0x8
332 #define LPU12_EVT_BAD_TLP 0x9
333 #define LPU12_EVT_NAK_DLLP_SENT 0xA
334 #define LPU12_EVT_ACK_DLLP_SENT 0xB
335 #define LPU12_EVT_RCVR_ERROR 0xC
336 #define LPU12_EVT_LTSSM_RECOV_ENTRY 0xD
337 #define LPU12_EVT_REPLAY_IN_PROG 0xE
338 #define LPU12_EVT_TLP_XMT_IN_PROG 0xF
339 #define LPU12_EVT_CLK_CYC 0x10
340 #define LPU12_EVT_TLP_DLLP_XMT_PROG 0x11
341 #define LPU12_EVT_TLP_DLLP_RCV_PROG 0x12