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/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Drenesas,emev2-smu.txt24 - #clock-cells: Should be <0>
35 - #clock-cells: Should be <0>
41 reg = <0x610 0>;
43 #clock-cells = <0>;
48 reg = <0x4a0 1>;
50 #clock-cells = <0>;
57 reg = <0xe1020000 0x38>;
58 interrupts = <0 8 0>;
70 reg = <0xe0110000 0x10000>;
72 #size-cells = <0>;
[all …]
H A Drenesas,emev2-smu.yaml28 const: 0
61 const: 0
92 const: 0
112 reg = <0xe0110000 0x10000>;
114 #size-cells = <0>;
119 #clock-cells = <0>;
126 #clock-cells = <0>;
128 usia_u0_sclkdiv: usia_u0_sclkdiv@610,0 {
130 reg = <0x610 0>;
132 #clock-cells = <0>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/marvell/
H A Dcn9130-crb-A.dts17 phys = <&cp0_comphy0 0
18 &cp0_comphy1 0
19 &cp0_comphy2 0
20 &cp0_comphy3 0>;
22 <0x0 &smmu 0x480 0x20>,
23 <0x100 &smmu 0x4a0 0x20>,
24 <0x200 &smmu 0x4c0 0x20>;
25 iommu-map-mask = <0x031f>;
H A Darmada-7040.dtsi20 <0x0 &smmu 0x480 0x20>,
21 <0x100 &smmu 0x4a0 0x20>,
22 <0x200 &smmu 0x4c0 0x20>;
23 iommu-map-mask = <0x031f>;
27 iommus = <&smmu 0x444>;
31 iommus = <&smmu 0x445>;
35 iommus = <&smmu 0x440>;
39 iommus = <&smmu 0x441>;
H A Dcn9130-crb-B.dts17 phys = <&cp0_comphy0 0>;
19 <0x0 &smmu 0x480 0x20>,
20 <0x100 &smmu 0x4a0 0x20>,
21 <0x200 &smmu 0x4c0 0x20>;
22 iommu-map-mask = <0x031f>;
27 sata-port@0 {
30 phys = <&cp0_comphy2 0>;
38 phys = <&cp0_comphy1 0>;
H A Darmada-8040.dtsi20 <0x0 &smmu 0x480 0x20>,
21 <0x100 &smmu 0x4a0 0x20>,
22 <0x200 &smmu 0x4c0 0x20>;
23 iommu-map-mask = <0x031f>;
36 iommus = <&smmu 0x444>;
40 iommus = <&smmu 0x445>;
44 iommus = <&smmu 0x440>;
48 iommus = <&smmu 0x441>;
52 iommus = <&smmu 0x454>;
56 iommus = <&smmu 0x450>;
[all …]
/freebsd/sys/contrib/device-tree/include/dt-bindings/clock/
H A Dlpc18xx-ccu.h13 #define CLK_APB3_BUS 0x100
14 #define CLK_APB3_I2C1 0x108
15 #define CLK_APB3_DAC 0x110
16 #define CLK_APB3_ADC0 0x118
17 #define CLK_APB3_ADC1 0x120
18 #define CLK_APB3_CAN0 0x128
19 #define CLK_APB1_BUS 0x200
20 #define CLK_APB1_MOTOCON_PWM 0x208
21 #define CLK_APB1_I2C0 0x210
22 #define CLK_APB1_I2S 0x218
[all …]
H A Dam4.h8 #define AM4_CLKCTRL_OFFSET 0x20
12 #define AM4_L3S_TSC_CLKCTRL_OFFSET 0x120
14 #define AM4_L3S_TSC_ADC_TSC_CLKCTRL AM4_L3S_TSC_CLKCTRL_INDEX(0x120)
17 #define AM4_L4_WKUP_AON_CLKCTRL_OFFSET 0x228
19 #define AM4_L4_WKUP_AON_WKUP_M3_CLKCTRL AM4_L4_WKUP_AON_CLKCTRL_INDEX(0x228)
20 #define AM4_L4_WKUP_AON_COUNTER_32K_CLKCTRL AM4_L4_WKUP_AON_CLKCTRL_INDEX(0x230)
23 #define AM4_L4_WKUP_CLKCTRL_OFFSET 0x220
25 #define AM4_L4_WKUP_L4_WKUP_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x220)
26 #define AM4_L4_WKUP_TIMER1_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x328)
27 #define AM4_L4_WKUP_WD_TIMER2_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x338)
[all …]
/freebsd/sys/contrib/device-tree/Bindings/pinctrl/
H A Dfsl,imx8mq-pinctrl.yaml75 reg = <0x30330000 0x10000>;
79 <0x234 0x49C 0x4F4 0x0 0x0 0x49>,
80 <0x238 0x4A0 0x4F4 0x0 0x0 0x49>;
/freebsd/sys/arm/freescale/
H A Dfsl_ocotpreg.h32 #define FSL_OCOTP_CTRL 0x000
33 #define FSL_OCOTP_CTRL_SET 0x004
34 #define FSL_OCOTP_CTRL_CLR 0x008
35 #define FSL_OCOTP_CTRL_TOG 0x00C
36 #define FSL_OCOTP_TIMING 0x010
37 #define FSL_OCOTP_DATA 0x020
38 #define FSL_OCOTP_READ_CTRL 0x030
39 #define FSL_OCOTP_READ_FUSE_DATA 0x040
40 #define FSL_OCOTP_SW_STICKY 0x050
41 #define FSL_OCOTP_SCS 0x060
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/freescale/
H A Dimx8mq-pinfunc.h15 #define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0…
16 #define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0…
17 #define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0…
18 #define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0…
19 #define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0…
20 #define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
21 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
22 #define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
23 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
24 #define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
[all …]
H A Dimx8mm-pinfunc.h14 #define MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
15 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
16 #define MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
17 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
18 #define MX8MM_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
19 #define MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0…
20 #define MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0…
21 #define MX8MM_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0…
22 #define MX8MM_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0…
23 #define MX8MM_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0…
[all …]
H A Dimx8mn-pinfunc.h14 …ne MX8MN_IOMUXC_BOOT_MODE2_CCMSRCGPCMIX_BOOT_MODE2 0x020 0x25C 0x000 0x0 0x0
15 …ne MX8MN_IOMUXC_BOOT_MODE2_I2C1_SCL 0x020 0x25C 0x55C 0x1 0x3
16 …ne MX8MN_IOMUXC_BOOT_MODE3_CCMSRCGPCMIX_BOOT_MODE3 0x024 0x260 0x000 0x0 0x0
17 …ne MX8MN_IOMUXC_BOOT_MODE3_I2C1_SDA 0x024 0x260 0x56C 0x1 0x3
18 …ne MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0
19 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x000 0x1 0x0
20 …ne MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0
21 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0
22 …ne MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0
23 …ne MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0
[all …]
H A Dimx8mp-pinfunc.h13 #define MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x014 0x274 0x000 0x0 0x0
14 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT 0x014 0x274 0x000 0x1 0x0
15 #define MX8MP_IOMUXC_GPIO1_IO00__ISP_FL_TRIG_0 0x014 0x274 0x5D4 0x3 0x0
16 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1 0x014 0x274 0x000 0x6 0x0
17 #define MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x018 0x278 0x000 0x0 0x0
18 #define MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x018 0x278 0x000 0x1 0x0
19 #define MX8MP_IOMUXC_GPIO1_IO01__ISP_SHUTTER_TRIG_0 0x018 0x278 0x5DC 0x3 0x0
20 #define MX8MP_IOMUXC_GPIO1_IO01__CCM_EXT_CLK2 0x018 0x278 0x000 0x6 0x0
21 #define MX8MP_IOMUXC_GPIO1_IO02__GPIO1_IO02 0x01C 0x27C 0x000 0x0 0x0
22 #define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x01C 0x27C 0x000 0x1 0x0
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx53-pinfunc.h13 #define MX53_PAD_GPIO_19__KPP_COL_5 0x020 0x348 0x840 0x0 0x0
14 #define MX53_PAD_GPIO_19__GPIO4_5 0x020 0x348 0x000 0x1 0x0
15 #define MX53_PAD_GPIO_19__CCM_CLKO 0x020 0x348 0x000 0x2 0x0
16 #define MX53_PAD_GPIO_19__SPDIF_OUT1 0x020 0x348 0x000 0x3 0x0
17 #define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 0x020 0x348 0x000 0x4 0x0
18 #define MX53_PAD_GPIO_19__ECSPI1_RDY 0x020 0x348 0x000 0x5 0x0
19 #define MX53_PAD_GPIO_19__FEC_TDATA_3 0x020 0x348 0x000 0x6 0x0
20 #define MX53_PAD_GPIO_19__SRC_INT_BOOT 0x020 0x348 0x000 0x7 0x0
21 #define MX53_PAD_KEY_COL0__KPP_COL_0 0x024 0x34c 0x000 0x0 0x0
22 #define MX53_PAD_KEY_COL0__GPIO4_6 0x024 0x34c 0x000 0x1 0x0
[all …]
H A Dimx6sl-pinfunc.h13 #define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x04c 0x2a4 0x000 0x0 0x0
14 #define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0
15 #define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x0
16 #define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0
17 #define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0
18 #define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x0
19 #define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x04c 0x2a4 0x7f4 0x6 0x0
20 #define MX6SL_PAD_AUD_RXC__AUD3_RXC 0x050 0x2a8 0x000 0x0 0x0
21 #define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0
22 #define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0
[all …]
H A Dimx6q-pinfunc.h13 #define MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x04c 0x360 0x000 0x0 0x0
14 #define MX6QDL_PAD_SD2_DAT1__ECSPI5_SS0 0x04c 0x360 0x834 0x1 0x0
15 #define MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0x04c 0x360 0x000 0x2 0x0
16 #define MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x04c 0x360 0x7c8 0x3 0x0
17 #define MX6QDL_PAD_SD2_DAT1__KEY_COL7 0x04c 0x360 0x8f0 0x4 0x0
18 #define MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x04c 0x360 0x000 0x5 0x0
19 #define MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x050 0x364 0x000 0x0 0x0
20 #define MX6QDL_PAD_SD2_DAT2__ECSPI5_SS1 0x050 0x364 0x838 0x1 0x0
21 #define MX6QDL_PAD_SD2_DAT2__EIM_CS3_B 0x050 0x364 0x000 0x2 0x0
22 #define MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x050 0x364 0x7b8 0x3 0x0
[all …]
H A Dimx25-pinfunc.h16 #define MX25_PAD_A10__A10 0x008 0x000 0x000 0x00 0x000
17 #define MX25_PAD_A10__GPIO_4_0 0x008 0x000 0x000 0x05 0x000
19 #define MX25_PAD_A13__A13 0x00c 0x22C 0x000 0x00 0x000
20 #define MX25_PAD_A13__GPIO_4_1 0x00c 0x22C 0x000 0x05 0x000
21 #define MX25_PAD_A13__LCDC_CLS 0x00c 0x22C 0x000 0x07 0x000
23 #define MX25_PAD_A14__A14 0x010 0x230 0x000 0x00 0x000
24 #define MX25_PAD_A14__GPIO_2_0 0x010 0x230 0x000 0x05 0x000
25 #define MX25_PAD_A14__SIM1_CLK1 0x010 0x230 0x000 0x06 0x000
26 #define MX25_PAD_A14__LCDC_SPL 0x010 0x230 0x000 0x07 0x000
28 #define MX25_PAD_A15__A15 0x014 0x234 0x000 0x00 0x000
[all …]
/freebsd/sys/contrib/device-tree/Bindings/mmc/
H A Dsdhci-msm.yaml112 pinctrl-0:
163 '^opp-?[0-9]+$':
225 reg = <0 0x08804000 0 0x1000>;
235 iommus = <&apps_smmu 0x4a0 0x0>;
236 qcom,dll-config = <0x0007642
[all...]
/freebsd/sys/dev/ntb/ntb_hw/
H A Dntb_hw_amd.h48 #define NTB_HW_AMD_VENDOR_ID 0x1022
49 #define NTB_HW_AMD_DEVICE_ID1 0x145B
50 #define NTB_HW_AMD_DEVICE_ID2 0x148B
52 #define NTB_HW_HYGON_VENDOR_ID 0x19D4
53 #define NTB_HW_HYGON_DEVICE_ID1 0x145B
56 #define NTB_DEF_PEER_IDX 0
61 #define NTB_LIN_STA_ACTIVE_BIT 0x00000002
62 #define NTB_LNK_STA_SPEED_MASK 0x000F0000
63 #define NTB_LNK_STA_WIDTH_MASK 0x03F00000
87 #define QUIRK_MW0_32BIT 0x01
[all …]
/freebsd/sys/dev/bwi/
H A Dbwiphy.c103 #define BWI_PHYTBL_WRSSI 0x1000
104 #define BWI_PHYTBL_NOISE_SCALE 0x1400
105 #define BWI_PHYTBL_NOISE 0x1800
106 #define BWI_PHYTBL_ROTOR 0x2000
107 #define BWI_PHYTBL_DELAY 0x2400
108 #define BWI_PHYTBL_RSSI 0x4000
109 #define BWI_PHYTBL_SIGMA_SQ 0x5000
110 #define BWI_PHYTBL_WRSSI_REV1 0x5400
111 #define BWI_PHYTBL_FREQ 0x5800
187 for (i = 0; i < nitems(bwi_sup_bphy); ++i) { in bwi_phy_attach()
[all …]
/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Ddm816x-clocks.dtsi7 reg = <0x400 0x40>;
23 reg = <0x440 0x30>;
35 reg = <0x470 0x30>;
46 reg = <0x4a0 0x30>;
59 #clock-cells = <0>;
65 #clock-cells = <0>;
71 #clock-cells = <0>;
77 #clock-cells = <0>;
83 /* 0x48180000 */
86 #clock-cells = <0>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/renesas/
H A Demev2.dtsi29 #size-cells = <0>;
31 cpu0: cpu@0 {
34 reg = <0>;
49 reg = <0xe0028000 0x1000>,
50 <0xe0020000 0x0100>;
62 reg = <0xe0110000 0x10000>;
64 #size-cells = <0>;
69 #clock-cells = <0>;
71 iic0_sclkdiv: iic0_sclkdiv@624,0 {
73 reg = <0x624 0>;
[all …]
/freebsd/sys/dev/dwc/
H A Ddwc1000_reg.h37 #define MAC_CONFIGURATION 0x0
47 #define MAC_FRAME_FILTER 0x4
53 #define FRAME_FILTER_PR (1 << 0) /* All Incoming Frames */
54 #define GMAC_MAC_HTHIGH 0x08
55 #define GMAC_MAC_HTLOW 0x0c
56 #define GMII_ADDRESS 0x10
57 #define GMII_ADDRESS_PA_MASK 0x1f /* Phy device */
59 #define GMII_ADDRESS_GR_MASK 0x1f /* Phy register */
61 #define GMII_ADDRESS_CR_MASK 0xf
64 #define GMII_ADDRESS_GB (1 << 0) /* Busy */
[all …]
/freebsd/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dosprey_reg_map.h86 volatile char pad__0[0x8]; /* 0x0 - 0x8 */
87 volatile u_int32_t MAC_DMA_CR; /* 0x8 - 0xc */
88 volatile char pad__1[0x8]; /* 0xc - 0x14 */
89 volatile u_int32_t MAC_DMA_CFG; /* 0x14 - 0x18 */
90 volatile u_int32_t MAC_DMA_RXBUFPTR_THRESH; /* 0x18 - 0x1c */
91 volatile u_int32_t MAC_DMA_TXDPPTR_THRESH; /* 0x1c - 0x20 */
92 volatile u_int32_t MAC_DMA_MIRT; /* 0x20 - 0x24 */
93 volatile u_int32_t MAC_DMA_GLOBAL_IER; /* 0x24 - 0x28 */
94 volatile u_int32_t MAC_DMA_TIMT; /* 0x28 - 0x2c */
95 volatile u_int32_t MAC_DMA_RIMT; /* 0x2c - 0x30 */
[all …]

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