Searched +full:0 +full:x46200000 (Results 1 – 5 of 5) sorted by relevance
45 implementation defined. Some SoCs can use 0x00000000-0x0fffffff and46 0x40000000-0x4fffffff, while other SoCs only 0x40000000-0x4fffffff.53 bank 0 to 0x42000000-0x43ffffff, bank 5 to 0x46000000-0x46ffffff55 bank 0 to 0x48000000-0x49ffffff, bank 5 to 0x44000000-0x44ffffff61 "^.*@[1-5],[1-9a-f][0-9a-f]+$":77 // - the Ethernet device is connected at the offset 0x01f00000 of CS1 and78 // mapped to 0x43f00000 of the parent bus.79 // - the UART device is connected at the offset 0x00200000 of CS5 and80 // mapped to 0x46200000 of the parent bus.84 reg = <0x58c00000 0x400>;[all …]
17 #size-cells = <0>;19 cpu0: cpu@0 {22 reg = <0>;38 arm,smc-id = <0xb200005a>;44 #clock-cells = <0>;46 clock-frequency = <0>;50 #clock-cells = <0>;67 #size-cells = <0>;68 linaro,optee-channel-id = <0>;71 reg = <0x14>;[all …]
24 #clock-cells = <0>;30 #clock-cells = <0>;38 #size-cells = <0>;40 CPU0: cpu@0 {43 reg = <0x0 0x0>;57 reg = <0x0 0x1>;66 reg = <0x0 0x2>;75 reg = <0x0 0x3>;84 reg = <0x0 0x100>;98 reg = <0x0 0x101>;[all …]
30 #clock-cells = <0>;35 #clock-cells = <0>;41 #size-cells = <0>;43 CPU0: cpu@0 {46 reg = <0x0 0x0>;47 clocks = <&cpufreq_hw 0>;52 qcom,freq-domain = <&cpufreq_hw 0>;65 reg = <0x0 0x1>;66 clocks = <&cpufreq_hw 0>;71 qcom,freq-domain = <&cpufreq_hw 0>;[all …]
1 0x00 = 0x000000002 0x01 = 0x010000003 0x02 = 0x020000004 0x03 = 0x030000005 0x04 = 0x040000006 0x05 = 0x050000007 0x06 = 0x060000008 0x07 = 0x070000009 0x08 = 0x0800000010 0x09 = 0x09000000[all …]