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/freebsd/sys/contrib/device-tree/src/arm64/ti/
H A Dk3-am65.dtsi54 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
55 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
56 <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */
57 <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */
58 <0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */
59 <0x00 0x70000000 0x00 0x70000000 0x00 0x00200000>, /* MSMC SRAM */
60 <0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */
62 <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
63 <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>,
64 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
[all …]
H A Dk3-j721s2.dtsi29 #size-cells = <0>;
42 cpu0: cpu@0 {
44 reg = <0x000>;
47 i-cache-size = <0xc000>;
50 d-cache-size = <0x8000>;
58 reg = <0x001>;
61 i-cache-size = <0xc000>;
64 d-cache-size = <0x8000>;
75 cache-size = <0x100000>;
118 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
[all …]
H A Dk3-j7200.dtsi25 #size-cells = <0>;
39 cpu0: cpu@0 {
41 reg = <0x000>;
44 i-cache-size = <0xc000>;
47 d-cache-size = <0x8000>;
55 reg = <0x001>;
58 i-cache-size = <0xc000>;
61 d-cache-size = <0x8000>;
72 cache-size = <0x100000>;
113 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
[all …]
H A Dk3-j784s4-j742s2-common.dtsi27 cache-size = <0x200000>;
37 cache-size = <0x200000>;
80 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
81 <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */
82 <0x00 0x00700000 0x00 0x00700000 0x00 0x00001000>, /* ESM */
83 <0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */
84 <0x00 0x04210000 0x00 0x04210000 0x00 0x00010000>, /* VPU0 */
85 <0x00 0x04220000 0x00 0x04220000 0x00 0x00010000>, /* VPU1 */
86 <0x00 0x0d000000 0x00 0x0d000000 0x00 0x00800000>, /* PCIe0 Core*/
87 <0x00 0x0d800000 0x00 0x0d800000 0x00 0x00800000>, /* PCIe1 Core*/
[all …]
H A Dk3-j721e.dtsi25 #size-cells = <0>;
39 cpu0: cpu@0 {
41 reg = <0x000>;
44 i-cache-size = <0xC000>;
47 d-cache-size = <0x8000>;
55 reg = <0x001>;
58 i-cache-size = <0xC000>;
61 d-cache-size = <0x8000>;
72 cache-size = <0x100000>;
114 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
[all …]
H A Dk3-am65-mcu.dtsi13 ranges = <0x0 0x0 0x40f00000 0x20000>;
17 reg = <0x200 0x8>;
22 reg = <0x4040 0x4>;
30 reg = <0x0 0x40f04200 0x0 0x10>;
33 pinctrl-single,function-mask = <0x00000101>;
39 reg = <0x0 0x40f04280 0x0 0x8>;
42 pinctrl-single,function-mask = <0x00000003>;
47 reg = <0x00 0x40a00000 0x00 0x100>;
56 reg = <0x00 0x41c00000 0x00 0x80000>;
57 ranges = <0x0 0x00 0x41c00000 0x80000>;
[all …]
H A Dk3-j721e-mcu-wakeup.dtsi19 reg = <0x00 0x44083000 0x0 0x1000>;
44 ranges = <0x0 0x0 0x40f00000 0x20000>;
48 reg = <0x200 0x8>;
53 reg = <0x4040 0x4>;
62 ranges = <0x0 0x00 0x43000000 0x20000>;
66 reg = <0x14 0x4>;
73 /* Proxy 0 addressing */
74 reg = <0x00 0x4301c000 0x00 0x178>;
77 pinctrl-single,function-mask = <0xffffffff>;
83 reg = <0x00 0x40f04200 0x00 0x28>;
[all …]
H A Dk3-j7200-mcu-wakeup.dtsi19 reg = <0x00 0x44083000 0x00 0x1000>;
43 reg = <0x00 0x40400000 0x00 0x400>;
57 reg = <0x00 0x40410000 0x00 0x400>;
61 assigned-clocks = <&k3_clks 71 1>, <&k3_clks 308 0>;
70 reg = <0x00 0x40420000 0x00 0x400>;
83 reg = <0x00 0x40430000 0x00 0x400>;
87 assigned-clocks = <&k3_clks 73 1>, <&k3_clks 309 0>;
96 reg = <0x00 0x40440000 0x00 0x400>;
109 reg = <0x00 0x40450000 0x00 0x400>;
113 assigned-clocks = <&k3_clks 75 1>, <&k3_clks 310 0>;
[all …]
H A Dk3-j784s4-mcu-wakeup.dtsi20 reg = <0x00 0x44083000 0x00 0x1000>;
46 ranges = <0x0 0x00 0x43000000 0x20000>;
51 reg = <0x14 0x4>;
59 reg = <0x00 0x43600000 0x00 0x10000>,
60 <0x00 0x44880000 0x00 0x20000>,
61 <0x00 0x44860000 0x00 0x20000>;
72 reg = <0x00 0x41c00000 0x00 0x100000>;
73 ranges = <0x00 0x00 0x41c00000 0x100000>;
80 /* Proxy 0 addressing */
81 reg = <0x00 0x4301c000 0x00 0x034>;
[all …]
H A Dk3-j784s4-j742s2-mcu-wakeup-common.dtsi19 reg = <0x00 0x44083000 0x00 0x1000>;
44 ranges = <0x0 0x00 0x43000000 0x20000>;
49 reg = <0x14 0x4>;
57 reg = <0x00 0x43600000 0x00 0x10000>,
58 <0x00 0x44880000 0x00 0x20000>,
59 <0x00 0x44860000 0x00 0x20000>;
72 reg = <0x00 0x41c00000 0x00 0x100000>;
73 ranges = <0x00 0x00 0x41c00000 0x100000>;
80 /* Proxy 0 addressing */
81 reg = <0x00 0x4301c000 0x00 0x034>;
[all …]
H A Dk3-j721s2-mcu-wakeup.dtsi19 reg = <0x00 0x44083000 0x00 0x1000>;
44 ranges = <0x0 0x00 0x43000000 0x20000>;
48 reg = <0x14 0x4>;
57 reg = <0x00 0x43600000 0x00 0x10000>,
58 <0x00 0x44880000 0x00 0x20000>,
59 <0x00 0x44860000 0x00 0x20000>;
72 reg = <0x00 0x41c00000 0x00 0x100000>;
73 ranges = <0x00 0x00 0x41c00000 0x100000>;
80 /* Proxy 0 addressing */
81 reg = <0x00 0x4301c000 0x00 0x034>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/bus/
H A Dsocionext,uniphier-system-bus.yaml45 implementation defined. Some SoCs can use 0x00000000-0x0fffffff and
46 0x40000000-0x4fffffff, while other SoCs only 0x40000000-0x4fffffff.
53 bank 0 to 0x42000000-0x43ffffff, bank 5 to 0x46000000-0x46ffffff
55 bank 0 to 0x48000000-0x49ffffff, bank 5 to 0x44000000-0x44ffffff
61 "^.*@[1-5],[1-9a-f][0-9a-f]+$":
77 // - the Ethernet device is connected at the offset 0x01f00000 of CS1 and
78 // mapped to 0x43f00000 of the parent bus.
79 // - the UART device is connected at the offset 0x00200000 of CS5 and
80 // mapped to 0x46200000 of the parent bus.
84 reg = <0x58c00000 0x400>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dti,k3-am654-cpsw-nuss.yaml19 The internal Communications Port Programming Interface (CPPI5) (Host port 0).
20 Host Port 0 CPPI Packet Streaming Interface interface supports 8 TX channels
27 Support for Audio/Video Bridging (P802.1Qav/D6.0)
31 IEEE P902.3br/D2.0 Interspersing Express Traffic
113 const: 0
171 "^mdio@[0-9a-f]+$":
178 "^cpts@[0-9a-f]+":
254 reg = <0x0 0x46000000 0x0 0x200000>;
256 ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>;
262 pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/ata/
H A Dcortina,gemini-sata-bridge.txt17 the ATA controller and SATA bridges. Values 0..3:
18 Mode 0: ata0 master <-> sata0
45 reg = <0x46000000 0x100>;
H A Dcortina,gemini-sata-bridge.yaml49 - 0
56 Mode 0: ata0 master <-> sata0
97 reg = <0x46000000 0x100>;
/freebsd/sys/contrib/device-tree/src/arm64/nvidia/
H A Dtegra264.dtsi22 reg = <0x0 0x86070000 0x0 0x2000>;
28 bus@0 {
34 ranges = <0x00 0x00000000 0x00 0x00000000 0x01 0x00000000>;
38 reg = <0x0 0x00100000 0x0 0x0f000>,
39 <0x0 0x0c140000 0x0 0x10000>;
44 reg = <0x0 0x08000000 0x0 0x140000>;
54 reg = <0x0 0x08400000 0x0 0x210000>;
88 iommus = <&smmu1 0x00000800>;
90 dma-channel-mask = <0xfffffffe>;
96 reg = <0x0 0x08800000 0x0 0xd0000>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Dam33xx-l4.dtsi1 &l4_wkup { /* 0x44c00000 */
4 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_L4_WKUP_CLKCTRL 0>;
6 reg = <0x44c00000 0x800>,
7 <0x44c00800 0x800>,
8 <0x44c01000 0x400>,
9 <0x44c01400 0x40
[all...]
H A Dam437x-l4.dtsi1 &l4_wkup { /* 0x44c00000 */
4 clocks = <&l4_wkup_clkctrl AM4_L4_WKUP_L4_WKUP_CLKCTRL 0>;
6 reg = <0x44c00000 0x800>,
7 <0x44c00800 0x800>,
8 <0x44c01000 0x400>,
9 <0x44c01400 0x400>;
13 ranges = <0x00000000 0x44c00000 0x100000>, /* segment 0 */
14 <0x00100000 0x44d00000 0x100000>, /* segment 1 */
15 <0x00200000 0x44e00000 0x100000>; /* segment 2 */
17 segment@0 { /* 0x44c00000 */
[all …]
H A Ddra7-l4.dtsi1 &l4_cfg { /* 0x4a000000 */
4 clocks = <&l4cfg_clkctrl DRA7_L4CFG_L4_CFG_CLKCTRL 0>;
6 reg = <0x4a000000 0x800>,
7 <0x4a000800 0x800>,
8 <0x4a001000 0x1000>;
12 ranges = <0x00000000 0x4a000000 0x100000>, /* segment 0 */
13 <0x00100000 0x4a100000 0x100000>, /* segment 1 */
14 <0x00200000 0x4a200000 0x100000>; /* segment 2 */
17 segment@0 { /* 0x4a000000 */
21 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/mediatek/
H A Dmt6795-sony-xperia-m5.dts35 disp_led_pwm: led-0 {
37 pwms = <&pwm0 0 500000>;
44 reg = <0 0x40000000 0 0x1e800000>;
54 reg = <0 0x43000000 0 0x30000>;
60 reg = <0 0x44800000 0 0x100000>;
65 reg = <0 0x46000000 0 0x400000>;
101 #size-cells = <0>;
103 panel: panel@0 {
105 reg = <0>;
113 pinctrl-0 = <&disp_rst_pins>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/dma/
H A Dti-edma.txt25 <&tptc_phandle TC_priority_number>. The highest priority is 0.
86 reg = <0x49000000 0x10000>;
93 ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 7>, <&edma_tptc2 0>;
100 dma-channel-mask = <0xffffffff /* Channel 0-31 */
101 0xffffe007>; /* Channel 32-63 */
107 reg = <0x49800000 0x100000>;
115 reg = <0x49900000 0x100000>;
123 reg = <0x49a00000 0x100000>;
131 reg = <0x53100000 0x200>;
134 dmas = <&edma 36 0>;
[all …]
/freebsd/contrib/llvm-project/lld/ELF/Arch/
H A DHexagon.cpp3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
56 defaultMaxPageSize = 0x10000; in Hexagon()
71 return ret.value_or(/* Default Arch Rev: */ 0x60); in calcEFlags()
75 uint32_t result = 0; in applyMask()
76 size_t off = 0; in applyMask()
78 for (size_t bit = 0; bit != 32; ++bit) { in applyMask()
170 {0x38000000, 0x0000201f}, {0x39000000, 0x0000201f},
171 {0x3e000000, 0x00001f80}, {0x3f000000, 0x00001f80},
172 {0x40000000, 0x000020f8}, {0x41000000, 0x000007e0},
173 {0x42000000, 0x000020f8}, {0x43000000, 0x000007e0},
[all …]
/freebsd/sys/contrib/device-tree/src/arm/gemini/
H A Dgemini.dtsi23 pinctrl-0 = <&pflash_default_pins>;
31 reg = <0x40000000 0x1000>;
39 offset = <0x0c>;
41 mask = <0xC0000000>;
49 pinctrl-0 = <&dram_default_pins>, <&system_default_pins>,
159 reg = <0x41000000 0x1000>;
168 reg = <0x42000000 0x100>;
173 pinctrl-0 = <&uart_default_pins>;
179 reg = <0x43000000 0x1000>;
193 reg = <0x45000000 0x100>;
[all …]
/freebsd/sys/dev/ti/
H A Dti_fw2.h6 static int tigon2FwReleaseMajor = 0xc;
7 static int tigon2FwReleaseMinor = 0x4;
8 static int tigon2FwReleaseFix = 0xb;
9 static u_int32_t tigon2FwStartAddr = 0x00004000;
10 static u_int32_t tigon2FwTextAddr = 0x00004000;
11 int tigon2FwTextLen = 0x132f8;
12 static u_int32_t tigon2FwRodataAddr = 0x000172f8;
13 int tigon2FwRodataLen = 0x10da;
14 static u_int32_t tigon2FwDataAddr = 0x000185c0;
15 int tigon2FwDataLen = 0x17c;
[all …]
/freebsd/sys/contrib/openzfs/module/icp/asm-x86_64/aes/
H A Daestab2.h50 0x00000001, 0x00000002, 0x00000004, 0x00000008,
51 0x00000010, 0x00000020, 0x00000040, 0x00000080,
52 0x0000001b, 0x00000036
58 0x00000063, 0x0000007c, 0x00000077, 0x0000007b,
59 0x000000f2, 0x0000006b, 0x0000006f, 0x000000c5,
60 0x00000030, 0x00000001, 0x00000067, 0x0000002b,
61 0x000000fe, 0x000000d7, 0x000000ab, 0x00000076,
62 0x000000ca, 0x00000082, 0x000000c9, 0x0000007d,
63 0x000000fa, 0x00000059, 0x00000047, 0x000000f0,
64 0x000000ad, 0x000000d4, 0x000000a2, 0x000000af,
[all …]

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