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/linux/include/uapi/linux/
H A Dptrace.h11 #define PTRACE_TRACEME 0
27 /* 0x4200-0x4300 are reserved for architecture-independent additions. */
28 #define PTRACE_SETOPTIONS 0x4200
29 #define PTRACE_GETEVENTMSG 0x4201
30 #define PTRACE_GETSIGINFO 0x4202
31 #define PTRACE_SETSIGINFO 0x4203
50 #define PTRACE_GETREGSET 0x4204
51 #define PTRACE_SETREGSET 0x4205
53 #define PTRACE_SEIZE 0x4206
54 #define PTRACE_INTERRUPT 0x4207
[all …]
/linux/drivers/regulator/
H A Dqcom_spmi-regulator.c25 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_NONE 0x00
26 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN0 0x01
27 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN1 0x02
28 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN2 0x04
29 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN3 0x08
30 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_HW_DEFAULT 0x10
33 #define SPMI_REGULATOR_PIN_CTRL_HPM_NONE 0x00
34 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN0 0x01
35 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN1 0x02
36 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN2 0x04
[all …]
H A Dqcom-pm8008-regulator.c22 #define LDO_STEPPER_CTL_REG 0x3b
23 #define STEP_RATE_MASK GENMASK(1, 0)
25 #define LDO_VSET_LB_REG 0x40
27 #define LDO_ENABLE_REG 0x46
45 REGULATOR_LINEAR_RANGE(528000, 0, 122, 8000),
49 REGULATOR_LINEAR_RANGE(1504000, 0, 237, 8000),
53 { "ldo1", "vdd-l1-l2", 0x4000, 225000, nldo_ranges, },
54 { "ldo2", "vdd-l1-l2", 0x4100, 225000, nldo_ranges, },
55 { "ldo3", "vdd-l3-l4", 0x4200, 300000, pldo_ranges, },
56 { "ldo4", "vdd-l3-l4", 0x4300, 300000, pldo_ranges, },
[all …]
/linux/drivers/net/ethernet/huawei/hinic/
H A Dhinic_hw_csr.h11 #define HINIC_CSR_FUNC_ATTR0_ADDR 0x0
12 #define HINIC_CSR_FUNC_ATTR1_ADDR 0x4
13 #define HINIC_CSR_FUNC_ATTR2_ADDR 0x8
14 #define HINIC_CSR_FUNC_ATTR4_ADDR 0x10
15 #define HINIC_CSR_FUNC_ATTR5_ADDR 0x14
17 #define HINIC_DMA_ATTR_BASE 0xC80
18 #define HINIC_ELECTION_BASE 0x4200
20 #define HINIC_DMA_ATTR_STRIDE 0x4
24 #define HINIC_PPF_ELECTION_STRIDE 0x4
30 #define HINIC_CSR_API_CMD_BASE 0xF000
[all …]
/linux/drivers/dma/ti/
H A Dk3-psil-am654.c54 PSIL_SA2UL(0x4000, 0),
55 PSIL_SA2UL(0x4001, 0),
56 PSIL_SA2UL(0x4002, 0),
57 PSIL_SA2UL(0x4003, 0),
59 PSIL_ETHERNET(0x4100),
60 PSIL_ETHERNET(0x4101),
61 PSIL_ETHERNET(0x4102),
62 PSIL_ETHERNET(0x4103),
64 PSIL_ETHERNET(0x4200),
65 PSIL_ETHERNET(0x4201),
[all …]
H A Dk3-psil-am64.c66 PSIL_SAUL(0x4000, 17, 32, 8, 32, 0),
67 PSIL_SAUL(0x4001, 18, 32, 8, 33, 0),
68 PSIL_SAUL(0x4002, 19, 40, 8, 40, 0),
69 PSIL_SAUL(0x4003, 20, 40, 8, 41, 0),
71 PSIL_ETHERNET(0x4100, 21, 48, 16),
72 PSIL_ETHERNET(0x4101, 22, 64, 16),
73 PSIL_ETHERNET(0x4102, 23, 80, 16),
74 PSIL_ETHERNET(0x4103, 24, 96, 16),
76 PSIL_ETHERNET(0x4200, 25, 112, 16),
77 PSIL_ETHERNET(0x4201, 26, 128, 16),
[all …]
H A Dk3-psil-j721e.c72 PSIL_SA2UL(0x4000, 0),
73 PSIL_SA2UL(0x4001, 0),
74 PSIL_SA2UL(0x4002, 0),
75 PSIL_SA2UL(0x4003, 0),
77 PSIL_ETHERNET(0x4100),
78 PSIL_ETHERNET(0x4101),
79 PSIL_ETHERNET(0x4102),
80 PSIL_ETHERNET(0x4103),
82 PSIL_ETHERNET(0x4200),
83 PSIL_ETHERNET(0x4201),
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
H A Dgt215.c46 u32 sctl = nvkm_rd32(device, 0x4120 + (idx * 4)); in read_vco()
48 switch (sctl & 0x00000030) { in read_vco()
49 case 0x00000000: in read_vco()
51 case 0x00000020: in read_vco()
52 return read_pll(clk, 0x41, 0x00e820); in read_vco()
53 case 0x00000030: in read_vco()
54 return read_pll(clk, 0x42, 0x00e8a0); in read_vco()
56 return 0; in read_vco()
66 /* refclk for the 0xe8xx plls is a fixed frequency */ in read_clk()
67 if (idx >= 0x40) { in read_clk()
[all …]
/linux/drivers/gpu/drm/radeon/reg_srcs/
H A Drv5151 rv515 0x6d40
2 0x1434 SRC_Y_X
3 0x1438 DST_Y_X
4 0x143C DST_HEIGHT_WIDTH
5 0x146C DP_GUI_MASTER_CNTL
6 0x1474 BRUSH_Y_X
7 0x1478 DP_BRUSH_BKGD_CLR
8 0x147C DP_BRUSH_FRGD_CLR
9 0x1480 BRUSH_DATA0
10 0x1484 BRUSH_DATA1
[all …]
H A Dr3001 r300 0x4f60
2 0x1434 SRC_Y_X
3 0x1438 DST_Y_X
4 0x143C DST_HEIGHT_WIDTH
5 0x146C DP_GUI_MASTER_CNTL
6 0x1474 BRUSH_Y_X
7 0x1478 DP_BRUSH_BKGD_CLR
8 0x147C DP_BRUSH_FRGD_CLR
9 0x1480 BRUSH_DATA0
10 0x1484 BRUSH_DATA1
[all …]
H A Drs6001 rs600 0x6d40
2 0x1434 SRC_Y_X
3 0x1438 DST_Y_X
4 0x143C DST_HEIGHT_WIDTH
5 0x146C DP_GUI_MASTER_CNTL
6 0x1474 BRUSH_Y_X
7 0x1478 DP_BRUSH_BKGD_CLR
8 0x147C DP_BRUSH_FRGD_CLR
9 0x1480 BRUSH_DATA0
10 0x1484 BRUSH_DATA1
[all …]
H A Dr4201 r420 0x4f60
2 0x1434 SRC_Y_X
3 0x1438 DST_Y_X
4 0x143C DST_HEIGHT_WIDTH
5 0x146C DP_GUI_MASTER_CNTL
6 0x1474 BRUSH_Y_X
7 0x1478 DP_BRUSH_BKGD_CLR
8 0x147C DP_BRUSH_FRGD_CLR
9 0x1480 BRUSH_DATA0
10 0x1484 BRUSH_DATA1
[all …]
/linux/arch/mips/include/asm/
H A Dprocessor.h39 #define TASK_SIZE 0x80000000UL
55 #define TASK_SIZE32 0x7fff8000UL
57 #define TASK_SIZE64 (0x1UL << ((cpu_data[0].vmbits>48)?48:cpu_data[0].vmbits))
59 #define TASK_SIZE64 0x10000000000UL
139 {0,} \
158 /* DMFC2 rt, 0x0201 */
160 /* DMFC2 rt, 0x0202 (Set with DMTC2 rt, 0x1202) */
162 /* DMFC2 rt, 0x0200 (set with DMTC2 rt, 0x4200) */
164 /* DMFC2 rt, 0x0402; DMFC2 rt, 0x040A */
166 /* DMFC2 rt, 0x0084 */
[all …]
H A Dcpu.h16 register 15, select 0) is defined in this (backwards compatible) way:
24 that bits 16-23 have been 0 for all MIPS processors before the MIPS32/64
28 #define PRID_OPT_MASK 0xff000000
34 #define PRID_COMP_MASK 0xff0000
36 #define PRID_COMP_LEGACY 0x000000
37 #define PRID_COMP_MIPS 0x010000
38 #define PRID_COMP_BROADCOM 0x020000
39 #define PRID_COMP_ALCHEMY 0x030000
40 #define PRID_COMP_SIBYTE 0x040000
41 #define PRID_COMP_SANDCRAFT 0x050000
[all …]
/linux/arch/arm64/boot/dts/ti/
H A Dk3-am654-idk.dtso17 ethernet3 = "/icssg0-eth/ethernet-ports/port@0";
19 ethernet5 = "/icssg1-eth/ethernet-ports/port@0";
27 pinctrl-0 = <&icssg0_rgmii_pins_default>;
50 interrupts = <24 0 2>, <25 1 3>;
53 dmas = <&main_udmap 0xc100>, /* egress slice 0 */
54 <&main_udmap 0xc101>, /* egress slice 0 */
55 <&main_udmap 0xc102>, /* egress slice 0 */
56 <&main_udmap 0xc103>, /* egress slice 0 */
57 <&main_udmap 0xc104>, /* egress slice 1 */
58 <&main_udmap 0xc105>, /* egress slice 1 */
[all …]
/linux/drivers/net/ethernet/amd/
H A Dariadne.h17 * Publication #16907, Rev. B, Amendment/0, May 1994
62 #define CSR0 0x0000 /* - PCnet-ISA Controller Status */
63 #define CSR1 0x0100 /* - IADR[15:0] */
64 #define CSR2 0x0200 /* - IADR[23:16] */
65 #define CSR3 0x0300 /* - Interrupt Masks and Deferral Control */
66 #define CSR4 0x0400 /* - Test and Features Control */
67 #define CSR6 0x0600 /* RCV/XMT Descriptor Table Length */
68 #define CSR8 0x0800 /* - Logical Address Filter, LADRF[15:0] */
69 #define CSR9 0x0900 /* - Logical Address Filter, LADRF[31:16] */
70 #define CSR10 0x0a00 /* - Logical Address Filter, LADRF[47:32] */
[all …]
/linux/drivers/media/usb/pwc/
H A Dpwc-ctrl.c41 #define GET_STATUS_B00 0x0B00
42 #define SENSOR_TYPE_FORMATTER1 0x0C00
43 #define GET_STATUS_3000 0x3000
44 #define READ_RAW_Y_MEAN_FORMATTER 0x3100
45 #define SET_POWER_SAVE_MODE_FORMATTER 0x3200
46 #define MIRROR_IMAGE_FORMATTER 0x3300
47 #define LED_FORMATTER 0x3400
48 #define LOWLIGHT 0x3500
49 #define GET_STATUS_3600 0x3600
50 #define SENSOR_TYPE_FORMATTER2 0x3700
[all …]
/linux/arch/mips/kernel/
H A Docteon_switch.S31 #if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
38 andi t0, 0x3f
46 LONG_L t8, 0(t1) /* Load from CVMSEG */
50 LONG_S t8, 0(t2) /* Store CVMSEG to thread storage */
58 xori t0, t0, 0x40 /* Bit 6 is CVMSEG user enable */
66 LONG_S t9, 0(t8)
80 li a3, 0xff01
83 nor a3, $0, a3
102 dmfc2 t0, 0x0201
103 dmfc2 t1, 0x0202
[all …]
/linux/drivers/media/usb/gspca/stv06xx/
H A Dstv06xx.c36 u8 len = (i2c_data > 0xff) ? 2 : 1; in stv06xx_write_bridge()
38 buf[0] = i2c_data & 0xff; in stv06xx_write_bridge()
39 buf[1] = (i2c_data >> 8) & 0xff; in stv06xx_write_bridge()
41 err = usb_control_msg(udev, usb_sndctrlpipe(udev, 0), in stv06xx_write_bridge()
42 0x04, 0x40, address, 0, buf, len, in stv06xx_write_bridge()
45 gspca_dbg(gspca_dev, D_CONF, "Written 0x%x to address 0x%x, status: %d\n", in stv06xx_write_bridge()
48 return (err < 0) ? err : 0; in stv06xx_write_bridge()
58 err = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0), in stv06xx_read_bridge()
59 0x04, 0xc0, address, 0, buf, 1, in stv06xx_read_bridge()
62 *i2c_data = buf[0]; in stv06xx_read_bridge()
[all …]
/linux/sound/hda/codecs/realtek/
H A Dalc882.c71 alc_update_coef_idx(codec, 7, 0, 0x2030); in alc889_fixup_coef()
93 static const hda_nid_t conn1[] = { 0x0c, 0x0d }; in alc889_fixup_dac_route()
94 static const hda_nid_t conn2[] = { 0x0e, 0x0f }; in alc889_fixup_dac_route()
95 snd_hda_override_conn_list(codec, 0x14, ARRAY_SIZE(conn1), conn1); in alc889_fixup_dac_route()
96 snd_hda_override_conn_list(codec, 0x15, ARRAY_SIZE(conn1), conn1); in alc889_fixup_dac_route()
97 snd_hda_override_conn_list(codec, 0x18, ARRAY_SIZE(conn2), conn2); in alc889_fixup_dac_route()
98 snd_hda_override_conn_list(codec, 0x1a, ARRAY_SIZE(conn2), conn2); in alc889_fixup_dac_route()
101 static const hda_nid_t conn[] = { 0x0c, 0x0d, 0x0e, 0x0f, 0x26 }; in alc889_fixup_dac_route()
102 snd_hda_override_conn_list(codec, 0x14, ARRAY_SIZE(conn), conn); in alc889_fixup_dac_route()
103 snd_hda_override_conn_list(codec, 0x15, ARRAY_SIZE(conn), conn); in alc889_fixup_dac_route()
[all …]
/linux/arch/arm/boot/dts/ti/omap/
H A Dam43xx-clocks.dtsi9 #clock-cells = <0>;
14 reg = <0x0040>;
18 #clock-cells = <0>;
23 reg = <0x0040>;
27 #clock-cells = <0>;
32 reg = <0x0040>;
36 #clock-cells = <0>;
45 #clock-cells = <0>;
54 #clock-cells = <0>;
63 #clock-cells = <0>;
[all …]
/linux/drivers/media/usb/em28xx/
H A Dem28xx-core.c43 } while (0)
53 } while (0)
60 } while (0)
71 int pipe = usb_rcvctrlpipe(udev, 0); in em28xx_read_reg_req_len()
82 0x0000, reg, dev->urb_buf, len, 1000); in em28xx_read_reg_req_len()
83 if (ret < 0) { in em28xx_read_reg_req_len()
84 …em28xx_regdbg("(pipe 0x%08x): IN: %02x %02x %02x %02x %02x %02x %02x %02x failed with error %i\n… in em28xx_read_reg_req_len()
87 req, 0, 0, in em28xx_read_reg_req_len()
88 reg & 0xff, reg >> 8, in em28xx_read_reg_req_len()
89 len & 0xff, len >> 8, ret); in em28xx_read_reg_req_len()
[all …]
/linux/drivers/net/wireless/intersil/p54/
H A Dp54usb.c45 {USB_DEVICE(0x0411, 0x0050)}, /* Buffalo WLI2-USB2-G54 */
46 {USB_DEVICE(0x045e, 0x00c2)}, /* Microsoft MN-710 */
47 {USB_DEVICE(0x0506, 0x0a11)}, /* 3COM 3CRWE254G72 */
48 {USB_DEVICE(0x0675, 0x0530)}, /* DrayTek Vigor 530 */
49 {USB_DEVICE(0x06b9, 0x0120)}, /* Thomson SpeedTouch 120g */
50 {USB_DEVICE(0x0707, 0xee06)}, /* SMC 2862W-G */
51 {USB_DEVICE(0x07aa, 0x001c)}, /* Corega CG-WLUSB2GT */
52 {USB_DEVICE(0x083a, 0x4501)}, /* Accton 802.11g WN4501 USB */
53 {USB_DEVICE(0x083a, 0x4502)}, /* Siemens Gigaset USB Adapter */
54 {USB_DEVICE(0x083a, 0x5501)}, /* Phillips CPWUA054 */
[all …]
/linux/drivers/net/ethernet/marvell/octeontx2/af/
H A Drvu_reg.h12 #define RVU_AF_MSIXTR_BASE (0x10)
13 #define RVU_AF_ECO (0x20)
14 #define RVU_AF_BLK_RST (0x30)
15 #define RVU_AF_PF_BAR4_ADDR (0x40)
16 #define RVU_AF_RAS (0x100)
17 #define RVU_AF_RAS_W1S (0x108)
18 #define RVU_AF_RAS_ENA_W1S (0x110)
19 #define RVU_AF_RAS_ENA_W1C (0x118)
20 #define RVU_AF_GEN_INT (0x120)
21 #define RVU_AF_GEN_INT_W1S (0x128)
[all …]
/linux/arch/arm/probes/
H A Ddecode-thumb.c20 DECODE_REJECT (0xfe4f0000, 0xe80f0000),
24 DECODE_REJECT (0xffc00000, 0xe8000000),
27 DECODE_REJECT (0xffc00000, 0xe9800000),
30 DECODE_REJECT (0xfe508000, 0xe8008000),
32 DECODE_REJECT (0xfe50c000, 0xe810c000),
34 DECODE_REJECT (0xfe402000, 0xe8002000),
40 DECODE_CUSTOM (0xfe400000, 0xe8000000, PROBES_T32_LDMSTM),
50 DECODE_OR (0xff600000, 0xe8600000),
53 DECODE_EMULATEX (0xff400000, 0xe9400000, PROBES_T32_LDRDSTRD,
54 REGS(NOPCWB, NOSPPC, NOSPPC, 0, 0)),
[all …]

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