/freebsd/sys/contrib/device-tree/src/arm64/freescale/ |
H A D | imx8mn-pinfunc.h | 14 …ne MX8MN_IOMUXC_BOOT_MODE2_CCMSRCGPCMIX_BOOT_MODE2 0x020 0x25C 0x000 0x0 0x0 15 …ne MX8MN_IOMUXC_BOOT_MODE2_I2C1_SCL 0x020 0x25C 0x55C 0x1 0x3 16 …ne MX8MN_IOMUXC_BOOT_MODE3_CCMSRCGPCMIX_BOOT_MODE3 0x024 0x260 0x000 0x0 0x0 17 …ne MX8MN_IOMUXC_BOOT_MODE3_I2C1_SDA 0x024 0x260 0x56C 0x1 0x3 18 …ne MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0 19 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x000 0x1 0x0 20 …ne MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0 21 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0 22 …ne MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0 23 …ne MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0 [all …]
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H A D | imx8mp-pinfunc.h | 13 #define MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x014 0x274 0x000 0x0 0x0 14 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT 0x014 0x274 0x000 0x1 0x0 15 #define MX8MP_IOMUXC_GPIO1_IO00__ISP_FL_TRIG_0 0x014 0x274 0x5D4 0x3 0x0 16 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1 0x014 0x274 0x000 0x6 0x0 17 #define MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x018 0x278 0x000 0x0 0x0 18 #define MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x018 0x278 0x000 0x1 0x0 19 #define MX8MP_IOMUXC_GPIO1_IO01__ISP_SHUTTER_TRIG_0 0x018 0x278 0x5DC 0x3 0x0 20 #define MX8MP_IOMUXC_GPIO1_IO01__CCM_EXT_CLK2 0x018 0x278 0x000 0x6 0x0 21 #define MX8MP_IOMUXC_GPIO1_IO02__GPIO1_IO02 0x01C 0x27C 0x000 0x0 0x0 22 #define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x01C 0x27C 0x000 0x1 0x0 [all …]
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H A D | imx8mm-pinfunc.h | 14 #define MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0… 15 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0… 16 #define MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0… 17 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0… 18 #define MX8MM_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0… 19 #define MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0… 20 #define MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0… 21 #define MX8MM_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0… 22 #define MX8MM_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0… 23 #define MX8MM_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0… [all …]
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H A D | imx8mq-pinfunc.h | 15 #define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0… 16 #define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0… 17 #define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0… 18 #define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0… 19 #define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0… 20 #define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0… 21 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0… 22 #define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0… 23 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0… 24 #define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0… [all …]
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/freebsd/sys/contrib/device-tree/include/dt-bindings/clock/ |
H A D | lpc18xx-ccu.h | 13 #define CLK_APB3_BUS 0x100 14 #define CLK_APB3_I2C1 0x108 15 #define CLK_APB3_DAC 0x110 16 #define CLK_APB3_ADC0 0x118 17 #define CLK_APB3_ADC1 0x120 18 #define CLK_APB3_CAN0 0x128 19 #define CLK_APB1_BUS 0x200 20 #define CLK_APB1_MOTOCON_PWM 0x208 21 #define CLK_APB1_I2C0 0x210 22 #define CLK_APB1_I2S 0x218 [all …]
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/freebsd/sys/contrib/device-tree/Bindings/pinctrl/ |
H A D | fsl,imx93-pinctrl.yaml | 76 reg = <0x30330000 0x10000>; 80 <0x48 0x1f8 0x41c 0x1 0x0 0x49>, 81 <0x4c 0x1fc 0x418 0x1 0x0 0x49>;
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/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/ |
H A D | imx50-pinfunc.h | 13 #define MX50_PAD_KEY_COL0__KPP_COL_0 0x020 0x2cc 0x000 0x0 0x0 14 #define MX50_PAD_KEY_COL0__GPIO4_0 0x020 0x2cc 0x000 0x1 0x0 15 #define MX50_PAD_KEY_COL0__EIM_NANDF_CLE 0x020 0x2cc 0x000 0x2 0x0 16 #define MX50_PAD_KEY_COL0__CTI_TRIGIN7 0x020 0x2cc 0x000 0x6 0x0 17 #define MX50_PAD_KEY_COL0__USBPHY1_TXREADY 0x020 0x2cc 0x000 0x7 0x0 18 #define MX50_PAD_KEY_ROW0__KPP_ROW_0 0x024 0x2d0 0x000 0x0 0x0 19 #define MX50_PAD_KEY_ROW0__GPIO4_1 0x024 0x2d0 0x000 0x1 0x0 20 #define MX50_PAD_KEY_ROW0__EIM_NANDF_ALE 0x024 0x2d0 0x000 0x2 0x0 21 #define MX50_PAD_KEY_ROW0__CTI_TRIGIN_ACK7 0x024 0x2d0 0x000 0x6 0x0 22 #define MX50_PAD_KEY_ROW0__USBPHY1_RXVALID 0x024 0x2d0 0x000 0x7 0x0 [all …]
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H A D | imx53-pinfunc.h | 13 #define MX53_PAD_GPIO_19__KPP_COL_5 0x020 0x348 0x840 0x0 0x0 14 #define MX53_PAD_GPIO_19__GPIO4_5 0x020 0x348 0x000 0x1 0x0 15 #define MX53_PAD_GPIO_19__CCM_CLKO 0x020 0x348 0x000 0x2 0x0 16 #define MX53_PAD_GPIO_19__SPDIF_OUT1 0x020 0x348 0x000 0x3 0x0 17 #define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 0x020 0x348 0x000 0x4 0x0 18 #define MX53_PAD_GPIO_19__ECSPI1_RDY 0x020 0x348 0x000 0x5 0x0 19 #define MX53_PAD_GPIO_19__FEC_TDATA_3 0x020 0x348 0x000 0x6 0x0 20 #define MX53_PAD_GPIO_19__SRC_INT_BOOT 0x020 0x348 0x000 0x7 0x0 21 #define MX53_PAD_KEY_COL0__KPP_COL_0 0x024 0x34c 0x000 0x0 0x0 22 #define MX53_PAD_KEY_COL0__GPIO4_6 0x024 0x34c 0x000 0x1 0x0 [all …]
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H A D | imx6sl-pinfunc.h | 13 #define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x04c 0x2a4 0x000 0x0 0x0 14 #define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0 15 #define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x0 16 #define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0 17 #define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0 18 #define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x0 19 #define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x04c 0x2a4 0x7f4 0x6 0x0 20 #define MX6SL_PAD_AUD_RXC__AUD3_RXC 0x050 0x2a8 0x000 0x0 0x0 21 #define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0 22 #define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0 [all …]
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H A D | imx51-pinfunc.h | 13 #define MX51_PAD_EIM_D16__AUD4_RXFS 0x05c 0x3f0 0x000 0x5 0x0 14 #define MX51_PAD_EIM_D16__AUD5_TXD 0x05c 0x3f0 0x8d8 0x7 0x0 15 #define MX51_PAD_EIM_D16__EIM_D16 0x05c 0x3f0 0x000 0x0 0x0 16 #define MX51_PAD_EIM_D16__GPIO2_0 0x05c 0x3f0 0x000 0x1 0x0 17 #define MX51_PAD_EIM_D16__I2C1_SDA 0x05c 0x3f0 0x9b4 0x4 0x0 18 #define MX51_PAD_EIM_D16__UART2_CTS 0x05c 0x3f0 0x000 0x3 0x0 19 #define MX51_PAD_EIM_D16__USBH2_DATA0 0x05c 0x3f0 0x000 0x2 0x0 20 #define MX51_PAD_EIM_D17__AUD5_RXD 0x060 0x3f4 0x8d4 0x7 0x0 21 #define MX51_PAD_EIM_D17__EIM_D17 0x060 0x3f4 0x000 0x0 0x0 22 #define MX51_PAD_EIM_D17__GPIO2_1 0x060 0x3f4 0x000 0x1 0x0 [all …]
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H A D | imxrt1170-pinfunc.h | 10 #define IMX_PAD_SION 0x40000000 17 #define IOMUXC_GPIO_LPSR_00_FLEXCAN3_TX 0x000 0x040 0x0 0x0 0x0 18 #define IOMUXC_GPIO_LPSR_00_MIC_CLK 0x000 0x040 0x0 0x1 0x0 19 #define IOMUXC_GPIO_LPSR_00_MQS_RIGHT 0x000 0x040 0x0 0x2 0x0 20 #define IOMUXC_GPIO_LPSR_00_ARM_CM4_EVENTO 0x000 0x040 0x0 0x3 0x0 21 #define IOMUXC_GPIO_LPSR_00_GPIO_MUX6_IO00 0x000 0x040 0x0 0x5 0x0 22 #define IOMUXC_GPIO_LPSR_00_LPUART12_TXD 0x000 0x040 0x0B0 0x6 0x0 23 #define IOMUXC_GPIO_LPSR_00_SAI4_MCLK 0x000 0x040 0x0C8 0x7 0x0 24 #define IOMUXC_GPIO_LPSR_00_GPIO12_IO00 0x000 0x040 0x0 0xA 0x0 26 #define IOMUXC_GPIO_LPSR_01_FLEXCAN3_RX 0x004 0x044 0x080 0x0 0x0 [all …]
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H A D | imx6q-pinfunc.h | 13 #define MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x04c 0x360 0x000 0x0 0x0 14 #define MX6QDL_PAD_SD2_DAT1__ECSPI5_SS0 0x04c 0x360 0x834 0x1 0x0 15 #define MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0x04c 0x360 0x000 0x2 0x0 16 #define MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x04c 0x360 0x7c8 0x3 0x0 17 #define MX6QDL_PAD_SD2_DAT1__KEY_COL7 0x04c 0x360 0x8f0 0x4 0x0 18 #define MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x04c 0x360 0x000 0x5 0x0 19 #define MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x050 0x364 0x000 0x0 0x0 20 #define MX6QDL_PAD_SD2_DAT2__ECSPI5_SS1 0x050 0x364 0x838 0x1 0x0 21 #define MX6QDL_PAD_SD2_DAT2__EIM_CS3_B 0x050 0x364 0x000 0x2 0x0 22 #define MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x050 0x364 0x7b8 0x3 0x0 [all …]
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H A D | imx6dl-pinfunc.h | 13 #define MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x04c 0x360 0x000 0x0 0x0 14 #define MX6QDL_PAD_CSI0_DAT10__AUD3_RXC 0x04c 0x360 0x000 0x1 0x0 15 #define MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x04c 0x360 0x7f8 0x2 0x0 16 #define MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x04c 0x360 0x000 0x3 0x0 17 #define MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x04c 0x360 0x8fc 0x3 0x0 18 #define MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x04c 0x360 0x000 0x5 0x0 19 #define MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x04c 0x360 0x000 0x7 0x0 20 #define MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x050 0x364 0x000 0x0 0x0 21 #define MX6QDL_PAD_CSI0_DAT11__AUD3_RXFS 0x050 0x364 0x000 0x1 0x0 22 #define MX6QDL_PAD_CSI0_DAT11__ECSPI2_SS0 0x050 0x364 0x800 0x2 0x0 [all …]
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H A D | imxrt1050-pinfunc.h | 10 #define IMX_PAD_SION 0x40000000 17 #define MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00 0x014 0x204 0x000 0x0 0x0 18 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A 0x014 0x204 0x494 0x1 0x0 19 #define MXRT1050_IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x014 0x204 0x500 0x2 0x1 20 #define MXRT1050_IOMUXC_GPIO_EMC_00_XBAR_INOUT2 0x014 0x204 0x60C 0x3 0x0 21 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXIO1_D00 0x014 0x204 0x000 0x4 0x0 22 #define MXRT1050_IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x014 0x204 0x000 0x5 0x0 24 #define MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01 0x018 0x208 0x000 0x0 0x0 25 #define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B 0x018 0x208 0x000 0x1 0x0 26 #define MXRT1050_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x018 0x208 0x4FC 0x2 0x1 [all …]
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/freebsd/sys/dev/ntb/ntb_hw/ |
H A D | ntb_hw_amd.h | 48 #define NTB_HW_AMD_VENDOR_ID 0x1022 49 #define NTB_HW_AMD_DEVICE_ID1 0x145B 50 #define NTB_HW_AMD_DEVICE_ID2 0x148B 52 #define NTB_HW_HYGON_VENDOR_ID 0x19D4 53 #define NTB_HW_HYGON_DEVICE_ID1 0x145B 56 #define NTB_DEF_PEER_IDX 0 61 #define NTB_LIN_STA_ACTIVE_BIT 0x00000002 62 #define NTB_LNK_STA_SPEED_MASK 0x000F0000 63 #define NTB_LNK_STA_WIDTH_MASK 0x03F00000 87 #define QUIRK_MW0_32BIT 0x01 [all …]
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/freebsd/sys/dev/dwc/ |
H A D | dwc1000_reg.h | 37 #define MAC_CONFIGURATION 0x0 47 #define MAC_FRAME_FILTER 0x4 53 #define FRAME_FILTER_PR (1 << 0) /* All Incoming Frames */ 54 #define GMAC_MAC_HTHIGH 0x08 55 #define GMAC_MAC_HTLOW 0x0c 56 #define GMII_ADDRESS 0x10 57 #define GMII_ADDRESS_PA_MASK 0x1f /* Phy device */ 59 #define GMII_ADDRESS_GR_MASK 0x1f /* Phy register */ 61 #define GMII_ADDRESS_CR_MASK 0xf 64 #define GMII_ADDRESS_GB (1 << 0) /* Busy */ [all …]
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/freebsd/sys/arm/nvidia/drm2/ |
H A D | tegra_dc_reg.h | 37 #define DC_CMD_GENERAL_INCR_SYNCPT 0x000 38 #define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL 0x001 40 #define SYNCPT_CNTRL_SOFT_RESET (1 << 0) 42 #define DC_CMD_GENERAL_INCR_SYNCPT_ERROR 0x002 43 #define DC_CMD_WIN_A_INCR_SYNCPT 0x008 44 #define DC_CMD_WIN_A_INCR_SYNCPT_CNTRL 0x009 45 #define DC_CMD_WIN_A_INCR_SYNCPT_ERROR 0x00a 46 #define DC_CMD_WIN_B_INCR_SYNCPT 0x010 47 #define DC_CMD_WIN_B_INCR_SYNCPT_CNTRL 0x011 48 #define DC_CMD_WIN_B_INCR_SYNCPT_ERROR 0x012 [all …]
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/freebsd/sys/dev/mge/ |
H A D | if_mgevar.h | 43 #define MGE_RX_DEFAULT_QUEUE 0 48 #define MGE_IC_RX 0 119 #define MGE_READ(sc,reg) bus_read_4((sc)->res[0], (reg)) 120 #define MGE_WRITE(sc,reg,val) bus_write_4((sc)->res[0], (reg), (val)) 126 } while (0) 134 } while (0) 144 } while (0) 149 } while (0) 154 } while (0) 159 } while (0) [all …]
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/freebsd/sys/contrib/device-tree/src/arm/ti/omap/ |
H A D | am57xx-idk-common.dtsi | 64 gpios = <&tpic2810 0 GPIO_ACTIVE_HIGH>; 111 hdmi0: connector@0 { 124 tpd12s015: encoder@0 { 127 gpios = <0>, /* optional CT_CP_HPD */ 128 <0>, /* optional LS_OE */ 133 #size-cells = <0>; 135 port@0 { 136 reg = <0>; 138 tpd12s015_in: endpoint@0 { 146 tpd12s015_out: endpoint@0 { [all …]
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/freebsd/sys/dev/gpio/ |
H A D | pl061.c | 58 #if 0 61 } while (0) 67 #define PL061_DATA 0x3FC 68 #define PL061_DIR 0x400 69 #define PL061_INTSENSE 0x404 70 #define PL061_INTBOTHEDGES 0x408 71 #define PL061_INTEVENT 0x40C 72 #define PL061_INTMASK 0x410 73 #define PL061_RAWSTATUS 0x414 74 #define PL061_STATUS 0x418 [all …]
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/freebsd/sys/contrib/dev/ath/ath_hal/ar9300/ |
H A D | osprey_reg_map.h | 86 volatile char pad__0[0x8]; /* 0x0 - 0x8 */ 87 volatile u_int32_t MAC_DMA_CR; /* 0x8 - 0xc */ 88 volatile char pad__1[0x8]; /* 0xc - 0x14 */ 89 volatile u_int32_t MAC_DMA_CFG; /* 0x14 - 0x18 */ 90 volatile u_int32_t MAC_DMA_RXBUFPTR_THRESH; /* 0x18 - 0x1c */ 91 volatile u_int32_t MAC_DMA_TXDPPTR_THRESH; /* 0x1c - 0x20 */ 92 volatile u_int32_t MAC_DMA_MIRT; /* 0x20 - 0x24 */ 93 volatile u_int32_t MAC_DMA_GLOBAL_IER; /* 0x24 - 0x28 */ 94 volatile u_int32_t MAC_DMA_TIMT; /* 0x28 - 0x2c */ 95 volatile u_int32_t MAC_DMA_RIMT; /* 0x2c - 0x30 */ [all …]
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H A D | scorpion_reg_map.h | 77 volatile char pad__0[0x8]; /* 0x0 - 0x8 */ 78 volatile u_int32_t MAC_DMA_CR; /* 0x8 - 0xc */ 79 volatile char pad__1[0x8]; /* 0xc - 0x14 */ 80 volatile u_int32_t MAC_DMA_CFG; /* 0x14 - 0x18 */ 81 volatile u_int32_t MAC_DMA_RXBUFPTR_THRESH; /* 0x18 - 0x1c */ 82 volatile u_int32_t MAC_DMA_TXDPPTR_THRESH; /* 0x1c - 0x20 */ 83 volatile u_int32_t MAC_DMA_MIRT; /* 0x20 - 0x24 */ 84 volatile u_int32_t MAC_DMA_GLOBAL_IER; /* 0x24 - 0x28 */ 85 volatile u_int32_t MAC_DMA_TIMT; /* 0x28 - 0x2c */ 86 volatile u_int32_t MAC_DMA_RIMT; /* 0x2c - 0x30 */ [all …]
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/freebsd/sys/dev/rtwn/rtl8192c/ |
H A D | r92c_reg.h | 28 #define R92C_SYS_ISO_CTRL 0x000 29 #define R92C_SYS_FUNC_EN 0x002 30 #define R92C_APS_FSMCO 0x004 31 #define R92C_SYS_CLKR 0x008 32 #define R92C_AFE_MISC 0x010 33 #define R92C_SPS0_CTRL 0x011 34 #define R92C_SPS_OCP_CFG 0x018 35 #define R92C_RSV_CTRL 0x01c 36 #define R92C_RF_CTRL 0x01f 37 #define R92C_LDOA15_CTRL 0x020 [all …]
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/freebsd/sys/dev/wpi/ |
H A D | if_wpireg.h | 43 #define WPI_RING_DMA_ALIGN 0x4000 51 #define WPI_HW_IF_CONFIG 0x000 52 #define WPI_INT 0x008 53 #define WPI_INT_MASK 0x00c 54 #define WPI_FH_INT 0x010 55 #define WPI_GPIO_IN 0x018 56 #define WPI_RESET 0x020 57 #define WPI_GP_CNTRL 0x024 58 #define WPI_EEPROM 0x02c 59 #define WPI_EEPROM_GP 0x030 [all …]
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/freebsd/tools/tools/cxgbtool/ |
H A D | reg_defs.c | 7 { "SG_CONTROL", 0x0, 0 }, 8 { "CmdQ0_Enable", 0, 1 }, 24 { "SG_DOORBELL", 0x4, 0 }, 25 { "CmdQ0_Enable", 0, 1 }, 29 { "SG_CMD0BASELWR", 0x8, 0 }, 30 { "SG_CMD0BASEUPR", 0xc, 0 }, 31 { "SG_CMD1BASELWR", 0x10, 0 }, 32 { "SG_CMD1BASEUPR", 0x14, 0 }, 33 { "SG_FL0BASELWR", 0x18, 0 }, 34 { "SG_FL0BASEUPR", 0x1c, 0 }, [all …]
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