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/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dfsl,mpic-msi.yaml145 reg = <0x41600 0x80>;
146 msi-available-ranges = <0 0x100>;
147 interrupts = <0xe0 0>, <0xe1 0>, <0xe2 0>, <0xe3 0>,
148 <0xe4 0>, <0xe5 0>, <0xe6 0>, <0xe7 0>;
154 reg = <0x41600 0x200>, <0x44148 4>;
155 interrupts = <0xe0 0 0 0>, <0xe1 0 0 0>, <0xe2 0 0 0>, <0xe3 0 0 0>,
156 <0xe4 0 0 0>, <0xe5 0 0 0>, <0xe6 0 0 0>, <0xe7 0 0 0>,
157 <0x100 0 0 0>, <0x101 0 0 0>, <0x102 0 0 0>, <0x103 0 0 0>,
158 <0x104 0 0 0>, <0x105 0 0 0>, <0x106 0 0 0>, <0x107 0 0 0>;
/linux/arch/powerpc/boot/dts/fsl/
H A Dpq3-mpic.dtsi2 * PQ3 MPIC device tree stub [ controller @ offset 0x40000 ]
37 #address-cells = <0>;
39 reg = <0x40000 0x40000>;
49 reg = <0x41100 0x100 0x41300 4>;
50 interrupts = <0 0 3 0
51 1 0 3 0
52 2 0 3 0
53 3 0 3 0>;
58 reg = <0x41400 0x200>;
60 0xb0 2 0 0
[all …]
H A Dqoriq-mpic.dtsi2 * QorIQ MPIC device tree stub [ controller @ offset 0x40000 ]
37 #address-cells = <0>;
39 reg = <0x40000 0x40000>;
42 clock-frequency = <0x0>;
47 reg = <0x41100 0x100 0x41300 4>;
48 interrupts = <0 0 3 0
49 1 0 3 0
50 2 0 3 0
51 3 0 3 0>;
56 reg = <0x41600 0x200 0x44140 4>;
[all …]
H A Dqoriq-mpic4.3.dtsi2 * QorIQ MPIC device tree stub [ controller @ offset 0x40000 ]
37 #address-cells = <0>;
39 reg = <0x40000 0x40000>;
42 clock-frequency = <0x0>;
47 reg = <0x41100 0x100 0x41300 4>;
48 interrupts = <0 0 3 0
49 1 0 3 0
50 2 0 3 0
51 3 0 3 0>;
56 reg = <0x41600 0x200 0x44148 4>;
[all …]
/linux/arch/powerpc/boot/dts/
H A Dxpedite5301.dts16 boot-bank = <0x0>; /* 0: Primary flash, 1: Secondary flash */
29 #size-cells = <0>;
31 PowerPC,8572@0 {
33 reg = <0x0>;
36 d-cache-size = <0x8000>; // L1, 32K
37 i-cache-size = <0x8000>; // L1, 32K
38 timebase-frequency = <0>;
39 bus-frequency = <0>;
40 clock-frequency = <0>;
46 reg = <0x1>;
[all …]
H A Dxpedite5370.dts27 #size-cells = <0>;
29 PowerPC,8572@0 {
31 reg = <0x0>;
34 d-cache-size = <0x8000>; // L1, 32K
35 i-cache-size = <0x8000>; // L1, 32K
36 timebase-frequency = <0>;
37 bus-frequency = <0>;
38 clock-frequency = <0>;
44 reg = <0x1>;
47 d-cache-size = <0x8000>; // L1, 32K
[all …]
H A Dxcalibur1501.dts28 #size-cells = <0>;
30 PowerPC,8572@0 {
32 reg = <0x0>;
35 d-cache-size = <0x8000>; // L1, 32K
36 i-cache-size = <0x8000>; // L1, 32K
37 timebase-frequency = <0>;
38 bus-frequency = <0>;
39 clock-frequency = <0>;
45 reg = <0x1>;
48 d-cache-size = <0x8000>; // L1, 32K
[all …]
H A Dxpedite5330.dts16 boot-bank = <0x0>; /* 0: Primary flash, 1: Secondary flash */
30 #size-cells = <0>;
32 pmcslot@0 {
33 cell-index = <0>;
44 #size-cells = <0>;
46 xmcslot@0 {
47 cell-index = <0>;
65 #size-cells = <0>;
67 PowerPC,8572@0 {
69 reg = <0x0>;
[all …]