Home
last modified time | relevance | path

Searched +full:0 +full:x40a0 (Results 1 – 25 of 29) sorted by relevance

12

/linux/Documentation/devicetree/bindings/soc/ti/
H A Dti,j721e-system-controller.yaml49 "^mux-controller@[0-9a-f]+$":
54 "^clock-controller@[0-9a-f]+$":
60 "phy@[0-9a-f]+$":
66 "^chipid@[0-9a-f]+$":
72 "^pcie-ctrl@[0-9a-f]+$":
77 "^clock@[0-9a-f]+$":
83 "^dss-oldi-io-ctrl@[0-9a-f]+$":
102 reg = <0x00100000 0x1c000>;
109 reg = <0x00004080 0x50>;
113 <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
[all …]
/linux/lib/crc/
H A Dcrc-t10dif-main.c17 * gt: 0x8bb7
20 0x0000, 0x8BB7, 0x9CD9, 0x176E, 0xB205, 0x39B2, 0x2EDC, 0xA56B,
21 0xEFBD, 0x640A, 0x7364, 0xF8D3, 0x5DB8, 0xD60F, 0xC161, 0x4AD6,
22 0x54CD, 0xDF7A, 0xC814, 0x43A3, 0xE6C8, 0x6D7F, 0x7A11, 0xF1A6,
23 0xBB70, 0x30C7, 0x27A9, 0xAC1E, 0x0975, 0x82C2, 0x95AC, 0x1E1B,
24 0xA99A, 0x222D, 0x3543, 0xBEF4, 0x1B9F, 0x9028, 0x8746, 0x0CF1,
25 0x4627, 0xCD90, 0xDAFE, 0x5149, 0xF422, 0x7F95, 0x68FB, 0xE34C,
26 0xFD57, 0x76E0, 0x618E, 0xEA39, 0x4F52, 0xC4E5, 0xD38B, 0x583C,
27 0x12EA, 0x995D, 0x8E33, 0x0584, 0xA0EF, 0x2B58, 0x3C36, 0xB781,
28 0xD883, 0x5334, 0x445A, 0xCFED, 0x6A86, 0xE131, 0xF65F, 0x7DE8,
[all …]
/linux/drivers/net/ethernet/tehuti/
H A Dtn40_regs.h8 #define TN40_REGS_SIZE 0x10000
10 /* Registers from 0x0000-0x00fc were remapped to 0x4000-0x40fc */
11 #define TN40_REG_TXD_CFG1_0 0x4000
12 #define TN40_REG_TXD_CFG1_1 0x4004
13 #define TN40_REG_TXD_CFG1_2 0x4008
14 #define TN40_REG_TXD_CFG1_3 0x400C
16 #define TN40_REG_RXF_CFG1_0 0x4010
17 #define TN40_REG_RXF_CFG1_1 0x4014
18 #define TN40_REG_RXF_CFG1_2 0x4018
19 #define TN40_REG_RXF_CFG1_3 0x401C
[all …]
H A Dtehuti.h81 # define L32_64(x) (u32) ((u64)(x) & 0xffffffff)
83 # define H32_64(x) 0
105 # define NETDEV_TX_OK 0
134 #define GET_INT_COAL(x) GET_BITS_SHIFT(x, 15, 0)
189 * if len == 0 addr is dma
190 * if len != 0 addr is skb */
207 u64 InUCast; /* 0x7200 */
208 u64 InMCast; /* 0x7210 */
209 u64 InBCast; /* 0x7220 */
210 u64 InPkts; /* 0x7230 */
[all …]
/linux/drivers/gpu/drm/radeon/reg_srcs/
H A Drv5151 rv515 0x6d40
2 0x1434 SRC_Y_X
3 0x1438 DST_Y_X
4 0x143C DST_HEIGHT_WIDTH
5 0x146C DP_GUI_MASTER_CNTL
6 0x1474 BRUSH_Y_X
7 0x1478 DP_BRUSH_BKGD_CLR
8 0x147C DP_BRUSH_FRGD_CLR
9 0x1480 BRUSH_DATA0
10 0x1484 BRUSH_DATA1
[all …]
/linux/arch/arm/boot/dts/nxp/mxs/
H A Dimx28-pinfunc.h13 #define MX28_PAD_GPMI_D00__GPMI_D0 0x0000
14 #define MX28_PAD_GPMI_D01__GPMI_D1 0x0010
15 #define MX28_PAD_GPMI_D02__GPMI_D2 0x0020
16 #define MX28_PAD_GPMI_D03__GPMI_D3 0x0030
17 #define MX28_PAD_GPMI_D04__GPMI_D4 0x0040
18 #define MX28_PAD_GPMI_D05__GPMI_D5 0x0050
19 #define MX28_PAD_GPMI_D06__GPMI_D6 0x0060
20 #define MX28_PAD_GPMI_D07__GPMI_D7 0x0070
21 #define MX28_PAD_GPMI_CE0N__GPMI_CE0N 0x0100
22 #define MX28_PAD_GPMI_CE1N__GPMI_CE1N 0x0110
[all …]
/linux/include/video/
H A Dsamsung_fimd.h18 #define VIDCON0 0x00
21 #define VIDCON0_VIDOUT_MASK (0x7 << 26)
23 #define VIDCON0_VIDOUT_RGB (0x0 << 26)
24 #define VIDCON0_VIDOUT_TV (0x1 << 26)
25 #define VIDCON0_VIDOUT_I80_LDI0 (0x2 << 26)
26 #define VIDCON0_VIDOUT_I80_LDI1 (0x3 << 26)
27 #define VIDCON0_VIDOUT_WB_RGB (0x4 << 26)
28 #define VIDCON0_VIDOUT_WB_I80_LDI0 (0x6 << 26)
29 #define VIDCON0_VIDOUT_WB_I80_LDI1 (0x7 << 26)
31 #define VIDCON0_L1_DATA_MASK (0x7 << 23)
[all …]
/linux/drivers/media/dvb-frontends/
H A Ds5h1411.c42 } while (0)
50 { S5H1411_I2C_TOP_ADDR, 0x00, 0x0071, },
51 { S5H1411_I2C_TOP_ADDR, 0x08, 0x0047, },
52 { S5H1411_I2C_TOP_ADDR, 0x1c, 0x0400, },
53 { S5H1411_I2C_TOP_ADDR, 0x1e, 0x0370, },
54 { S5H1411_I2C_TOP_ADDR, 0x1f, 0x342c, },
55 { S5H1411_I2C_TOP_ADDR, 0x24, 0x0231, },
56 { S5H1411_I2C_TOP_ADDR, 0x25, 0x1011, },
57 { S5H1411_I2C_TOP_ADDR, 0x26, 0x0f07, },
58 { S5H1411_I2C_TOP_ADDR, 0x27, 0x0f04, },
[all …]
/linux/drivers/clk/imx/
H A Dclk-imx8mn.c334 hws[IMX8MN_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx8mn_clocks_probe()
343 base = devm_of_iomap(dev, np, 0, NULL); in imx8mn_clocks_probe()
350 …hws[IMX8MN_AUDIO_PLL1_REF_SEL] = imx_clk_hw_mux("audio_pll1_ref_sel", base + 0x0, 0, 2, pll_ref_se… in imx8mn_clocks_probe()
351 …hws[IMX8MN_AUDIO_PLL2_REF_SEL] = imx_clk_hw_mux("audio_pll2_ref_sel", base + 0x14, 0, 2, pll_ref_s… in imx8mn_clocks_probe()
352 …hws[IMX8MN_VIDEO_PLL_REF_SEL] = imx_clk_hw_mux("video_pll_ref_sel", base + 0x28, 0, 2, pll_ref_sel… in imx8mn_clocks_probe()
353 …hws[IMX8MN_DRAM_PLL_REF_SEL] = imx_clk_hw_mux("dram_pll_ref_sel", base + 0x50, 0, 2, pll_ref_sels,… in imx8mn_clocks_probe()
354 …hws[IMX8MN_GPU_PLL_REF_SEL] = imx_clk_hw_mux("gpu_pll_ref_sel", base + 0x64, 0, 2, pll_ref_sels, A… in imx8mn_clocks_probe()
355 …hws[IMX8MN_M7_ALT_PLL_REF_SEL] = imx_clk_hw_mux("m7_alt_pll_ref_sel", base + 0x74, 0, 2, pll_ref_s… in imx8mn_clocks_probe()
356 …hws[IMX8MN_ARM_PLL_REF_SEL] = imx_clk_hw_mux("arm_pll_ref_sel", base + 0x84, 0, 2, pll_ref_sels, A… in imx8mn_clocks_probe()
357 …hws[IMX8MN_SYS_PLL3_REF_SEL] = imx_clk_hw_mux("sys_pll3_ref_sel", base + 0x114, 0, 2, pll_ref_sels… in imx8mn_clocks_probe()
[all …]
H A Dclk-imx8mm.c314 hws[IMX8MM_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0); in imx8mm_clocks_probe()
323 base = of_iomap(np, 0); in imx8mm_clocks_probe()
328 …hws[IMX8MM_AUDIO_PLL1_REF_SEL] = imx_clk_hw_mux("audio_pll1_ref_sel", base + 0x0, 0, 2, pll_ref_se… in imx8mm_clocks_probe()
329 …hws[IMX8MM_AUDIO_PLL2_REF_SEL] = imx_clk_hw_mux("audio_pll2_ref_sel", base + 0x14, 0, 2, pll_ref_s… in imx8mm_clocks_probe()
330 …hws[IMX8MM_VIDEO_PLL1_REF_SEL] = imx_clk_hw_mux("video_pll1_ref_sel", base + 0x28, 0, 2, pll_ref_s… in imx8mm_clocks_probe()
331 …hws[IMX8MM_DRAM_PLL_REF_SEL] = imx_clk_hw_mux("dram_pll_ref_sel", base + 0x50, 0, 2, pll_ref_sels,… in imx8mm_clocks_probe()
332 …hws[IMX8MM_GPU_PLL_REF_SEL] = imx_clk_hw_mux("gpu_pll_ref_sel", base + 0x64, 0, 2, pll_ref_sels, A… in imx8mm_clocks_probe()
333 …hws[IMX8MM_VPU_PLL_REF_SEL] = imx_clk_hw_mux("vpu_pll_ref_sel", base + 0x74, 0, 2, pll_ref_sels, A… in imx8mm_clocks_probe()
334 …hws[IMX8MM_ARM_PLL_REF_SEL] = imx_clk_hw_mux("arm_pll_ref_sel", base + 0x84, 0, 2, pll_ref_sels, A… in imx8mm_clocks_probe()
335 …hws[IMX8MM_SYS_PLL3_REF_SEL] = imx_clk_hw_mux("sys_pll3_ref_sel", base + 0x114, 0, 2, pll_ref_sels… in imx8mm_clocks_probe()
[all …]
/linux/drivers/net/wireless/realtek/rtw89/
H A Drtw8922a.c26 {2, 1641, grp_0}, /* ACH 0 */
38 {0, 0, 0}, /* FWCMDQ */
39 {0, 0, 0}, /* BMC */
40 {0, 0, 0}, /* H2D */
44 1651, /* Group 0 */
47 0, /* WP threshold */
61 {54, 222, grp_0}, /* ACH 0 */
62 {0, 0, grp_0}, /* ACH 1 */
64 {0, 0, grp_0}, /* ACH 3 */
66 {0, 0, grp_0}, /* ACH 5 */
[all …]
H A Drtw8851b_table.c11 {0x704, 0x601E0500},
12 {0x4000, 0x00000000},
13 {0x4004, 0xCA014000},
14 {0x4008, 0xC751D4F0},
15 {0x400C, 0x44511475},
16 {0x4010, 0x00000000},
17 {0x4014, 0x00000000},
18 {0x47BC, 0x00000380},
19 {0x4018, 0x4F4C084B},
20 {0x401C, 0x084A4E52},
[all …]
/linux/tools/perf/pmu-events/arch/powerpc/power9/
H A Dother.json3 "EventCode": "0x3084",
8 "EventCode": "0xF880",
13 "EventCode": "0x4088",
18 "EventCode": "0x20A4",
23 "EventCode": "0x40008",
28 "EventCode": "0x20064",
33 "EventCode": "0x260B4",
38 "EventCode": "0x20006",
43 "EventCode": "0x201E4",
48 "EventCode": "0x4E044",
[all …]
/linux/drivers/pinctrl/tegra/
H A Dpinctrl-tegra234.c1432 .mux_bit = 0, \
1446 #define drive_soc_gpio08_pb0 DRV_PINGROUP_ENTRY_Y(0x500c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1447 #define drive_soc_gpio36_pm5 DRV_PINGROUP_ENTRY_Y(0x10004, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1448 #define drive_soc_gpio53_pm6 DRV_PINGROUP_ENTRY_Y(0x1000c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1449 #define drive_soc_gpio55_pm4 DRV_PINGROUP_ENTRY_Y(0x10014, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1450 #define drive_soc_gpio38_pm7 DRV_PINGROUP_ENTRY_Y(0x1001c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1451 #define drive_soc_gpio39_pn1 DRV_PINGROUP_ENTRY_Y(0x10024, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1452 #define drive_soc_gpio40_pn2 DRV_PINGROUP_ENTRY_Y(0x1002c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1453 #define drive_dp_aux_ch0_hpd_pm0 DRV_PINGROUP_ENTRY_Y(0x10034, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1454 #define drive_dp_aux_ch1_hpd_pm1 DRV_PINGROUP_ENTRY_Y(0x1003c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
[all …]
H A Dpinctrl-tegra238.c1595 .mux_bit = 0, \
1608 #define drive_soc_gpio36_pt1 DRV_PINGROUP_ENTRY_Y(0x10004, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1609 #define drive_soc_gpio53_pt2 DRV_PINGROUP_ENTRY_Y(0x1000c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1610 #define drive_soc_gpio38_pt3 DRV_PINGROUP_ENTRY_Y(0x1001c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1611 #define drive_soc_gpio40_pt4 DRV_PINGROUP_ENTRY_Y(0x1002c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1612 #define drive_soc_gpio75_ps2 DRV_PINGROUP_ENTRY_Y(0x10034, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1613 #define drive_soc_gpio81_pt0 DRV_PINGROUP_ENTRY_Y(0x1003c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1614 #define drive_soc_gpio78_ps5 DRV_PINGROUP_ENTRY_Y(0x10044, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1615 #define drive_soc_gpio34_pt5 DRV_PINGROUP_ENTRY_Y(0x1004c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1616 #define drive_gen7_i2c_scl_ps3 DRV_PINGROUP_ENTRY_Y(0x100a4, 12, 5, 20, 5, -1, -1, -1, -1, 0)
[all …]
H A Dpinctrl-tegra194.c1333 .mux_bit = 0, \
1348 …efine drive_soc_gpio33_pt0 DRV_PINGROUP_ENTRY_Y(0x1004, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1349 …efine drive_soc_gpio32_ps7 DRV_PINGROUP_ENTRY_Y(0x100c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1350 …efine drive_soc_gpio31_ps6 DRV_PINGROUP_ENTRY_Y(0x1014, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1351 …efine drive_soc_gpio30_ps5 DRV_PINGROUP_ENTRY_Y(0x101c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1352 …efine drive_aud_mclk_ps4 DRV_PINGROUP_ENTRY_Y(0x1024, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1353 …efine drive_dap1_fs_ps3 DRV_PINGROUP_ENTRY_Y(0x102c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1354 …efine drive_dap1_din_ps2 DRV_PINGROUP_ENTRY_Y(0x1034, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1355 …efine drive_dap1_dout_ps1 DRV_PINGROUP_ENTRY_Y(0x103c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1356 …efine drive_dap1_sclk_ps0 DRV_PINGROUP_ENTRY_Y(0x1044, 12, 5, 20, 5, -1, -1, -1, -1, 0)
[all …]
/linux/sound/soc/mediatek/mt8195/
H A Dmt8195-reg.h13 #define AFE_SRAM_BASE (0x10880000)
14 #define AFE_SRAM_SIZE (0x10000)
16 #define AUDIO_TOP_CON0 (0x0000)
17 #define AUDIO_TOP_CON1 (0x0004)
18 #define AUDIO_TOP_CON2 (0x0008)
19 #define AUDIO_TOP_CON3 (0x000c)
20 #define AUDIO_TOP_CON4 (0x0010)
21 #define AUDIO_TOP_CON5 (0x0014)
22 #define AUDIO_TOP_CON6 (0x0018)
23 #define AFE_MAS_HADDR_MSB (0x0020)
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_d.h26 #define ixATTR00 0x0000
27 #define ixATTR01 0x0001
28 #define ixATTR02 0x0002
29 #define ixATTR03 0x0003
30 #define ixATTR04 0x0004
31 #define ixATTR05 0x0005
32 #define ixATTR06 0x0006
33 #define ixATTR07 0x0007
34 #define ixATTR08 0x0008
35 #define ixATTR09 0x0009
[all …]
H A Ddce_8_0_d.h27 #define mmPIPE0_PG_CONFIG 0x1760
28 #define mmPIPE0_PG_ENABLE 0x1761
29 #define mmPIPE0_PG_STATUS 0x1762
30 #define mmPIPE1_PG_CONFIG 0x1764
31 #define mmPIPE1_PG_ENABLE 0x1765
32 #define mmPIPE1_PG_STATUS 0x1766
33 #define mmPIPE2_PG_CONFIG 0x1768
34 #define mmPIPE2_PG_ENABLE 0x1769
35 #define mmPIPE2_PG_STATUS 0x176a
36 #define mmPIPE3_PG_CONFIG 0x176c
[all …]
H A Ddce_11_0_d.h27 #define mmPIPE0_PG_CONFIG 0x2c0
28 #define mmPIPE0_PG_ENABLE 0x2c1
29 #define mmPIPE0_PG_STATUS 0x2c2
30 #define mmPIPE1_PG_CONFIG 0x2c3
31 #define mmPIPE1_PG_ENABLE 0x2c4
32 #define mmPIPE1_PG_STATUS 0x2c5
33 #define mmPIPE2_PG_CONFIG 0x2c6
34 #define mmPIPE2_PG_ENABLE 0x2c7
35 #define mmPIPE2_PG_STATUS 0x2c8
36 #define mmDCFEV0_PG_CONFIG 0x2db
[all …]
H A Ddce_10_0_d.h27 #define mmPIPE0_PG_CONFIG 0x2c0
28 #define mmPIPE0_PG_ENABLE 0x2c1
29 #define mmPIPE0_PG_STATUS 0x2c2
30 #define mmPIPE1_PG_CONFIG 0x2c3
31 #define mmPIPE1_PG_ENABLE 0x2c4
32 #define mmPIPE1_PG_STATUS 0x2c5
33 #define mmPIPE2_PG_CONFIG 0x2c6
34 #define mmPIPE2_PG_ENABLE 0x2c7
35 #define mmPIPE2_PG_STATUS 0x2c8
36 #define mmPIPE3_PG_CONFIG 0x2c9
[all …]
H A Ddce_11_2_d.h27 #define mmPIPE0_PG_CONFIG 0x2c0
28 #define mmPIPE0_PG_ENABLE 0x2c1
29 #define mmPIPE0_PG_STATUS 0x2c2
30 #define mmPIPE1_PG_CONFIG 0x2c3
31 #define mmPIPE1_PG_ENABLE 0x2c4
32 #define mmPIPE1_PG_STATUS 0x2c5
33 #define mmPIPE2_PG_CONFIG 0x2c6
34 #define mmPIPE2_PG_ENABLE 0x2c7
35 #define mmPIPE2_PG_STATUS 0x2c8
36 #define mmPIPE3_PG_CONFIG 0x2c9
[all …]
/linux/tools/perf/pmu-events/arch/powerpc/power8/
H A Dother.json3 "EventCode": "0x1f05e",
9 "EventCode": "0x2006e",
11 …"BriefDescription": "Cycles in 2-lpar mode. Threads 0-3 belong to Lpar0 and threads 4-7 belong to …
15 "EventCode": "0x4e05e",
17 …"BriefDescription": "Number of cycles in 4 LPAR mode. Threads 0-1 belong to lpar0, threads 2-3 bel…
21 "EventCode": "0x610050",
27 "EventCode": "0x520050",
33 "EventCode": "0x620052",
39 "EventCode": "0x610052",
45 "EventCode": "0x610054",
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_11_0_0_offset.h29 // base address: 0x4980
30 …SDMA0_DEC_START 0x0000
31 …e regSDMA0_DEC_START_BASE_IDX 0
32 …SDMA0_F32_MISC_CNTL 0x000b
33 …e regSDMA0_F32_MISC_CNTL_BASE_IDX 0
34 …SDMA0_GLOBAL_TIMESTAMP_LO 0x000f
35 …e regSDMA0_GLOBAL_TIMESTAMP_LO_BASE_IDX 0
36 …SDMA0_GLOBAL_TIMESTAMP_HI 0x0010
37 …e regSDMA0_GLOBAL_TIMESTAMP_HI_BASE_IDX 0
38 …SDMA0_POWER_CNTL 0x001a
[all …]
H A Dgc_11_0_3_offset.h29 // base address: 0x4980
30 …SDMA0_DEC_START 0x0000
31 …e regSDMA0_DEC_START_BASE_IDX 0
32 …SDMA0_F32_MISC_CNTL 0x000b
33 …e regSDMA0_F32_MISC_CNTL_BASE_IDX 0
34 …SDMA0_GLOBAL_TIMESTAMP_LO 0x000f
35 …e regSDMA0_GLOBAL_TIMESTAMP_LO_BASE_IDX 0
36 …SDMA0_GLOBAL_TIMESTAMP_HI 0x0010
37 …e regSDMA0_GLOBAL_TIMESTAMP_HI_BASE_IDX 0
38 …SDMA0_POWER_CNTL 0x001a
[all …]

12