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/freebsd/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dwasp_reg_map.h20 volatile char pad__0[0x4000]; /* 0x0 - 0x4000 */
21 volatile u_int32_t HOST_INTF_RESET_CONTROL; /* 0x4000 - 0x4004 */
22 volatile u_int32_t HOST_INTF_PM_CTRL; /* 0x4004 - 0x4008 */
23 volatile u_int32_t HOST_INTF_TIMEOUT; /* 0x4008 - 0x400c */
24 volatile u_int32_t HOST_INTF_SREV; /* 0x400c - 0x4010 */
25 volatile u_int32_t HOST_INTF_INTR_SYNC_CAUSE; /* 0x4010 - 0x4014 */
26 volatile u_int32_t HOST_INTF_INTR_SYNC_ENABLE; /* 0x4014 - 0x4018 */
27 volatile u_int32_t HOST_INTF_INTR_ASYNC_MASK; /* 0x4018 - 0x401c */
28 volatile u_int32_t HOST_INTF_INTR_SYNC_MASK; /* 0x401c - 0x4020 */
29 volatile u_int32_t HOST_INTF_INTR_ASYNC_CAUSE; /* 0x4020 - 0x4024 */
[all …]
/freebsd/sys/contrib/dev/athk/ath11k/
H A Dpci.h13 #define PCIE_SOC_GLOBAL_RESET 0x3008
16 #define WLAON_WARM_SW_ENTRY 0x1f80504
17 #define WLAON_SOC_RESET_CAUSE_REG 0x01f8060c
19 #define PCIE_Q6_COOKIE_ADDR 0x01f80500
20 #define PCIE_Q6_COOKIE_DATA 0xc0000000
23 #define PCIE_SCRATCH_0_SOC_PCIE_REG 0x4040
26 #define PCIE_SOC_WAKE_PCIE_LOCAL_REG 0x3004
28 #define PCIE_PCIE_PARF_LTSSM 0x1e081b0
29 #define PARM_LTSSM_VALUE 0x111
31 #define GCC_GCC_PCIE_HOT_RST 0x1e402bc
[all …]
/freebsd/sys/contrib/device-tree/Bindings/remoteproc/
H A Dqcom,qcs404-pas.yaml69 reg = <0x0c700000 0x4040>;
75 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
84 qcom,smem-states = <&adsp_smp2p_out 0>;
H A Dqcom,sdx55-pas.yaml80 reg = <0x04080000 0x4040>;
86 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
99 qcom,smem-states = <&modem_smp2p_out 0>;
H A Dqcom,sc7180-pas.yaml155 reg = <0x04080000 0x4040>;
161 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
177 qcom,smem-states = <&modem_smp2p_out 0>;
H A Dqcom,qcs404-cdsp-pil.yaml122 reg = <0x00b00000 0x4040>;
125 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
154 qcom,halt-regs = <&tcsr 0x19004>;
158 qcom,smem-states = <&cdsp_smp2p_out 0>;
H A Dqcom,sm8150-pas.yaml143 reg = <0x17300000 0x4040>;
151 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
163 qcom,smem-states = <&adsp_smp2p_out 0>;
/freebsd/sys/contrib/dev/athk/ath12k/
H A Dpci.h13 #define PCIE_SOC_GLOBAL_RESET 0x3008
16 #define WLAON_WARM_SW_ENTRY 0x1f80504
17 #define WLAON_SOC_RESET_CAUSE_REG 0x01f8060c
19 #define PCIE_Q6_COOKIE_ADDR 0x01f80500
20 #define PCIE_Q6_COOKIE_DATA 0xc0000000
23 #define PCIE_SCRATCH_0_SOC_PCIE_REG 0x4040
26 #define PCIE_SOC_WAKE_PCIE_LOCAL_REG 0x3004
28 #define PCIE_PCIE_PARF_LTSSM 0x1e081b0
29 #define PARM_LTSSM_VALUE 0x111
31 #define GCC_GCC_PCIE_HOT_RST 0x1e38338
[all …]
/freebsd/sys/libkern/
H A Dcrc16.c32 /* CRC table for the CRC-16. The poly is 0x8005 (x16 + x15 + x2 + 1). */
34 0x0000, 0xC0C1, 0xC181, 0x0140, 0xC301, 0x03C0, 0x0280, 0xC241,
35 0xC601, 0x06C0, 0x0780, 0xC741, 0x0500, 0xC5C1, 0xC481, 0x0440,
36 0xCC01, 0x0CC0, 0x0D80, 0xCD41, 0x0F00, 0xCFC1, 0xCE81, 0x0E40,
37 0x0A00, 0xCAC1, 0xCB81, 0x0B40, 0xC901, 0x09C0, 0x0880, 0xC841,
38 0xD801, 0x18C0, 0x1980, 0xD941, 0x1B00, 0xDBC1, 0xDA81, 0x1A40,
39 0x1E00, 0xDEC1, 0xDF81, 0x1F40, 0xDD01, 0x1DC0, 0x1C80, 0xDC41,
40 0x1400, 0xD4C1, 0xD581, 0x1540, 0xD701, 0x17C0, 0x1680, 0xD641,
41 0xD201, 0x12C0, 0x1380, 0xD341, 0x1100, 0xD1C1, 0xD081, 0x1040,
42 0xF001, 0x30C0, 0x3180, 0xF141, 0x3300, 0xF3C1, 0xF281, 0x3240,
[all …]
/freebsd/sys/dev/ntb/ntb_hw/
H A Dntb_hw_intel.h42 * Params: [in] P = Bit position of start of the bit field (lsb is 0).
51 #define NTB_LINK_STATUS_ACTIVE 0x2000
52 #define NTB_LINK_SPEED_MASK 0x000f
53 #define NTB_LINK_WIDTH_MASK 0x03f0
67 #define XEON_SPCICMD_OFFSET 0x0504
68 #define XEON_DEVCTRL_OFFSET 0x0598
69 #define XEON_DEVSTS_OFFSET 0x059a
70 #define XEON_LINK_STATUS_OFFSET 0x01a2
71 #define XEON_SLINK_STATUS_OFFSET 0x05a2
73 #define XEON_PBAR2LMT_OFFSET 0x0000
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nxp/mxs/
H A Dimx28-pinfunc.h13 #define MX28_PAD_GPMI_D00__GPMI_D0 0x0000
14 #define MX28_PAD_GPMI_D01__GPMI_D1 0x0010
15 #define MX28_PAD_GPMI_D02__GPMI_D2 0x0020
16 #define MX28_PAD_GPMI_D03__GPMI_D3 0x0030
17 #define MX28_PAD_GPMI_D04__GPMI_D4 0x0040
18 #define MX28_PAD_GPMI_D05__GPMI_D5 0x0050
19 #define MX28_PAD_GPMI_D06__GPMI_D6 0x0060
20 #define MX28_PAD_GPMI_D07__GPMI_D7 0x0070
21 #define MX28_PAD_GPMI_CE0N__GPMI_CE0N 0x0100
22 #define MX28_PAD_GPMI_CE1N__GPMI_CE1N 0x0110
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dqcs404.dtsi24 #clock-cells = <0>;
30 #clock-cells = <0>;
37 #size-cells = <0>;
42 reg = <0x100>;
56 reg = <0x101>;
70 reg = <0x102>;
84 reg = <0x103>;
104 CPU_SLEEP_0: cpu-sleep-0 {
107 arm,psci-suspend-param = <0x40000003>;
161 reg = <0
[all...]
H A Dsc7180-idp.dts50 reg = <0x0 0x94600000 0x0 0x800000>;
56 reg = <0x0 0x80b00000 0x0 0x100000>;
61 reg = <0x0 0x8600000
[all...]
/freebsd/sys/contrib/device-tree/Bindings/net/wireless/
H A Dqcom,ath11k.yaml267 reg = <0xcd00000 0x4040>,
268 <0x4ab000 0x20>;
275 reg = <0xc000000 0x2000000>;
276 interrupts = <0 320 1>,
277 <0 319 1>,
278 <0 318 1>,
279 <0 317 1>,
280 <0 316 1>,
281 <0 315 1>,
282 <0 314 1>,
[all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/westmereex/
H A Dmemory.json4 "Counter": "0,1,2,3",
5 "EventCode": "0x5",
8 "UMask": "0x2"
13 "EventCode": "0xB7",
15 "MSRIndex": "0x1A6",
16 "MSRValue": "0x6011",
19 "UMask": "0x1"
24 "EventCode": "0xB7",
26 "MSRIndex": "0x1A6",
27 "MSRValue": "0xF811",
[all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/nehalemep/
H A Dmemory.json5 "EventCode": "0xB7",
7 "MSRIndex": "0x1A6",
8 "MSRValue": "0x6011",
11 "UMask": "0x1"
16 "EventCode": "0xB7",
18 "MSRIndex": "0x1A6",
19 "MSRValue": "0xF811",
22 "UMask": "0x1"
27 "EventCode": "0xB7",
29 "MSRIndex": "0x1A6",
[all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/nehalemex/
H A Dmemory.json3 "EventCode": "0xB7",
4 "MSRValue": "0x6011",
6 "UMask": "0x1",
8 "MSRIndex": "0x1A6",
14 "EventCode": "0xB7",
15 "MSRValue": "0xF811",
17 "UMask": "0x1",
19 "MSRIndex": "0x1A6",
25 "EventCode": "0xB7",
26 "MSRValue": "0x4011",
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/ti/
H A Dk3-am65-mcu.dtsi11 reg = <0x0 0x40f00000 0x0 0x20000>;
14 ranges = <0x0 0x0 0x40f00000 0x20000>;
18 reg = <0x4040
[all...]
H A Dk3-j721s2-mcu-wakeup.dtsi19 reg = <0x00 0x44083000 0x00 0x1000>;
41 ranges = <0x0 0x00 0x43000000 0x20000>;
45 reg = <0x14 0x
[all...]
H A Dk3-j7200-mcu-wakeup.dtsi19 reg = <0x00 0x44083000 0x00 0x1000>;
40 reg = <0x00 0x40400000 0x00 0x400>;
53 reg = <0x00 0x4041000
[all...]
/freebsd/sys/dev/bxe/
H A D57712_int_offsets.h31 { 0x40, 0x0, 0x0, 0x0, 0x0}, // COMMON_SB_SIZE
32 { 0x40, 0x0, 0x0, 0x0, 0x0}, // COMMON_SB_DATA_SIZE
33 { 0x28, 0x0, 0x0, 0x0, 0x0}, // COMMON_SP_SB_SIZE
34 { 0x10, 0x0, 0x0, 0x0, 0x0}, // COMMON_SP_SB_DATA_SIZE
35 { 0x40, 0x0, 0x0, 0x0, 0x0}, // COMMON_DYNAMIC_HC_CONFIG_SIZE
36 { 0x10, 0x0, 0x0, 0x0, 0x0}, // COMMON_ASM_ASSERT_MSG_SIZE
37 { 0x8, 0x0, 0x0, 0x0, 0x0}, // COMMON_ASM_ASSERT_INDEX_SIZE
38 { 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_ASM_INVALID_ASSERT_OPCODE
39 { 0x3d, 0x0, 0x0, 0x0, 0x0}, // COMMON_RAM1_TEST_EVENT_ID
40 …{ 0x3c, 0x0, 0x0, 0x0, 0x0}, // COMMON_INBOUND_INTERRUPT_TEST_AGG_INT_EVEN…
[all …]
H A D57711_int_offsets.h31 { 0x40, 0x0, 0x0, 0x0, 0x0}, // COMMON_SB_SIZE
32 { 0x40, 0x0, 0x0, 0x0, 0x0}, // COMMON_SB_DATA_SIZE
33 { 0x28, 0x0, 0x0, 0x0, 0x0}, // COMMON_SP_SB_SIZE
34 { 0x10, 0x0, 0x0, 0x0, 0x0}, // COMMON_SP_SB_DATA_SIZE
35 { 0x40, 0x0, 0x0, 0x0, 0x0}, // COMMON_DYNAMIC_HC_CONFIG_SIZE
36 { 0x10, 0x0, 0x0, 0x0, 0x0}, // COMMON_ASM_ASSERT_MSG_SIZE
37 { 0x8, 0x0, 0x0, 0x0, 0x0}, // COMMON_ASM_ASSERT_INDEX_SIZE
38 { 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_ASM_INVALID_ASSERT_OPCODE
39 { 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_RAM1_TEST_EVENT_ID
40 …{ 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_INBOUND_INTERRUPT_TEST_AGG_INT_EVEN…
[all …]
/freebsd/sys/dev/bnxt/bnxt_re/
H A Dib_verbs.h41 #define BNXT_RE_ROCE_V2_UDP_SPORT 0x8CD1
42 #define BNXT_RE_QP_RANDOM_QKEY 0x81818181
97 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_256MB 0x1cUL
488 return 0; in bnxt_re_init_pow2_flag()
508 return 0; in bnxt_re_init_rsvd_wqe_flag()
516 return _is_chip_gen_p5_p7(cctx) ? 0 : BNXT_QPLIB_RESERVED_QP_WRS; in bnxt_re_get_diff()
518 return 0; in bnxt_re_get_diff()
559 return (*(u16 *)a ^ *(u16 *)b) | (a32[0] ^ b32[0]) | in compare_ether_header()
572 /* CRC table for the CRC-16. The poly is 0x8005 (x16 + x15 + x2 + 1). */ in crc16()
574 0x0000, 0xC0C1, 0xC181, 0x0140, 0xC301, 0x03C0, 0x0280, 0xC241, in crc16()
[all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/westmereep-dp/
H A Dmemory.json4 "Counter": "0,1,2,3",
5 "EventCode": "0x5",
8 "UMask": "0x2"
12 "Counter": "0,1,2,3",
13 "EventCode": "0xB7, 0xBB",
15 "MSRIndex": "0x1a6,0x1a7",
16 "MSRValue": "0x3011",
19 "UMask": "0x1"
23 "Counter": "0,1,2,3",
24 "EventCode": "0xB7, 0xBB",
[all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/westmereep-sp/
H A Dmemory.json4 "Counter": "0,1,2,3",
5 "EventCode": "0xB7, 0xBB",
7 "MSRIndex": "0x1a6,0x1a7",
8 "MSRValue": "0x6011",
11 "UMask": "0x1"
15 "Counter": "0,1,2,3",
16 "EventCode": "0xB7, 0xBB",
18 "MSRIndex": "0x1a6,0x1a7",
19 "MSRValue": "0xF811",
22 "UMask": "0x1"
[all …]

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