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12

/linux/arch/arm64/boot/dts/ti/
H A Dk3-am65.dtsi54 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
55 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
56 <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */
57 <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */
58 <0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */
59 <0x00 0x70000000 0x00 0x70000000 0x00 0x00200000>, /* MSMC SRAM */
60 <0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */
62 <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
63 <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>,
64 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
[all …]
H A Dk3-j721s2.dtsi29 #size-cells = <0>;
42 cpu0: cpu@0 {
44 reg = <0x000>;
47 i-cache-size = <0xc000>;
50 d-cache-size = <0x8000>;
58 reg = <0x001>;
61 i-cache-size = <0xc000>;
64 d-cache-size = <0x8000>;
75 cache-size = <0x100000>;
118 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
[all …]
H A Dk3-j7200.dtsi25 #size-cells = <0>;
39 cpu0: cpu@0 {
41 reg = <0x000>;
44 i-cache-size = <0xc000>;
47 d-cache-size = <0x8000>;
55 reg = <0x001>;
58 i-cache-size = <0xc000>;
61 d-cache-size = <0x8000>;
72 cache-size = <0x100000>;
113 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
[all …]
H A Dk3-j721e.dtsi25 #size-cells = <0>;
39 cpu0: cpu@0 {
41 reg = <0x000>;
44 i-cache-size = <0xC000>;
47 d-cache-size = <0x8000>;
55 reg = <0x001>;
58 i-cache-size = <0xC000>;
61 d-cache-size = <0x8000>;
72 cache-size = <0x100000>;
114 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
[all …]
H A Dk3-am65-mcu.dtsi13 ranges = <0x0 0x0 0x40f00000 0x20000>;
17 reg = <0x200 0x8>;
22 reg = <0x4040 0x4>;
30 reg = <0x0 0x40f04200 0x0 0x10>;
33 pinctrl-single,function-mask = <0x00000101>;
39 reg = <0x0 0x40f04280 0x0 0x8>;
42 pinctrl-single,function-mask = <0x00000003>;
47 reg = <0x00 0x40a00000 0x00 0x100>;
56 reg = <0x00 0x41c00000 0x00 0x80000>;
57 ranges = <0x0 0x00 0x41c00000 0x80000>;
[all …]
H A Dk3-j721e-mcu-wakeup.dtsi19 reg = <0x00 0x44083000 0x0 0x1000>;
44 ranges = <0x0 0x0 0x40f00000 0x20000>;
48 reg = <0x200 0x8>;
53 reg = <0x4040 0x4>;
62 ranges = <0x0 0x00 0x43000000 0x20000>;
66 reg = <0x14 0x4>;
73 /* Proxy 0 addressing */
74 reg = <0x00 0x4301c000 0x00 0x178>;
77 pinctrl-single,function-mask = <0xffffffff>;
83 reg = <0x00 0x40f04200 0x00 0x28>;
[all …]
H A Dk3-j721s2-mcu-wakeup.dtsi19 reg = <0x00 0x44083000 0x00 0x1000>;
44 ranges = <0x0 0x00 0x43000000 0x20000>;
48 reg = <0x14 0x4>;
57 reg = <0x00 0x43600000 0x00 0x10000>,
58 <0x00 0x44880000 0x00 0x20000>,
59 <0x00 0x44860000 0x00 0x20000>;
72 reg = <0x00 0x41c00000 0x00 0x100000>;
73 ranges = <0x00 0x00 0x41c00000 0x100000>;
80 /* Proxy 0 addressing */
81 reg = <0x00 0x4301c000 0x00 0x034>;
[all …]
/linux/arch/arm/mach-omap2/
H A Dsram.h57 #define OMAP2_SRAM_PA 0x40200000
58 #define OMAP3_SRAM_PA 0x40200000
/linux/arch/powerpc/platforms/cell/spufs/
H A Dspu_restore_dump.h_shipped7 0x40800000,
8 0x409ff801,
9 0x24000080,
10 0x24fd8081,
11 0x1cd80081,
12 0x33001180,
13 0x42034003,
14 0x33800284,
15 0x1c010204,
16 0x40200000,
[all …]
H A Dspu_save_crt0.S18 .space SIZEOF_SPU_SPILL_REGS, 0x0
24 stqa $0, regs_spill + 0
47 .balignl 16, 0x40200000
49 stqd $16, 0($3)
53 andi $5, $4, 0x7F
62 il $0, 0
64 stqd $0, 0($SP)
74 brsl $0, main
78 * stop-and-signal with code=0.
84 stop 0x0
[all …]
H A Dspu_restore_crt0.S19 .space SIZEOF_SPU_SPILL_REGS, 0x0
28 il $0, 0
30 stqd $0, 0($SP)
40 brsl $0, main
52 .balignl 16, 0x40200000
54 lqd $16, 0($3)
58 andi $5, $4, 0x7F
64 lqa $0, regs_spill + 0
87 * following the 'stop 0x3ffc' have been modified at run
97 stop 0
[all …]
H A Dspu_restore.c15 #define LS_SIZE 0x40000 /* 256K (in bytes) */
25 #define BR_INSTR 0x327fff80 /* br -4 */
26 #define NOP_INSTR 0x40200000 /* nop */
27 #define HEQ_INSTR 0x7b000000 /* heq $0, $0 */
28 #define STOP_INSTR 0x00000000 /* stop 0x0 */
29 #define ILLEGAL_INSTR 0x00800000 /* illegal instr */
30 #define RESTORE_COMPLETE 0x00003ffc /* stop 0x3ffc */
34 unsigned int ls = (unsigned int)&regs_spill[0]; in fetch_regs_from_mem()
36 unsigned int tag_id = 0; in fetch_regs_from_mem()
37 unsigned int cmd = 0x40; /* GET */ in fetch_regs_from_mem()
[all …]
H A Dspu_save_dump.h_shipped7 0x20805000,
8 0x20805201,
9 0x20805402,
10 0x20805603,
11 0x20805804,
12 0x20805a05,
13 0x20805c06,
14 0x20805e07,
15 0x20806008,
16 0x20806209,
[all …]
/linux/arch/arm64/boot/dts/arm/
H A Dcorstone1000-mps3.dts18 reg = <0x40100000 0x10000>;
27 reg = <0x40200000 0x100000>;
/linux/arch/arm64/boot/dts/qcom/
H A Dsa8540p.dtsi184 linux,pci-domain = <0>;
201 reg = <0x0 0x01c10000 0x0 0x3000>,
202 <0x0 0x40000000 0x0 0xf1d>,
203 <0x0 0x40000f20 0x0 0xa8>,
204 <0x0 0x40001000 0x0 0x1000>,
205 <0x0 0x40100000 0x0 0x100000>;
208 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
209 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1d00000>;
216 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 541 IRQ_TYPE_LEVEL_HIGH>,
217 <0 0 0 2 &intc 0 0 GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH>,
[all …]
H A Dsa8540p-ride.dts34 regulators-0 {
163 pinctrl-0 = <&ethernet0_default>;
170 #size-cells = <0>;
174 compatible = "ethernet-phy-id0141.0dd4";
175 reg = <0x8>;
189 /* Set MODE[2:0] to RGMII_SGMII */
190 <0x12 0x14 0xfff8 0x4>,
191 /* Soft reset required after changing MODE[2:0] */
192 <0x12 0x14 0x7fff 0x8000>;
202 snps,map-to-dma-channel = <0x0>;
[all …]
H A Dsa8775p.dtsi30 #clock-cells = <0>;
35 #clock-cells = <0>;
41 #size-cells = <0>;
43 cpu0: cpu@0 {
46 reg = <0x0 0x0>;
50 qcom,freq-domain = <&cpufreq_hw 0>;
70 reg = <0x0 0x100>;
74 qcom,freq-domain = <&cpufreq_hw 0>;
89 reg = <0x0 0x200>;
93 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
/linux/Documentation/devicetree/bindings/usb/
H A Dnxp,isp1760.yaml61 reg = <0x40200000 0x100000>;
/linux/arch/arm/boot/dts/intel/pxa/
H A Dpxa2xx.dtsi64 reg = <0x40d00000 0xd0>;
69 #address-cells = <0x1>;
70 #size-cells = <0x1>;
71 reg = <0x40e00000 0x10000>;
73 #gpio-cells = <0x2>;
77 #interrupt-cells = <0x2>;
81 reg = <0x40e00000 0x4>;
85 reg = <0x40e00004 0x4>;
89 reg = <0x40e00008 0x4>;
92 reg = <0x40e0000c 0x4>;
[all …]
/linux/Documentation/devicetree/bindings/pci/
H A Dqcom,pcie-sa8775p.yaml91 reg = <0x0 0x01c00000 0x0 0x3000>,
92 <0x0 0x40000000 0x0 0xf20>,
93 <0x0 0x40000f20 0x0 0xa8>,
94 <0x0 0x40001000 0x0 0x4000>,
95 <0x0 0x40100000 0x0 0x100000>,
96 <0x0 0x01c03000 0x0 0x1000>;
98 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
99 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
101 bus-range = <0x00 0xff>;
103 linux,pci-domain = <0>;
[all …]
H A Dqcom,pcie-sc7280.yaml95 reg = <0 0x01c08000 0 0x3000>,
96 <0 0x40000000 0 0xf1d>,
97 <0 0x40000f20 0 0xa8>,
98 <0 0x40001000 0 0x1000>,
99 <0 0x40100000 0 0x100000>;
101 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
102 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
104 bus-range = <0x00 0xff>;
156 interrupt-map-mask = <0 0 0 0x7>;
157 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>,
[all …]
/linux/arch/arm/boot/dts/arm/
H A Dmps2.dtsi53 #clock-cells = <0>;
59 #clock-cells = <0>;
65 #clock-cells = <0>;
71 #clock-cells = <0>;
77 #clock-cells = <0>;
84 #clock-cells = <0>;
92 #clock-cells = <0>;
100 #clock-cells = <0>;
113 ranges = <0 0x40000000 0x10000>;
115 timer0: mps2-timer0@0 {
[all …]
/linux/arch/arm/mach-pxa/
H A Ddevices.c52 [0] = {
53 .start = 0x41100000,
54 .end = 0x41100fff,
69 .id = 0, in pxa_set_mci_info()
74 .dma_mask = 0xffffffffUL, in pxa_set_mci_info()
91 [0] = {
92 .start = 0x40600000,
93 .end = 0x4060ffff,
103 static u64 udc_dma_mask = ~(u32)0;
128 [0] = {
[all …]
/linux/sound/pci/mixart/
H A Dmixart_mixer.c24 0xc2c00000, /* [000] -96.0 dB */
25 0xc2bf0000, /* [001] -95.5 dB */
26 0xc2be0000, /* [002] -95.0 dB */
27 0xc2bd0000, /* [003] -94.5 dB */
28 0xc2bc0000, /* [004] -94.0 dB */
29 0xc2bb0000, /* [005] -93.5 dB */
30 0xc2ba0000, /* [006] -93.0 dB */
31 0xc2b90000, /* [007] -92.5 dB */
32 0xc2b80000, /* [008] -92.0 dB */
33 0xc2b70000, /* [009] -91.5 dB */
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/nbio/
H A Dnbio_2_3_default.h26 #define mmBIF_BX_PF_MM_INDEX_DEFAULT 0x00000000
27 #define mmBIF_BX_PF_MM_DATA_DEFAULT 0x00000000
28 #define mmBIF_BX_PF_MM_INDEX_HI_DEFAULT 0x00000000
32 #define mmSYSHUB_INDEX_OVLP_DEFAULT 0x00000000
33 #define mmSYSHUB_DATA_OVLP_DEFAULT 0x00000000
34 #define mmPCIE_INDEX_DEFAULT 0x00000000
35 #define mmPCIE_DATA_DEFAULT 0x00000000
36 #define mmPCIE_INDEX2_DEFAULT 0x00000000
37 #define mmPCIE_DATA2_DEFAULT 0x00000000
38 #define mmSBIOS_SCRATCH_0_DEFAULT 0x00000000
[all …]

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