Lines Matching +full:0 +full:x40200000
34 regulators-0 {
162 pinctrl-0 = <ðernet0_default>;
169 #size-cells = <0>;
173 compatible = "ethernet-phy-id0141.0dd4";
174 reg = <0x8>;
188 /* Set MODE[2:0] to RGMII_SGMII */
189 <0x12 0x14 0xfff8 0x4>,
190 /* Soft reset required after changing MODE[2:0] */
191 <0x12 0x14 0x7fff 0x8000>;
201 snps,map-to-dma-channel = <0x0>;
203 snps,priority = <0x1>;
208 snps,map-to-dma-channel = <0x1>;
214 snps,map-to-dma-channel = <0x2>;
220 snps,map-to-dma-channel = <0x3>;
221 snps,priority = <0xc>;
238 snps,send_slope = <0x1000>;
239 snps,idle_slope = <0x1000>;
240 snps,high_credit = <0x3e800>;
241 snps,low_credit = <0xffc18000>;
246 snps,send_slope = <0x1000>;
247 snps,idle_slope = <0x1000>;
248 snps,high_credit = <0x3e800>;
249 snps,low_credit = <0xffc18000>;
261 pinctrl-0 = <ðernet1_default>;
276 snps,map-to-dma-channel = <0x0>;
278 snps,priority = <0x1>;
283 snps,map-to-dma-channel = <0x1>;
289 snps,map-to-dma-channel = <0x2>;
295 snps,map-to-dma-channel = <0x3>;
296 snps,priority = <0xc>;
313 snps,send_slope = <0x1000>;
314 snps,idle_slope = <0x1000>;
315 snps,high_credit = <0x3e800>;
316 snps,low_credit = <0xffc18000>;
321 snps,send_slope = <0x1000>;
322 snps,idle_slope = <0x1000>;
323 snps,high_credit = <0x3e800>;
324 snps,low_credit = <0xffc18000>;
331 pinctrl-0 = <&i2c0_default>;
338 pinctrl-0 = <&i2c1_default>;
345 pinctrl-0 = <&i2c12_default>;
352 pinctrl-0 = <&i2c15_default>;
359 pinctrl-0 = <&i2c18_default>;
365 ranges = <0x01000000 0x0 0x3c200000 0x0 0x3c200000 0x0 0x100000>,
366 <0x02000000 0x0 0x3c300000 0x0 0x3c300000 0x0 0x1d00000>,
367 <0x03000000 0x5 0x00000000 0x5 0x00000000 0x1 0x00000000>;
373 pinctrl-0 = <&pcie2a_default>;
386 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
387 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x20000000>,
388 <0x03000000 0x6 0x00000000 0x6 0x00000000 0x2 0x00000000>;
394 pinctrl-0 = <&pcie3a_default>;
417 reg = <0xa0 0x4>;