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/freebsd/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dwasp_reg_map.h20 volatile char pad__0[0x4000]; /* 0x0 - 0x4000 */
21 volatile u_int32_t HOST_INTF_RESET_CONTROL; /* 0x4000 - 0x4004 */
22 volatile u_int32_t HOST_INTF_PM_CTRL; /* 0x4004 - 0x4008 */
23 volatile u_int32_t HOST_INTF_TIMEOUT; /* 0x4008 - 0x400c */
24 volatile u_int32_t HOST_INTF_SREV; /* 0x400c - 0x4010 */
25 volatile u_int32_t HOST_INTF_INTR_SYNC_CAUSE; /* 0x4010 - 0x4014 */
26 volatile u_int32_t HOST_INTF_INTR_SYNC_ENABLE; /* 0x4014 - 0x4018 */
27 volatile u_int32_t HOST_INTF_INTR_ASYNC_MASK; /* 0x4018 - 0x401c */
28 volatile u_int32_t HOST_INTF_INTR_SYNC_MASK; /* 0x401c - 0x4020 */
29 volatile u_int32_t HOST_INTF_INTR_ASYNC_CAUSE; /* 0x4020 - 0x4024 */
[all …]
H A Dosprey_reg_map.h86 volatile char pad__0[0x8]; /* 0x0 - 0x8 */
87 volatile u_int32_t MAC_DMA_CR; /* 0x8 - 0xc */
88 volatile char pad__1[0x8]; /* 0xc - 0x14 */
89 volatile u_int32_t MAC_DMA_CFG; /* 0x14 - 0x18 */
90 volatile u_int32_t MAC_DMA_RXBUFPTR_THRESH; /* 0x18 - 0x1c */
91 volatile u_int32_t MAC_DMA_TXDPPTR_THRESH; /* 0x1c - 0x20 */
92 volatile u_int32_t MAC_DMA_MIRT; /* 0x20 - 0x24 */
93 volatile u_int32_t MAC_DMA_GLOBAL_IER; /* 0x24 - 0x28 */
94 volatile u_int32_t MAC_DMA_TIMT; /* 0x28 - 0x2c */
95 volatile u_int32_t MAC_DMA_RIMT; /* 0x2c - 0x30 */
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/ti/
H A Dk3-am62a-wakeup.dtsi13 ranges = <0x00 0x00 0x43000000 0x20000>;
17 reg = <0x14 0x4>;
22 reg = <0x200 0x8>;
27 reg = <0x4008 0x4>;
32 reg = <0x4018 0x4>;
38 reg = <0x00 0x2b300000 0x00 0x100>;
41 clocks = <&k3_clks 114 0>;
48 reg = <0x00 0x2b200000 0x00 0x100>;
51 #size-cells = <0>;
60 reg = <0x00 0x2b1f0000 0x00 0x100>;
[all …]
H A Dk3-am62-wakeup.dtsi14 reg = <0x00 0x43000000 0x00 0x20000>;
17 ranges = <0x0 0x00 0x43000000 0x20000>;
22 reg = <0x14 0x4>;
27 reg = <0x200 0x8>;
32 reg = <0x4008 0x4>;
37 reg = <0x4018 0x4>;
43 reg = <0x00 0x2b300050 0x00 0x4>,
44 <0x00 0x2b300054 0x00 0x4>,
45 <0x00 0x2b300058 0x00 0x4>;
57 clocks = <&k3_clks 114 0>;
[all …]
H A Dk3-am62p-j722s-common-wakeup.dtsi11 reg = <0x00 0x43000000 0x00 0x20000>;
14 ranges = <0x00 0x00 0x43000000 0x20000>;
19 reg = <0x14 0x4>;
25 reg = <0x200 0x8>;
30 reg = <0x4008 0x4>;
35 reg = <0x4018 0x4>;
41 reg = <0x00 0x2b300000 0x00 0x100>;
44 clocks = <&k3_clks 114 0>;
51 reg = <0x00 0x2b200000 0x00 0x100>;
54 #size-cells = <0>;
[all …]
H A Dk3-am62p-wakeup.dtsi10 reg = <0x00 0x43000000 0x00 0x20000>;
13 ranges = <0x00 0x00 0x43000000 0x20000>;
18 reg = <0x14 0x4>;
24 reg = <0x4008 0x4>;
29 reg = <0x4018 0x4>;
35 reg = <0x00 0x2b300000 0x00 0x100>;
38 clocks = <&k3_clks 114 0>;
45 reg = <0x00 0x2b200000 0x00 0x100>;
48 #size-cells = <0>;
57 reg = <0x00 0x2b1f0000 0x00 0x100>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/usb/
H A Dti,am62-usb.yaml62 "^usb@[0-9a-f]+$":
88 reg = <0x00 0x0f910000 0x00 0x800>,
89 <0x00 0x0f918000 0x00 0x400>;
92 ti,syscon-phy-pll-refclk = <&wkup_conf 0x4018>;
99 reg = <0x00 0x31100000 0x00 0x50000>;
100 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
101 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */
/freebsd/sys/dev/vmware/pvscsi/
H A Dpvscsi.h12 #define PCI_VENDOR_ID_VMWARE 0x15ad
13 #define PCI_DEVICE_ID_VMWARE_PVSCSI 0x07c0
16 PVSCSI_REG_OFFSET_COMMAND = 0x0000,
17 PVSCSI_REG_OFFSET_COMMAND_DATA = 0x0004,
18 PVSCSI_REG_OFFSET_COMMAND_STATUS = 0x0008,
19 PVSCSI_REG_OFFSET_LAST_STS_0 = 0x0100,
20 PVSCSI_REG_OFFSET_LAST_STS_1 = 0x0104,
21 PVSCSI_REG_OFFSET_LAST_STS_2 = 0x0108,
22 PVSCSI_REG_OFFSET_LAST_STS_3 = 0x010c,
23 PVSCSI_REG_OFFSET_INTR_STATUS = 0x100c,
[all …]
/freebsd/sys/dev/flash/
H A Dmx25l.c57 #define FL_NONE 0x00
58 #define FL_ERASE_4K 0x01
59 #define FL_ERASE_32K 0x02
60 #define FL_ENABLE_4B_ADDR 0x04
61 #define FL_DISABLE_4B_ADDR 0x08
96 #define TSTATE_STOPPED 0
118 { "en25f32", 0x1c, 0x3116, 64 * 1024, 64, FL_NONE },
119 { "en25p32", 0x1c, 0x2016, 64 * 1024, 64, FL_NONE },
120 { "en25p64", 0x1c, 0x2017, 64 * 1024, 128, FL_NONE },
121 { "en25q32", 0x1c, 0x3016, 64 * 1024, 64, FL_NONE },
[all …]
/freebsd/sys/dev/et/
H A Dif_etreg.h57 #define ET_PCIR_DEVICE_CAPS 0x4C
58 #define ET_PCIM_DEVICE_CAPS_MAX_PLSZ 0x7 /* Max playload size */
59 #define ET_PCIV_DEVICE_CAPS_PLSZ_128 0x0
60 #define ET_PCIV_DEVICE_CAPS_PLSZ_256 0x1
62 #define ET_PCIR_DEVICE_CTRL 0x50
63 #define ET_PCIM_DEVICE_CTRL_MAX_RRSZ 0x7000 /* Max read request size */
64 #define ET_PCIV_DEVICE_CTRL_RRSZ_2K 0x4000
66 #define ET_PCIR_MAC_ADDR0 0xA4
67 #define ET_PCIR_MAC_ADDR1 0xA8
69 #define ET_PCIR_EEPROM_STATUS 0xB2 /* XXX undocumented */
[all …]
/freebsd/sys/dev/ntb/ntb_hw/
H A Dntb_hw_intel.h42 * Params: [in] P = Bit position of start of the bit field (lsb is 0).
51 #define NTB_LINK_STATUS_ACTIVE 0x2000
52 #define NTB_LINK_SPEED_MASK 0x000f
53 #define NTB_LINK_WIDTH_MASK 0x03f0
67 #define XEON_SPCICMD_OFFSET 0x0504
68 #define XEON_DEVCTRL_OFFSET 0x0598
69 #define XEON_DEVSTS_OFFSET 0x059a
70 #define XEON_LINK_STATUS_OFFSET 0x01a2
71 #define XEON_SLINK_STATUS_OFFSET 0x05a2
73 #define XEON_PBAR2LMT_OFFSET 0x0000
[all …]
/freebsd/sys/dev/ath/ath_hal/ar5210/
H A Dar5210reg.h28 #define PCI_VENDOR_ATHEROS 0x168c
30 #define PCI_PRODUCT_ATHEROS_AR5210 0x0007
31 #define PCI_PRODUCT_ATHEROS_AR5210_OLD 0x0004
34 #define AR_TXDP0 0x0000 /* TX queue pointer 0 register */
35 #define AR_TXDP1 0x0004 /* TX queue pointer 1 register */
36 #define AR_CR 0x0008 /* Command register */
37 #define AR_RXDP 0x000c /* RX queue descriptor ptr register */
38 #define AR_CFG 0x0014 /* Configuration and status register */
39 #define AR_ISR 0x001c /* Interrupt status register */
40 #define AR_IMR 0x0020 /* Interrupt mask register */
[all …]
/freebsd/sys/dev/gem/
H A Dif_gemreg.h37 #define GEM_SEB_STATE 0x0000 /* SEB state reg, R/O */
38 #define GEM_CONFIG 0x0004 /* config reg */
39 #define GEM_STATUS 0x000c /* status reg */
40 /* Note: Reading the status reg clears bits 0-6. */
41 #define GEM_INTMASK 0x0010
42 #define GEM_INTACK 0x0014 /* Interrupt acknowledge, W/O */
43 #define GEM_STATUS_ALIAS 0x001c
46 #define GEM_SEB_ARB 0x00000002 /* Arbitration status */
47 #define GEM_SEB_RXWON 0x00000004
50 #define GEM_CONFIG_BURST_64 0x00000000 /* maximum burst size 64KB */
[all …]
/freebsd/lib/libpmc/pmu-events/arch/arm64/
H A Dcommon-and-microarch.json4 "EventCode": "0x00",
10 "EventCode": "0x01",
16 "EventCode": "0x02",
22 "EventCode": "0x03",
28 "EventCode": "0x04",
34 "EventCode": "0x05",
40 "EventCode": "0x06",
46 "EventCode": "0x07",
52 "EventCode": "0x08",
58 "EventCode": "0x09",
[all …]
/freebsd/lib/libc/softfloat/
H A Dtimesoftfloat.c91 0xFFFFBB79, 0x405CF80F, 0x00000000, 0xFFFFFD04,
92 0xFFF20002, 0x0C8EF795, 0xF00011FF, 0x000006CA,
93 0x00009BFE, 0xFF4862E3, 0x9FFFEFFE, 0xFFFFFFB7,
94 0x0BFF7FFF, 0x0000F37A, 0x0011DFFE, 0x00000006,
95 0xFFF02006, 0xFFFFF7D1, 0x10200003, 0xDE8DF765,
96 0x00003E02, 0x000019E8, 0x0008FFFE, 0xFFFFFB5C,
97 0xFFDF7FFE, 0x07C42FBF, 0x0FFFE3FF, 0x040B9F13,
98 0xBFFFFFF8, 0x0001BF56, 0x000017F6, 0x000A908A
107 count = 0; in time_a_int32_z_float32()
108 inputNum = 0; in time_a_int32_z_float32()
[all …]
/freebsd/sys/dev/smartpqi/
H A Dsmartpqi_defines.h44 #define PQI_STATUS_SUCCESS 0
47 #define PQI_VENDOR_GENERAL_CONFIG_TABLE_UPDATE 0
65 #define INVALID_ELEM 0xffff
78 #define INT_MAX 0x7FFFFFFF
87 (offsetof(TYPE, MEMBER) + sizeof(((TYPE *)0)->MEMBER))
125 #define false 0
134 #define INTR_TYPE_NONE 0x0
135 #define INTR_TYPE_FIXED 0x1
136 #define INTR_TYPE_MSI 0x2
137 #define INTR_TYPE_MSIX 0x4
[all …]
/freebsd/sys/dev/bxe/
H A D57711_int_offsets.h31 { 0x40, 0x0, 0x0, 0x0, 0x0}, // COMMON_SB_SIZE
32 { 0x40, 0x0, 0x0, 0x0, 0x0}, // COMMON_SB_DATA_SIZE
33 { 0x28, 0x0, 0x0, 0x0, 0x0}, // COMMON_SP_SB_SIZE
34 { 0x10, 0x0, 0x0, 0x0, 0x0}, // COMMON_SP_SB_DATA_SIZE
35 { 0x40, 0x0, 0x0, 0x0, 0x0}, // COMMON_DYNAMIC_HC_CONFIG_SIZE
36 { 0x10, 0x0, 0x0, 0x0, 0x0}, // COMMON_ASM_ASSERT_MSG_SIZE
37 { 0x8, 0x0, 0x0, 0x0, 0x0}, // COMMON_ASM_ASSERT_INDEX_SIZE
38 { 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_ASM_INVALID_ASSERT_OPCODE
39 { 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_RAM1_TEST_EVENT_ID
40 …{ 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_INBOUND_INTERRUPT_TEST_AGG_INT_EVEN…
[all …]
H A Decore_hsi.h33 #define FW_ENCODE_32BIT_PATTERN 0x1e1e1e1e
39 #define LICENSE_MAX_ISCSI_TRGT_CONN_MASK 0xFFFF
40 #define LICENSE_MAX_ISCSI_TRGT_CONN_SHIFT 0
41 #define LICENSE_MAX_ISCSI_INIT_CONN_MASK 0xFFFF0000
47 #define LICENSE_MAX_FCOE_TRGT_CONN_MASK 0xFFFF
48 #define LICENSE_MAX_FCOE_TRGT_CONN_SHIFT 0
49 #define LICENSE_MAX_FCOE_INIT_CONN_MASK 0xFFFF0000
61 #define PIN_CFG_NA 0x00000000
62 #define PIN_CFG_GPIO0_P0 0x00000001
63 #define PIN_CFG_GPIO1_P0 0x00000002
[all …]
/freebsd/sys/dev/ath/ath_hal/ar5211/
H A Dar5211reg.h32 #define AR_CR 0x0008 /* control register */
33 #define AR_RXDP 0x000C /* receive queue descriptor pointer */
34 #define AR_CFG 0x0014 /* configuration and status register */
35 #define AR_IER 0x0024 /* Interrupt enable register */
36 #define AR_RTSD0 0x0028 /* RTS Duration Parameters 0 */
37 #define AR_RTSD1 0x002c /* RTS Duration Parameters 1 */
38 #define AR_TXCFG 0x0030 /* tx DMA size config register */
39 #define AR_RXCFG 0x0034 /* rx DMA size config register */
40 #define AR5211_JUMBO_LAST 0x0038 /* Jumbo descriptor last address */
41 #define AR_MIBC 0x0040 /* MIB control register */
[all …]
/freebsd/sys/dev/cas/
H A Dif_casreg.h42 #define CAS_CAW 0x0004 /* core arbitration weight */
43 #define CAS_INF_BURST 0x0008 /* infinite burst enable */
44 #define CAS_STATUS 0x000c /* interrupt status */
45 #define CAS_INTMASK 0x0010 /* interrupt mask */
46 #define CAS_CLEAR_ALIAS 0x0014 /* clear mask alias */
47 #define CAS_STATUS_ALIAS 0x001c /* interrupt status alias */
48 #define CAS_ERROR_STATUS 0x1000 /* PCI error status */
49 #define CAS_ERROR_MASK 0x1004 /* PCI error mask */
50 #define CAS_BIM_CONF 0x1008 /* BIM configuration */
51 #define CAS_BIM_DIAG 0x100c /* BIM diagnostic */
[all …]
/freebsd/sys/dev/ath/ath_hal/ar5212/
H A Dar5212reg.h27 #define AR_CR 0x0008 /* MAC control register */
28 #define AR_RXDP 0x000C /* MAC receive queue descriptor pointer */
29 #define AR_CFG 0x0014 /* MAC configuration and status register */
30 #define AR_IER 0x0024 /* MAC Interrupt enable register */
31 /* 0x28 is RTSD0 on the 5211 */
32 /* 0x2c is RTSD1 on the 5211 */
33 #define AR_TXCFG 0x0030 /* MAC tx DMA size config register */
34 #define AR_RXCFG 0x0034 /* MAC rx DMA size config register */
35 /* 0x38 is the jumbo descriptor address on the 5211 */
36 #define AR_MIBC 0x0040 /* MAC MIB control register */
[all …]
/freebsd/sys/dev/puc/
H A Dpucdata.c71 { 0x0009, 0x7168, 0xffff, 0,
74 PUC_PORT_2S, 0x10, 0, 8,
77 { 0x103c, 0x1048, 0x103c, 0x1049,
80 PUC_PORT_3S, 0x10, 0, -1,
84 { 0x103c, 0x1048, 0x103c, 0x104a,
87 PUC_PORT_2S, 0x10, 0, -1,
91 { 0x103c, 0x1048, 0x103c, 0x104b,
94 PUC_PORT_4S, 0x10, 0, -1,
98 { 0x103c, 0x1048, 0x103c, 0x1223,
101 PUC_PORT_3S, 0x10, 0, -1,
[all …]
/freebsd/sys/dev/bge/
H A Dif_bgereg.h54 * device register space at offset 0x8000 to read any 32K chunk
60 * accessed directly. NIC memory addresses are offset by 0x01000000.
64 #define BGE_PAGE_ZERO 0x00000000
65 #define BGE_PAGE_ZERO_END 0x000000FF
66 #define BGE_SEND_RING_RCB 0x00000100
67 #define BGE_SEND_RING_RCB_END 0x000001FF
68 #define BGE_RX_RETURN_RING_RCB 0x00000200
69 #define BGE_RX_RETURN_RING_RCB_END 0x000002FF
70 #define BGE_STATS_BLOCK 0x00000300
71 #define BGE_STATS_BLOCK_END 0x00000AFF
[all …]
/freebsd/share/i18n/csmapper/CNS/
H A DCNS11643-4%UCS@BMP.src5 SRC_ZONE 0x21-0x7E / 0x21-0x7E / 8
7 DST_INVALID 0xFFFE
13 # Unicode version: 5.0.0
47 0x2122 = 0x4E40
48 0x2123 = 0x4E41
49 0x2124 = 0x4E5A
50 0x2126 = 0x4E02
51 0x2127 = 0x4E29
52 0x212A = 0x5202
53 0x212B = 0x353E
[all …]
H A DUCS@BMP%CNS11643-4.src5 SRC_ZONE 0x3401 - 0x9F9E
7 DST_INVALID 0xFFFF
13 # Unicode version: 5.0.0
47 0x3401 = 0x2224
48 0x340C = 0x2157
49 0x3416 = 0x2336
50 0x341C = 0x2835
51 0x342C = 0x2337
52 0x342D = 0x2534
53 0x3430 = 0x2159
[all …]

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