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/freebsd/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dwasp_reg_map.h20 volatile char pad__0[0x4000]; /* 0x0 - 0x4000 */
21 volatile u_int32_t HOST_INTF_RESET_CONTROL; /* 0x4000 - 0x4004 */
22 volatile u_int32_t HOST_INTF_PM_CTRL; /* 0x4004 - 0x4008 */
23 volatile u_int32_t HOST_INTF_TIMEOUT; /* 0x4008 - 0x400c */
24 volatile u_int32_t HOST_INTF_SREV; /* 0x400c - 0x4010 */
25 volatile u_int32_t HOST_INTF_INTR_SYNC_CAUSE; /* 0x4010 - 0x4014 */
26 volatile u_int32_t HOST_INTF_INTR_SYNC_ENABLE; /* 0x4014 - 0x4018 */
27 volatile u_int32_t HOST_INTF_INTR_ASYNC_MASK; /* 0x4018 - 0x401c */
28 volatile u_int32_t HOST_INTF_INTR_SYNC_MASK; /* 0x401c - 0x4020 */
29 volatile u_int32_t HOST_INTF_INTR_ASYNC_CAUSE; /* 0x4020 - 0x4024 */
[all …]
/freebsd/sys/contrib/device-tree/Bindings/arm/apple/
H A Dapple,pmgr.yaml20 pattern: "^power-management@[0-9a-f]+$"
42 "power-controller@[0-9a-f]+$":
64 reg = <0x2 0x3b700000 0x0 0x14000>;
68 reg = <0x1c0 8>;
69 #power-domain-cells = <0>;
70 #reset-cells = <0>;
77 reg = <0x220 8>;
78 #power-domain-cells = <0>;
79 #reset-cells = <0>;
86 reg = <0x270 8>;
[all …]
/freebsd/contrib/arm-optimized-routines/string/aarch64/
H A Dstrchrnul.S40 two bits per byte (LSB is always in bits 0 and 1, for both big
41 and little-endian systems). For each tuple, bit 0 is set iff
50 /* Magic constant 0x40100401 to allow us to identify which lane
52 mov wtmp2, #0x0401
53 movk wtmp2, #0x4010, lsl #16
74 mov tmp3, #~0
78 mov tmp3, vend1.d[0]
91 mov tmp1, vend1.d[0]
101 mov tmp1, vend1.d[0]
H A Dmemchr.S42 * per byte. For each tuple, bit 0 is set if the relevant byte matched the
53 * Magic constant 0x40100401 allows us to identify which lane matches
56 mov wtmp2, #0x0401
57 movk wtmp2, #0x4010, lsl #16
81 mov synd, vend.d[0]
101 mov synd, vend.d[0]
111 mov synd, vend.d[0]
130 cmp synd, #0
140 mov result, #0
H A Dstrrchr.S48 two bits per byte (LSB is always in bits 0 and 1, for both big
49 and little-endian systems). For each tuple, bit 0 is set iff
58 /* Magic constant 0x40100401 to allow us to identify which lane
59 matches the requested byte. Magic constant 0x80200802 used
61 mov wtmp2, #0x0401
62 movk wtmp2, #0x4010, lsl #16
66 mov src_offset, #0
77 cmeq vhas_nul1.16b, vdata1.16b, #0
79 cmeq vhas_nul2.16b, vdata2.16b, #0
88 mov nul_match, vend1.d[0]
[all …]
/freebsd/sys/dev/et/
H A Dif_etreg.h57 #define ET_PCIR_DEVICE_CAPS 0x4C
58 #define ET_PCIM_DEVICE_CAPS_MAX_PLSZ 0x7 /* Max playload size */
59 #define ET_PCIV_DEVICE_CAPS_PLSZ_128 0x0
60 #define ET_PCIV_DEVICE_CAPS_PLSZ_256 0x1
62 #define ET_PCIR_DEVICE_CTRL 0x50
63 #define ET_PCIM_DEVICE_CTRL_MAX_RRSZ 0x7000 /* Max read request size */
64 #define ET_PCIV_DEVICE_CTRL_RRSZ_2K 0x4000
66 #define ET_PCIR_MAC_ADDR0 0xA4
67 #define ET_PCIR_MAC_ADDR1 0xA8
69 #define ET_PCIR_EEPROM_STATUS 0xB2 /* XXX undocumented */
[all …]
/freebsd/sys/dev/ntb/ntb_hw/
H A Dntb_hw_intel.h42 * Params: [in] P = Bit position of start of the bit field (lsb is 0).
51 #define NTB_LINK_STATUS_ACTIVE 0x2000
52 #define NTB_LINK_SPEED_MASK 0x000f
53 #define NTB_LINK_WIDTH_MASK 0x03f0
67 #define XEON_SPCICMD_OFFSET 0x0504
68 #define XEON_DEVCTRL_OFFSET 0x0598
69 #define XEON_DEVSTS_OFFSET 0x059a
70 #define XEON_LINK_STATUS_OFFSET 0x01a2
71 #define XEON_SLINK_STATUS_OFFSET 0x05a2
73 #define XEON_PBAR2LMT_OFFSET 0x0000
[all …]
/freebsd/sys/contrib/device-tree/src/arm/nxp/mxs/
H A Dimx28-pinfunc.h13 #define MX28_PAD_GPMI_D00__GPMI_D0 0x0000
14 #define MX28_PAD_GPMI_D01__GPMI_D1 0x0010
15 #define MX28_PAD_GPMI_D02__GPMI_D2 0x0020
16 #define MX28_PAD_GPMI_D03__GPMI_D3 0x0030
17 #define MX28_PAD_GPMI_D04__GPMI_D4 0x0040
18 #define MX28_PAD_GPMI_D05__GPMI_D5 0x0050
19 #define MX28_PAD_GPMI_D06__GPMI_D6 0x0060
20 #define MX28_PAD_GPMI_D07__GPMI_D7 0x0070
21 #define MX28_PAD_GPMI_CE0N__GPMI_CE0N 0x0100
22 #define MX28_PAD_GPMI_CE1N__GPMI_CE1N 0x0110
[all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/westmereex/
H A Dmemory.json4 "Counter": "0,1,2,3",
5 "EventCode": "0x5",
8 "UMask": "0x2"
13 "EventCode": "0xB7",
15 "MSRIndex": "0x1A6",
16 "MSRValue": "0x6011",
19 "UMask": "0x1"
24 "EventCode": "0xB7",
26 "MSRIndex": "0x1A6",
27 "MSRValue": "0xF811",
[all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/nehalemep/
H A Dmemory.json5 "EventCode": "0xB7",
7 "MSRIndex": "0x1A6",
8 "MSRValue": "0x6011",
11 "UMask": "0x1"
16 "EventCode": "0xB7",
18 "MSRIndex": "0x1A6",
19 "MSRValue": "0xF811",
22 "UMask": "0x1"
27 "EventCode": "0xB7",
29 "MSRIndex": "0x1A6",
[all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/nehalemex/
H A Dmemory.json3 "EventCode": "0xB7",
4 "MSRValue": "0x6011",
6 "UMask": "0x1",
8 "MSRIndex": "0x1A6",
14 "EventCode": "0xB7",
15 "MSRValue": "0xF811",
17 "UMask": "0x1",
19 "MSRIndex": "0x1A6",
25 "EventCode": "0xB7",
26 "MSRValue": "0x4011",
[all …]
/freebsd/contrib/file/magic/Magdir/
H A Dmsx11 0 string/b MGS MSX Gigamix MGSDRV3 music file,
12 >6 ubeshort 0x0D0A
16 >>8 string >\0 \b, title: %s
19 >6 uleshort 0x80
20 >>0x2E uleshort 0
21 >>>0x30 string >\0 \b, title: %s
24 0 string/b KSCC KSS music file v1.03
25 >0xE byte 0
26 >>0xF byte&0x02 0 \b, soundchips: AY-3-8910, SCC(+)
27 >>0xF byte&0x02 2 \b, soundchip(s): SN76489
[all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/westmereep-dp/
H A Dmemory.json4 "Counter": "0,1,2,3",
5 "EventCode": "0x5",
8 "UMask": "0x2"
12 "Counter": "0,1,2,3",
13 "EventCode": "0xB7, 0xBB",
15 "MSRIndex": "0x1a6,0x1a7",
16 "MSRValue": "0x3011",
19 "UMask": "0x1"
23 "Counter": "0,1,2,3",
24 "EventCode": "0xB7, 0xBB",
[all …]
/freebsd/lib/libpmc/pmu-events/arch/x86/westmereep-sp/
H A Dmemory.json4 "Counter": "0,1,2,3",
5 "EventCode": "0xB7, 0xBB",
7 "MSRIndex": "0x1a6,0x1a7",
8 "MSRValue": "0x6011",
11 "UMask": "0x1"
15 "Counter": "0,1,2,3",
16 "EventCode": "0xB7, 0xBB",
18 "MSRIndex": "0x1a6,0x1a7",
19 "MSRValue": "0xF811",
22 "UMask": "0x1"
[all …]
/freebsd/sys/dev/ath/ath_hal/ar5210/
H A Dar5210reg.h28 #define PCI_VENDOR_ATHEROS 0x168c
30 #define PCI_PRODUCT_ATHEROS_AR5210 0x0007
31 #define PCI_PRODUCT_ATHEROS_AR5210_OLD 0x0004
34 #define AR_TXDP0 0x0000 /* TX queue pointer 0 register */
35 #define AR_TXDP1 0x0004 /* TX queue pointer 1 register */
36 #define AR_CR 0x0008 /* Command register */
37 #define AR_RXDP 0x000c /* RX queue descriptor ptr register */
38 #define AR_CFG 0x0014 /* Configuration and status register */
39 #define AR_ISR 0x001c /* Interrupt status register */
40 #define AR_IMR 0x0020 /* Interrupt mask register */
[all …]
/freebsd/sys/arm/broadcom/bcm2835/
H A Dbcm2838_pci.c55 #define PCI_ID_VAL3 0x43c
56 #define CLASS_SHIFT 0x10
57 #define SUBCLASS_SHIFT 0x8
59 #define REG_CONTROLLER_HW_REV 0x406c
60 #define REG_BRIDGE_CTRL 0x9210
61 #define BRIDGE_DISABLE_FLAG 0x1
62 #define BRIDGE_RESET_FLAG 0x2
63 #define REG_PCIE_HARD_DEBUG 0x4204
64 #define REG_DMA_CONFIG 0x4008
65 #define REG_DMA_WINDOW_LOW 0x4034
[all …]
/freebsd/sys/dev/gem/
H A Dif_gemreg.h37 #define GEM_SEB_STATE 0x0000 /* SEB state reg, R/O */
38 #define GEM_CONFIG 0x0004 /* config reg */
39 #define GEM_STATUS 0x000c /* status reg */
40 /* Note: Reading the status reg clears bits 0-6. */
41 #define GEM_INTMASK 0x0010
42 #define GEM_INTACK 0x0014 /* Interrupt acknowledge, W/O */
43 #define GEM_STATUS_ALIAS 0x001c
46 #define GEM_SEB_ARB 0x00000002 /* Arbitration status */
47 #define GEM_SEB_RXWON 0x00000004
50 #define GEM_CONFIG_BURST_64 0x00000000 /* maximum burst size 64KB */
[all …]
/freebsd/lib/libpmc/pmu-events/arch/arm64/
H A Dcommon-and-microarch.json4 "EventCode": "0x00",
10 "EventCode": "0x01",
16 "EventCode": "0x02",
22 "EventCode": "0x03",
28 "EventCode": "0x04",
34 "EventCode": "0x05",
40 "EventCode": "0x06",
46 "EventCode": "0x07",
52 "EventCode": "0x08",
58 "EventCode": "0x09",
[all …]
/freebsd/share/man/man4/
H A Diwlwififw.460 .It 0x8086 Ta 0x08b1 Ta any Ta 0x4070 Ta iwlwifi-7260
63 .It 0x8086 Ta 0x08b1 Ta any Ta 0x4072 Ta iwlwifi-7260
66 .It 0x8086 Ta 0x08b1 Ta any Ta 0x4170 Ta iwlwifi-7260
69 .It 0x808
[all...]
/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Domap5.dtsi45 #size-cells = <0>;
47 cpu0: cpu@0 {
50 reg = <0x0>;
69 reg = <0x1>;
115 reg = <0 0x40300000 0 0x20000>; /* 128k */
122 reg = <0 0x48211000 0 0x1000>,
123 <0 0x48212000 0 0x2000>,
124 <0 0x48214000 0 0x2000>,
125 <0 0x48216000 0 0x2000>;
133 reg = <0 0x48281000 0 0x1000>;
[all …]
H A Domap4.dtsi40 #size-cells = <0>;
42 cpu@0 {
46 reg = <0x0>;
57 reg = <0x1>;
67 reg = <0x40304000 0xa000>; /* 40k */
74 reg = <0x48241000 0x1000>,
75 <0x48240100 0x0100>;
81 reg = <0x48242000 0x1000>;
89 reg = <0x48240600 0x20>;
98 reg = <0x48281000 0x1000>;
[all …]
H A Domap5-l4.dtsi1 &l4_cfg { /* 0x4a000000 */
4 clocks = <&l4cfg_clkctrl OMAP5_L4_CFG_CLKCTRL 0>;
6 reg = <0x4a000000 0x800>,
7 <0x4a000800 0x800>,
8 <0x4a001000 0x1000>;
12 ranges = <0x00000000 0x4a000000 0x080000>, /* segment 0 */
13 <0x00080000 0x4a080000 0x080000>, /* segment 1 */
14 <0x00100000 0x4a100000 0x080000>, /* segment 2 */
15 <0x00180000 0x4a180000 0x080000>, /* segment 3 */
16 <0x00200000 0x4a200000 0x080000>, /* segment 4 */
[all …]
/freebsd/sys/contrib/dev/iwlwifi/pcie/
H A Ddrv.c23 #define TRANS_CFG_MARKER BIT(0)
30 __builtin_choose_expr(_IS_A(cfg, iwl_cfg), 0, _invalid_type)))
41 {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */
42 {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */
43 {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */
44 {IWL_PCI_DEVICE(0x4232, 0x130
[all...]
/freebsd/sys/dev/smartpqi/
H A Dsmartpqi_defines.h44 #define PQI_STATUS_SUCCESS 0
47 #define PQI_VENDOR_GENERAL_CONFIG_TABLE_UPDATE 0
65 #define INVALID_ELEM 0xffff
78 #define INT_MAX 0x7FFFFFFF
87 (offsetof(TYPE, MEMBER) + sizeof(((TYPE *)0)->MEMBER))
125 #define false 0
134 #define INTR_TYPE_NONE 0x0
135 #define INTR_TYPE_FIXED 0x1
136 #define INTR_TYPE_MSI 0x2
137 #define INTR_TYPE_MSIX 0x4
[all …]
/freebsd/sys/dev/isp/
H A Dispmbox.h41 #define MBOX_NO_OP 0x0000
42 #define MBOX_LOAD_RAM 0x0001
43 #define MBOX_EXEC_FIRMWARE 0x0002
44 #define MBOX_LOAD_FLASH_FIRMWARE 0x0003
45 #define MBOX_WRITE_RAM_WORD 0x0004
46 #define MBOX_READ_RAM_WORD 0x0005
47 #define MBOX_MAILBOX_REG_TEST 0x0006
48 #define MBOX_VERIFY_CHECKSUM 0x0007
49 #define MBOX_ABOUT_FIRMWARE 0x0008
50 #define MBOX_LOAD_RISC_RAM_2100 0x0009
[all …]

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