Searched +full:0 +full:x40023800 (Results 1 – 4 of 4) sorted by relevance
110 - The first cell is the clock type, possible values are 0 for125 reg = <0x40023800 0x400>;137 reg = <0x58024400 0x400>;
33 reg = <0x40023800 0x400>;40 The primary index must be set to 0.43 from the first RCC clock enable register (RCC_AHB1ENR, address offset 0x30).46 Where bit_offset is the bit offset within the register (LSB is 0, MSB is 31).57 /* Gated clock, AHB1 bit 0 (GPIOA) */59 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>64 clocks = <&rcc 0 STM32F4_AHB2_CLOCK(CRYP)>74 0 SYSTICK132 crc = AHB1RSTR_offset / 4 * 32 + CRCRST_bit_offset = 0x10 / 4 * 32 + 12 = 140
54 #clock-cells = <0>;56 clock-frequency = <0>;60 #clock-cells = <0>;66 #clock-cells = <0>;72 #clock-cells = <0>;81 #size-cells = <0>;83 reg = <0x40000000 0x400>;84 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;103 #size-cells = <0>;105 reg = <0x40000400 0x400>;[all …]
58 #clock-cells = <0>;60 clock-frequency = <0>;64 #clock-cells = <0>;70 #clock-cells = <0>;76 #clock-cells = <0>;78 clock-frequency = <0>;85 reg = <0x1fff7800 0x400>;89 reg = <0x22c 0x2>;92 reg = <0x22e 0x2>;98 #size-cells = <0>;[all …]