Searched +full:0 +full:x40000c00 (Results 1 – 6 of 6) sorted by relevance
43 reg = <0x40000c00 0x400>;
33 reg = <0x58024400 0x400>;48 reg = <0x40000c00 0x400>;65 crc = AHB4RSTR_offset / 4 * 32 + CRCRST_bit_offset = 0x88 / 4 * 32 + 19 = 1107
20 dcr-parent = <&{/cpus/cpu@0}>;31 #size-cells = <0>;33 cpu@0 {36 reg = <0x00000000>;38 timebase-frequency = <0>; // Filled in by zImage50 reg = <0x00000000 0x00000000 0x00000000>; // Filled in by zImage58 dcr-reg = <0x200 0x009>;59 #address-cells = <0>;60 #size-cells = <0>;68 cell-index = <0>;[all …]
53 #clock-cells = <0>;55 clock-frequency = <0>;59 #clock-cells = <0>;65 #clock-cells = <0>;71 #clock-cells = <0>;80 #size-cells = <0>;82 reg = <0x40000000 0x400>;83 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;102 #size-cells = <0>;104 reg = <0x40000400 0x400>;[all …]
58 #clock-cells = <0>;60 clock-frequency = <0>;64 #clock-cells = <0>;70 #clock-cells = <0>;76 #clock-cells = <0>;78 clock-frequency = <0>;85 reg = <0x1fff7800 0x400>;89 reg = <0x22c 0x2>;92 reg = <0x22e 0x2>;98 #size-cells = <0>;[all …]
54 #clock-cells = <0>;56 clock-frequency = <0>;60 #clock-cells = <0>;66 #clock-cells = <0>;68 clock-frequency = <0>;75 reg = <0x40000c00 0x400>;82 #size-cells = <0>;84 reg = <0x40002400 0x400>;95 trigger@0 {97 reg = <0>;[all …]