Lines Matching +full:0 +full:x40000c00
58 #clock-cells = <0>;
60 clock-frequency = <0>;
64 #clock-cells = <0>;
70 #clock-cells = <0>;
76 #clock-cells = <0>;
78 clock-frequency = <0>;
85 reg = <0x1fff7800 0x400>;
89 reg = <0x22c 0x2>;
92 reg = <0x22e 0x2>;
98 #size-cells = <0>;
100 reg = <0x40000000 0x400>;
101 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
120 #size-cells = <0>;
122 reg = <0x40000400 0x400>;
123 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
142 #size-cells = <0>;
144 reg = <0x40000800 0x400>;
145 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
164 #size-cells = <0>;
166 reg = <0x40000C00 0x400>;
167 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
186 #size-cells = <0>;
188 reg = <0x40001000 0x400>;
189 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
202 #size-cells = <0>;
204 reg = <0x40001400 0x400>;
205 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
218 #size-cells = <0>;
220 reg = <0x40001800 0x400>;
221 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM12)>;
240 reg = <0x40001C00 0x400>;
241 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>;
254 reg = <0x40002000 0x400>;
255 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>;
268 reg = <0x40002800 0x400>;
274 st,syscfg = <&pwrcfg 0x00 0x100>;
280 reg = <0x40003000 0x400>;
288 #size-cells = <0>;
290 reg = <0x40003800 0x400>;
292 clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI2)>;
298 #size-cells = <0>;
300 reg = <0x40003c00 0x400>;
302 clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI3)>;
308 reg = <0x40004400 0x400>;
310 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART2)>;
316 reg = <0x40004800 0x400>;
318 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART3)>;
320 dmas = <&dma1 1 4 0x400 0x0>,
321 <&dma1 3 4 0x400 0x0>;
327 reg = <0x40004c00 0x400>;
329 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART4)>;
335 reg = <0x40005000 0x400>;
337 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART5)>;
343 reg = <0x40005400 0x400>;
347 clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C1)>;
349 #size-cells = <0>;
355 reg = <0x40005c00 0x400>;
359 clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C3)>;
361 #size-cells = <0>;
367 reg = <0x40006400 0x200>;
371 clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN1)>;
379 reg = <0x40006600 0x200>;
380 clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN1)>;
385 reg = <0x40006800 0x200>;
389 clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN2)>;
397 reg = <0x40007400 0x400>;
399 clocks = <&rcc 0 STM32F4_APB1_CLOCK(DAC)>;
402 #size-cells = <0>;
422 reg = <0x40007800 0x400>;
424 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART7)>;
430 reg = <0x40007c00 0x400>;
432 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART8)>;
438 #size-cells = <0>;
440 reg = <0x40010000 0x400>;
441 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM1)>;
451 timer@0 {
453 reg = <0>;
460 #size-cells = <0>;
462 reg = <0x40010400 0x400>;
463 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM8)>;
482 reg = <0x40011000 0x400>;
484 clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART1)>;
486 dmas = <&dma2 2 4 0x400 0x0>,
487 <&dma2 7 4 0x400 0x0>;
493 reg = <0x40011400 0x400>;
495 clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART6)>;
501 reg = <0x40012000 0x400>;
503 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
508 #size-cells = <0>;
511 adc1: adc@0 {
514 reg = <0x0>;
515 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
517 interrupts = <0>;
518 dmas = <&dma2 0 0 0x400 0x0>;
526 reg = <0x100>;
527 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC2)>;
530 dmas = <&dma2 3 1 0x400 0x0>;
538 reg = <0x200>;
539 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC3)>;
542 dmas = <&dma2 1 2 0x400 0x0>;
550 arm,primecell-periphid = <0x00880180>;
551 reg = <0x40012c00 0x400>;
552 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SDIO)>;
561 #size-cells = <0>;
563 reg = <0x40013000 0x400>;
565 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI1)>;
571 #size-cells = <0>;
573 reg = <0x40013400 0x400>;
575 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI4)>;
581 reg = <0x40013800 0x400>;
582 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SYSCFG)>;
589 reg = <0x40013C00 0x400>;
595 #size-cells = <0>;
597 reg = <0x40014000 0x400>;
598 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM9)>;
617 reg = <0x40014400 0x400>;
618 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM10)>;
631 reg = <0x40014800 0x400>;
632 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM11)>;
645 #size-cells = <0>;
647 reg = <0x40015000 0x400>;
649 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI5)>;
650 dmas = <&dma2 3 2 0x400 0x0>,
651 <&dma2 4 2 0x400 0x0>;
658 #size-cells = <0>;
660 reg = <0x40015400 0x400>;
662 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI6)>;
668 reg = <0x40007000 0x400>;
673 reg = <0x40016800 0x200>;
683 reg = <0x40023000 0x400>;
684 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(CRC)>;
692 reg = <0x40023800 0x400>;
701 reg = <0x40026000 0x400>;
710 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA1)>;
716 reg = <0x40026400 0x400>;
725 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2)>;
732 reg = <0x40028000 0x8000>;
737 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(ETHMAC)>,
738 <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACTX)>,
739 <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACRX)>;
740 st,syscon = <&syscfg 0x4>;
748 reg = <0x4002b000 0xc00>;
751 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2D)>;
758 reg = <0x40040000 0x40000>;
760 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHS)>;
767 reg = <0x50000000 0x40000>;
769 clocks = <&rcc 0 39>;
776 reg = <0x50050000 0x400>;
779 clocks = <&rcc 0 STM32F4_AHB2_CLOCK(DCMI)>;
782 pinctrl-0 = <&dcmi_pins>;
783 dmas = <&dma2 1 1 0x414 0x3>;
790 reg = <0x50060800 0x400>;
791 clocks = <&rcc 0 STM32F4_AHB2_CLOCK(RNG)>;