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/linux/drivers/crypto/cavium/nitrox/
H A Dnitrox_csr.h21 #define EMU_BIST_STATUSX(_i) (0x1402700 + ((_i) * 0x40000))
22 #define UCD_BIST_STATUS 0x12C0070
23 #define NPS_CORE_BIST_REG 0x10000E8
24 #define NPS_CORE_NPC_BIST_REG 0x1000128
25 #define NPS_PKT_SLC_BIST_REG 0x1040088
26 #define NPS_PKT_IN_BIST_REG 0x1040100
27 #define POM_BIST_REG 0x11C0100
28 #define BMI_BIST_REG 0x1140080
29 #define EFL_CORE_BIST_REGX(_i) (0x1240100 + ((_i) * 0x400))
30 #define EFL_TOP_BIST_STAT 0x1241090
[all …]
/linux/arch/arm/boot/dts/microchip/
H A Dat91sam9x5cm.dtsi11 reg = <0x20000000 0x8000000>;
27 timer@0 {
29 reg = <0>;
40 pinctrl_1wire_cm: 1wire_cm-0 {
52 pinctrl-0 = <&pinctrl_ebi_addr_nand
59 pinctrl-0 = <&pinctrl_nand_oe_we
65 reg = <0x3 0x0 0x800000>;
80 at91bootstrap@0 {
82 reg = <0x0 0x40000>;
87 reg = <0x40000 0xc0000>;
[all …]
H A Daks-cdu.dts33 rs485-rts-delay = <0 0>;
39 rs485-rts-delay = <0 0>;
45 rs485-rts-delay = <0 0>;
68 bootstrap@0 {
70 reg = <0x0 0x40000>;
75 reg = <0x40000 0x80000>;
80 reg = <0xc0000 0x40000>;
85 reg = <0x100000 0x400000>;
90 reg = <0x500000 0x7b00000>;
H A Dat91-sam9x60ek.dts40 pinctrl-0 = <&pinctrl_key_gpio_default>;
53 pinctrl-0 = <&pinctrl_gpio_leds>;
110 pinctrl-0 = <&pinctrl_adc_default &pinctrl_adtrg_default>;
116 pinctrl-0 = <&pinctrl_can0_rx_tx>;
122 pinctrl-0 = <&pinctrl_can1_rx_tx>;
128 pinctrl-0 = <&pinctrl_classd_default>;
136 pinctrl-0 = <&pinctrl_dbgu>;
142 pinctrl-0 = <&pinctrl_ebi_addr_nand &pinctrl_ebi_data_0_7>;
147 pinctrl-0 = <&pinctrl_nand_oe_we &pinctrl_nand_cs &pinctrl_nand_rb>;
151 reg = <0x3 0x0 0x800000>;
[all …]
H A Dat91-sama5d4_xplained.dts21 reg = <0x20000000 0x20000000>;
51 pinctrl-0 = <&pinctrl_macb0_rmii &pinctrl_macb0_phy_irq>;
62 pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3 &pinctrl_mmc1_cd>;
66 slot@0 {
67 reg = <0>;
69 cd-gpios = <&pioE 3 0>;
86 cs-gpios = <&pioB 21 0>;
91 timer0: timer@0 {
93 reg = <0>;
104 pinctrl-0 = <
[all …]
H A Dat91-sama7g54_curiosity.dts34 pinctrl-0 = <&pinctrl_key_gpio_default>;
47 pinctrl-0 = <&pinctrl_led_gpio_default>;
73 reg = <0x60000000 0x10000000>; /* 256 MiB DDR3L-1066 16-bit */
89 pinctrl-0 = <&pinctrl_mikrobus1_an_default &pinctrl_mikrobus2_an_default>;
111 pinctrl-0 = <&pinctrl_nand_default>;
118 reg = <0x3 0x0 0x800000>;
119 atmel,rb = <0>;
132 at91bootstrap@0 {
134 reg = <0x0 0x40000>;
139 reg = <0x40000 0x100000>;
[all …]
H A Dat91-sama5d3_eds.dts26 pinctrl-0 = <&pinctrl_key_gpio>;
31 linux,code = <0x104>;
37 reg = <0x20000000 0x10000000>;
81 pinctrl-0 = <&pinctrl_vcc_mmc0_reg_gpio>;
95 pinctrl-0 = <&pinctrl_ebi_nand_addr>;
103 reg = <0x3 0x0 0x2>;
104 atmel,rb = <0>;
117 at91bootstrap@0 {
119 reg = <0x0 0x40000>;
124 reg = <0x40000 0xc0000>;
[all …]
H A Dat91-nattis-2-natte-2.dts45 pwms = <&hlcdc_pwm 0 100000 0>;
47 brightness-levels = < 0 1 2 3 4 5 6 7 8 9
63 pinctrl-0 = <&pinctrl_blon>;
101 pinctrl-0 = <&pinctrl_lvds_prlud0 &pinctrl_lvds_hipow0>;
105 #size-cells = <0>;
107 port@0 {
108 reg = <0>;
160 AT91_PINCTRL_OUTPUT_VAL(0))>;
166 AT91_PINCTRL_OUTPUT_VAL(0))>;
172 AT91_PINCTRL_OUTPUT_VAL(0))>;
[all …]
H A Dat91-sama5d3_xplained.dts21 reg = <0x20000000 0x10000000>;
37 …pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_dat4_7 &pinctrl_mmc0_cd…
41 slot@0 {
42 reg = <0>;
44 cd-gpios = <&pioE 0 GPIO_ACTIVE_LOW>;
52 slot@0 {
53 reg = <0>;
62 cs-gpios = <&pioD 13 0>, <0>, <0>, <&pioD 16 0>;
71 timer0: timer@0 {
73 reg = <0>;
[all …]
H A Dat91-sama5d2_ptc_ek.dts46 pinctrl-0 = <&pinctrl_usba_vbus>;
52 atmel,vbus-gpio = <0
54 0
57 pinctrl-0 = <&pinctrl_usb_default>;
67 pinctrl-0 = <&pinctrl_nand_default>;
74 reg = <0x3 0x0 0x2>;
75 atmel,rb = <0>;
86 at91bootstrap@0 {
88 reg = <0x0 0x40000>;
93 reg = <0x40000 0xc0000>;
[all …]
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt7986a-bananapi-bpi-r3-nor.dtso16 #size-cells = <0>;
18 flash@0 {
20 reg = <0>;
28 partition@0 {
30 reg = <0x0 0x40000>;
36 reg = <0x40000 0x40000>;
41 reg = <0x80000 0x80000>;
46 reg = <0x100000 0x80000>;
52 reg = <0x180000 0xa80000>;
57 reg = <0xc00000 0x1400000>;
/linux/arch/powerpc/boot/dts/fsl/
H A Dpq3-mpic.dtsi2 * PQ3 MPIC device tree stub [ controller @ offset 0x40000 ]
37 #address-cells = <0>;
39 reg = <0x40000 0x40000>;
49 reg = <0x41100 0x100 0x41300 4>;
50 interrupts = <0 0 3 0
51 1 0 3 0
52 2 0 3 0
53 3 0 3 0>;
58 reg = <0x41400 0x200>;
60 0xb0 2 0 0
[all …]
H A Dqoriq-mpic.dtsi2 * QorIQ MPIC device tree stub [ controller @ offset 0x40000 ]
37 #address-cells = <0>;
39 reg = <0x40000 0x40000>;
42 clock-frequency = <0x0>;
47 reg = <0x41100 0x100 0x41300 4>;
48 interrupts = <0 0 3 0
49 1 0 3 0
50 2 0 3 0
51 3 0 3 0>;
56 reg = <0x41600 0x200 0x44140 4>;
[all …]
H A Dqoriq-mpic4.3.dtsi2 * QorIQ MPIC device tree stub [ controller @ offset 0x40000 ]
37 #address-cells = <0>;
39 reg = <0x40000 0x40000>;
42 clock-frequency = <0x0>;
47 reg = <0x41100 0x100 0x41300 4>;
48 interrupts = <0 0 3 0
49 1 0 3 0
50 2 0 3 0
51 3 0 3 0>;
56 reg = <0x41600 0x200 0x44148 4>;
[all …]
/linux/arch/powerpc/boot/dts/
H A Dxpedite5301.dts16 boot-bank = <0x0>; /* 0: Primary flash, 1: Secondary flash */
29 #size-cells = <0>;
31 PowerPC,8572@0 {
33 reg = <0x0>;
36 d-cache-size = <0x8000>; // L1, 32K
37 i-cache-size = <0x8000>; // L1, 32K
38 timebase-frequency = <0>;
39 bus-frequency = <0>;
40 clock-frequency = <0>;
46 reg = <0x1>;
[all …]
H A Dxpedite5370.dts27 #size-cells = <0>;
29 PowerPC,8572@0 {
31 reg = <0x0>;
34 d-cache-size = <0x8000>; // L1, 32K
35 i-cache-size = <0x8000>; // L1, 32K
36 timebase-frequency = <0>;
37 bus-frequency = <0>;
38 clock-frequency = <0>;
44 reg = <0x1>;
47 d-cache-size = <0x8000>; // L1, 32K
[all …]
H A Dxcalibur1501.dts28 #size-cells = <0>;
30 PowerPC,8572@0 {
32 reg = <0x0>;
35 d-cache-size = <0x8000>; // L1, 32K
36 i-cache-size = <0x8000>; // L1, 32K
37 timebase-frequency = <0>;
38 bus-frequency = <0>;
39 clock-frequency = <0>;
45 reg = <0x1>;
48 d-cache-size = <0x8000>; // L1, 32K
[all …]
H A Dsocrates.dts27 #size-cells = <0>;
29 PowerPC,8544@0 {
31 reg = <0>;
34 d-cache-size = <0x8000>; // L1, 32K
35 i-cache-size = <0x8000>; // L1, 32K
36 timebase-frequency = <0>;
37 bus-frequency = <0>;
38 clock-frequency = <0>;
45 reg = <0x00000000 0x00000000>; // Filled in by U-Boot
53 ranges = <0x00000000 0xe0000000 0x00100000>;
[all …]
H A Dxpedite5330.dts16 boot-bank = <0x0>; /* 0: Primary flash, 1: Secondary flash */
30 #size-cells = <0>;
32 pmcslot@0 {
33 cell-index = <0>;
44 #size-cells = <0>;
46 xmcslot@0 {
47 cell-index = <0>;
65 #size-cells = <0>;
67 PowerPC,8572@0 {
69 reg = <0x0>;
[all …]
/linux/arch/arm/boot/dts/marvell/
H A Darmada-380.dtsi20 #size-cells = <0>;
23 cpu@0 {
26 reg = <0>;
46 bus-range = <0x00 0xff>;
49 <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
50 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
51 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
52 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000
53 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */
54 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/bif/
H A Dbif_5_1_sh_mask.h27 #define MM_INDEX__MM_OFFSET_MASK 0x7fffffff
28 #define MM_INDEX__MM_OFFSET__SHIFT 0x0
29 #define MM_INDEX__MM_APER_MASK 0x80000000
30 #define MM_INDEX__MM_APER__SHIFT 0x1f
31 #define MM_INDEX_HI__MM_OFFSET_HI_MASK 0xffffffff
32 #define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
33 #define MM_DATA__MM_DATA_MASK 0xffffffff
34 #define MM_DATA__MM_DATA__SHIFT 0x0
35 #define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK 0x2
36 #define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT 0x1
[all …]
/linux/arch/mips/include/asm/mach-ralink/
H A Drt3883.h15 #define RT3883_SDRAM_BASE 0x00000000
16 #define RT3883_SYSC_BASE IOMEM(0x10000000)
17 #define RT3883_TIMER_BASE 0x10000100
18 #define RT3883_INTC_BASE 0x10000200
19 #define RT3883_MEMC_BASE 0x10000300
20 #define RT3883_UART0_BASE 0x10000500
21 #define RT3883_PIO_BASE 0x10000600
22 #define RT3883_FSCC_BASE 0x10000700
23 #define RT3883_NANDC_BASE 0x10000810
24 #define RT3883_I2C_BASE 0x10000900
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_8_0_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
36 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
[all …]
H A Dgfx_8_1_sh_mask.h27 #define CB_BLEND_RED__BLEND_RED_MASK 0xffffffff
28 #define CB_BLEND_RED__BLEND_RED__SHIFT 0x0
29 #define CB_BLEND_GREEN__BLEND_GREEN_MASK 0xffffffff
30 #define CB_BLEND_GREEN__BLEND_GREEN__SHIFT 0x0
31 #define CB_BLEND_BLUE__BLEND_BLUE_MASK 0xffffffff
32 #define CB_BLEND_BLUE__BLEND_BLUE__SHIFT 0x0
33 #define CB_BLEND_ALPHA__BLEND_ALPHA_MASK 0xffffffff
34 #define CB_BLEND_ALPHA__BLEND_ALPHA__SHIFT 0x0
35 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE_MASK 0x1
36 #define CB_DCC_CONTROL__OVERWRITE_COMBINER_DISABLE__SHIFT 0x0
[all …]
/linux/arch/arm/boot/dts/ti/omap/
H A Dam335x-guardian.dts22 cpu@0 {
29 reg = <0x80000000 0x10000000>; /* 256 MB */
34 pinctrl-0 = <&guardian_button_pins>;
54 pinctrl-0 = <&guardian_led_pins>;
73 pinctrl-0 = <&lcd_pins_default &lcd_disen_pins>;
87 hsync-active = <0>;
88 vsync-active = <0>;
93 ac-bias-intrpt = <0>;
97 fdd = <0x80>;
98 sync-edge = <0>;
[all …]

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