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/linux/drivers/accel/habanalabs/include/goya/asic_reg/
H A Dpci_nrtr_masks.h23 #define PCI_NRTR_HBW_MAX_CRED_WR_RQ_SHIFT 0
24 #define PCI_NRTR_HBW_MAX_CRED_WR_RQ_MASK 0x3F
26 #define PCI_NRTR_HBW_MAX_CRED_WR_RS_MASK 0x3F00
28 #define PCI_NRTR_HBW_MAX_CRED_RD_RQ_MASK 0x3F0000
30 #define PCI_NRTR_HBW_MAX_CRED_RD_RS_MASK 0x3F000000
33 #define PCI_NRTR_LBW_MAX_CRED_WR_RQ_SHIFT 0
34 #define PCI_NRTR_LBW_MAX_CRED_WR_RQ_MASK 0x3F
36 #define PCI_NRTR_LBW_MAX_CRED_WR_RS_MASK 0x3F00
38 #define PCI_NRTR_LBW_MAX_CRED_RD_RQ_MASK 0x3F0000
40 #define PCI_NRTR_LBW_MAX_CRED_RD_RS_MASK 0x3F000000
[all …]
H A Dtpc0_nrtr_masks.h23 #define TPC0_NRTR_HBW_MAX_CRED_WR_RQ_SHIFT 0
24 #define TPC0_NRTR_HBW_MAX_CRED_WR_RQ_MASK 0x3F
26 #define TPC0_NRTR_HBW_MAX_CRED_WR_RS_MASK 0x3F00
28 #define TPC0_NRTR_HBW_MAX_CRED_RD_RQ_MASK 0x3F0000
30 #define TPC0_NRTR_HBW_MAX_CRED_RD_RS_MASK 0x3F000000
33 #define TPC0_NRTR_LBW_MAX_CRED_WR_RQ_SHIFT 0
34 #define TPC0_NRTR_LBW_MAX_CRED_WR_RQ_MASK 0x3F
36 #define TPC0_NRTR_LBW_MAX_CRED_WR_RS_MASK 0x3F00
38 #define TPC0_NRTR_LBW_MAX_CRED_RD_RQ_MASK 0x3F0000
40 #define TPC0_NRTR_LBW_MAX_CRED_RD_RS_MASK 0x3F000000
[all …]
H A Ddma_nrtr_masks.h23 #define DMA_NRTR_HBW_MAX_CRED_WR_RQ_SHIFT 0
24 #define DMA_NRTR_HBW_MAX_CRED_WR_RQ_MASK 0x3F
26 #define DMA_NRTR_HBW_MAX_CRED_WR_RS_MASK 0x3F00
28 #define DMA_NRTR_HBW_MAX_CRED_RD_RQ_MASK 0x3F0000
30 #define DMA_NRTR_HBW_MAX_CRED_RD_RS_MASK 0x3F000000
33 #define DMA_NRTR_LBW_MAX_CRED_WR_RQ_SHIFT 0
34 #define DMA_NRTR_LBW_MAX_CRED_WR_RQ_MASK 0x3F
36 #define DMA_NRTR_LBW_MAX_CRED_WR_RS_MASK 0x3F00
38 #define DMA_NRTR_LBW_MAX_CRED_RD_RQ_MASK 0x3F0000
40 #define DMA_NRTR_LBW_MAX_CRED_RD_RS_MASK 0x3F000000
[all …]
H A Dmme1_rtr_masks.h23 #define MME1_RTR_HBW_RD_RQ_E_ARB_W_SHIFT 0
24 #define MME1_RTR_HBW_RD_RQ_E_ARB_W_MASK 0x7
26 #define MME1_RTR_HBW_RD_RQ_E_ARB_S_MASK 0x700
28 #define MME1_RTR_HBW_RD_RQ_E_ARB_N_MASK 0x70000
30 #define MME1_RTR_HBW_RD_RQ_E_ARB_L_MASK 0x7000000
33 #define MME1_RTR_HBW_RD_RQ_W_ARB_E_SHIFT 0
34 #define MME1_RTR_HBW_RD_RQ_W_ARB_E_MASK 0x7
36 #define MME1_RTR_HBW_RD_RQ_W_ARB_S_MASK 0x700
38 #define MME1_RTR_HBW_RD_RQ_W_ARB_N_MASK 0x70000
40 #define MME1_RTR_HBW_RD_RQ_W_ARB_L_MASK 0x7000000
[all …]
H A Dmme_masks.h23 #define MME_ARCH_STATUS_A_SHIFT 0
24 #define MME_ARCH_STATUS_A_MASK 0x1
26 #define MME_ARCH_STATUS_B_MASK 0x2
28 #define MME_ARCH_STATUS_CIN_MASK 0x4
30 #define MME_ARCH_STATUS_COUT_MASK 0x8
32 #define MME_ARCH_STATUS_TE_MASK 0x10
34 #define MME_ARCH_STATUS_LD_MASK 0x20
36 #define MME_ARCH_STATUS_ST_MASK 0x40
38 #define MME_ARCH_STATUS_SB_A_EMPTY_MASK 0x80
40 #define MME_ARCH_STATUS_SB_B_EMPTY_MASK 0x100
[all …]
/linux/arch/mips/lantiq/
H A Dearly_printk.c12 #define LTQ_ASC_FSTAT ((u32 *)(LTQ_EARLY_ASC + 0x0048))
14 #define LTQ_ASC_TBUF ((u32 *)(LTQ_EARLY_ASC + 0x0020 + 3))
16 #define LTQ_ASC_TBUF ((u32 *)(LTQ_EARLY_ASC + 0x0020))
18 #define TXMASK 0x3F00
/linux/drivers/media/pci/cx18/
H A Dcx18-av-firmware.c13 #define CX18_AUDIO_ENABLE 0xc72014
14 #define CX18_AI1_MUX_MASK 0x30
15 #define CX18_AI1_MUX_I2S1 0x00
16 #define CX18_AI1_MUX_I2S2 0x10
17 #define CX18_AI1_MUX_843_I2S 0x20
18 #define CX18_AI1_MUX_INVALID 0x30
25 int ret = 0; in cx18_av_verifyfw()
34 dl_control &= 0x00ffffff; in cx18_av_verifyfw()
35 dl_control |= 0x0f000000; in cx18_av_verifyfw()
38 } while ((dl_control & 0xff000000) != 0x0f000000); in cx18_av_verifyfw()
[all …]
/linux/drivers/accel/habanalabs/include/gaudi2/asic_reg/
H A Ddcore0_tpc0_eml_stm_regs.h23 #define mmDCORE0_TPC0_EML_STM_STMDMASTARTR 0x3C04
25 #define mmDCORE0_TPC0_EML_STM_STMDMASTOPR 0x3C08
27 #define mmDCORE0_TPC0_EML_STM_STMDMASTATR 0x3C0C
29 #define mmDCORE0_TPC0_EML_STM_STMDMACTLR 0x3C10
31 #define mmDCORE0_TPC0_EML_STM_STMDMAIDR 0x3CFC
33 #define mmDCORE0_TPC0_EML_STM_STMHEER 0x3D00
35 #define mmDCORE0_TPC0_EML_STM_STMHETER 0x3D20
37 #define mmDCORE0_TPC0_EML_STM_STMHEBSR 0x3D60
39 #define mmDCORE0_TPC0_EML_STM_STMHEMCR 0x3D64
41 #define mmDCORE0_TPC0_EML_STM_STMHEEXTMUXR 0x3D68
[all …]
H A Ddcore0_mme_ctrl_lo_masks.h24 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_AGU_IN_SHIFT 0
25 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_AGU_IN_MASK 0x1F
27 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_EU_MASK 0x20
29 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_AP_MASK 0x40
31 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_AGU_COUT_MASK 0x180
33 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_SB_IN_EMPTY_MASK 0x3E00
35 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_AGU_COUT_SM_IDLE_MASK 0xC000
37 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_WBC_AXI_IDLE_MASK 0x30000
39 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_SB_IN_AXI_IDLE_MASK 0x7C0000
41 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_ACCUM_FREE_MASK 0x3800000
[all …]
/linux/drivers/mmc/host/
H A Dcb710-mmc.h36 #define CB710_MMC_DATA_PORT 0x00
38 #define CB710_MMC_CONFIG_PORT 0x04
39 #define CB710_MMC_CONFIG0_PORT 0x04
40 #define CB710_MMC_CONFIG1_PORT 0x05
41 #define CB710_MMC_C1_4BIT_DATA_BUS 0x40
42 #define CB710_MMC_CONFIG2_PORT 0x06
43 #define CB710_MMC_C2_READ_PIO_SIZE_MASK 0x0F /* N-1 */
44 #define CB710_MMC_CONFIG3_PORT 0x07
46 #define CB710_MMC_CONFIGB_PORT 0x08
48 #define CB710_MMC_IRQ_ENABLE_PORT 0x0C
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/bif/
H A Dbif_5_1_sh_mask.h27 #define MM_INDEX__MM_OFFSET_MASK 0x7fffffff
28 #define MM_INDEX__MM_OFFSET__SHIFT 0x0
29 #define MM_INDEX__MM_APER_MASK 0x80000000
30 #define MM_INDEX__MM_APER__SHIFT 0x1f
31 #define MM_INDEX_HI__MM_OFFSET_HI_MASK 0xffffffff
32 #define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0
33 #define MM_DATA__MM_DATA_MASK 0xffffffff
34 #define MM_DATA__MM_DATA__SHIFT 0x0
35 #define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK 0x2
36 #define BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT 0x1
[all …]
/linux/drivers/net/ethernet/intel/igbvf/
H A Ddefines.h12 #define E1000_IVAR_VALID 0x80
15 #define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */
16 #define E1000_RXD_STAT_EOP 0x02 /* End of Packet */
17 #define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */
18 #define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */
19 #define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */
20 #define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */
21 #define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */
22 #define E1000_RXD_ERR_SE 0x02 /* Symbol Error */
23 #define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */
[all …]
/linux/drivers/net/wireless/broadcom/b43/
H A Dwa.c24 b43_phy_write(dev, B43_PHY_LNAHPFCTL, 0x1FF9); in b43_wa_initgains()
25 b43_phy_mask(dev, B43_PHY_LPFGAINCTL, 0xFF0F); in b43_wa_initgains()
27 b43_ofdmtab_write16(dev, B43_OFDMTAB_LPFGAIN, 0, 0x1FBF); in b43_wa_initgains()
28 b43_radio_write16(dev, 0x0002, 0x1FBF); in b43_wa_initgains()
30 b43_phy_write(dev, 0x0024, 0x4680); in b43_wa_initgains()
31 b43_phy_write(dev, 0x0020, 0x0003); in b43_wa_initgains()
32 b43_phy_write(dev, 0x001D, 0x0F40); in b43_wa_initgains()
33 b43_phy_write(dev, 0x001F, 0x1C00); in b43_wa_initgains()
35 b43_phy_maskset(dev, 0x002A, 0x00FF, 0x0400); in b43_wa_initgains()
37 b43_phy_maskset(dev, 0x002A, 0x00FF, 0x1A00); in b43_wa_initgains()
[all …]
H A Dphy_ht.h8 #define B43_PHY_HT_BBCFG 0x001 /* BB config */
9 #define B43_PHY_HT_BBCFG_RSTCCA 0x4000 /* Reset CCA */
10 #define B43_PHY_HT_BBCFG_RSTRX 0x8000 /* Reset RX */
11 #define B43_PHY_HT_BANDCTL 0x009 /* Band control */
12 #define B43_PHY_HT_BANDCTL_5GHZ 0x0001 /* Use the 5GHz band */
13 #define B43_PHY_HT_TABLE_ADDR 0x072 /* Table address */
14 #define B43_PHY_HT_TABLE_DATALO 0x073 /* Table data low */
15 #define B43_PHY_HT_TABLE_DATAHI 0x074 /* Table data high */
16 #define B43_PHY_HT_CLASS_CTL 0x0B0 /* Classifier control */
17 #define B43_PHY_HT_CLASS_CTL_CCK_EN 0x0001 /* CCK enable */
[all …]
/linux/arch/mips/sgi-ip22/
H A Dip22-berr.c39 sgimc->cstat = sgimc->gstat = 0; in save_and_clear_buserr()
42 #define GIO_ERRMASK 0xff00
43 #define CPU_ERRMASK 0x3f00
50 printk(KERN_ERR "HPC3 Bus Error 0x%x:<id=0x%x,%s,lane=0x%x>\n", in print_buserr()
59 printk(KERN_ERR "CPU error 0x%x<%s%s%s%s%s%s> @ 0x%08x\n", in print_buserr()
69 printk(KERN_ERR "GIO error 0x%x:<%s%s%s%s%s%s%s%s> @ 0x%08x\n", in print_buserr()
96 printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n", in ip22_be_interrupt()
/linux/drivers/tty/serial/
H A Dlantiq.c34 #define LTQ_ASC_TBUF (0x0020 + 3)
35 #define LTQ_ASC_RBUF (0x0024 + 3)
37 #define LTQ_ASC_TBUF 0x0020
38 #define LTQ_ASC_RBUF 0x0024
40 #define LTQ_ASC_FSTAT 0x0048
41 #define LTQ_ASC_WHBSTATE 0x0018
42 #define LTQ_ASC_STATE 0x0014
43 #define LTQ_ASC_IRNCR 0x00F8
44 #define LTQ_ASC_CLC 0x0000
45 #define LTQ_ASC_ID 0x0008
[all …]
/linux/include/linux/mfd/wm8350/
H A Drtc.h16 #define WM8350_RTC_SECONDS_MINUTES 0x10
17 #define WM8350_RTC_HOURS_DAY 0x11
18 #define WM8350_RTC_DATE_MONTH 0x12
19 #define WM8350_RTC_YEAR 0x13
20 #define WM8350_ALARM_SECONDS_MINUTES 0x14
21 #define WM8350_ALARM_HOURS_DAY 0x15
22 #define WM8350_ALARM_DATE_MONTH 0x16
23 #define WM8350_RTC_TIME_CONTROL 0x17
26 * R16 (0x10) - RTC Seconds/Minutes
28 #define WM8350_RTC_MINS_MASK 0x7F00
[all …]
/linux/sound/soc/samsung/
H A Di2s-regs.h12 #define I2SCON 0x0
13 #define I2SMOD 0x4
14 #define I2SFIC 0x8
15 #define I2SPSR 0xc
16 #define I2STXD 0x10
17 #define I2SRXD 0x14
18 #define I2SFICS 0x18
19 #define I2STXDS 0x1c
20 #define I2SAHB 0x20
21 #define I2SSTR0 0x24
[all …]
/linux/Documentation/devicetree/bindings/soc/fsl/cpm_qe/
H A Dfsl,cpm1-scc-qmc.yaml60 const: 0
63 '^channel@([0-9]|[1-5][0-9]|6[0-3])$':
71 minimum: 0
152 reg = <0xa60 0x20>,
153 <0x3f00 0xc0>,
154 <0x2000 0x1000>;
160 #size-cells = <0>;
169 fsl,tx-ts-mask = <0x00000000 0x000000aa>;
170 fsl,rx-ts-mask = <0x00000000 0x000000aa>;
178 fsl,tx-ts-mask = <0x00000000 0x00000055>;
[all …]
/linux/include/sound/
H A Dcs35l41.h16 #define CS35L41_FIRSTREG 0x00000000
17 #define CS35L41_LASTREG 0x03804FE8
18 #define CS35L41_DEVID 0x00000000
19 #define CS35L41_REVID 0x00000004
20 #define CS35L41_FABID 0x00000008
21 #define CS35L41_RELID 0x0000000C
22 #define CS35L41_OTPID 0x00000010
23 #define CS35L41_SFT_RESET 0x00000020
24 #define CS35L41_TEST_KEY_CTL 0x00000040
25 #define CS35L41_USER_KEY_CTL 0x00000044
[all …]
/linux/include/net/bluetooth/
H A Drfcomm.h43 #define RFCOMM_SABM 0x2f
44 #define RFCOMM_DISC 0x43
45 #define RFCOMM_UA 0x63
46 #define RFCOMM_DM 0x0f
47 #define RFCOMM_UIH 0xef
49 #define RFCOMM_TEST 0x08
50 #define RFCOMM_FCON 0x28
51 #define RFCOMM_FCOFF 0x18
52 #define RFCOMM_MSC 0x38
53 #define RFCOMM_RPN 0x24
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_scl_filters.c31 // <sharpness> = 0
37 0x1000, 0x0000,
38 0x0FF0, 0x0010,
39 0x0FB0, 0x0050,
40 0x0F34, 0x00CC,
41 0x0E68, 0x0198,
42 0x0D44, 0x02BC,
43 0x0BC4, 0x043C,
44 0x09FC, 0x0604,
45 0x0800, 0x0800
[all …]
/linux/drivers/gpu/drm/amd/display/dc/spl/
H A Ddc_spl_scl_filters.c11 // <sharpness> = 0
17 0x1000, 0x0000,
18 0x0FF0, 0x0010,
19 0x0FB0, 0x0050,
20 0x0F34, 0x00CC,
21 0x0E68, 0x0198,
22 0x0D44, 0x02BC,
23 0x0BC4, 0x043C,
24 0x09FC, 0x0604,
25 0x0800, 0x0800
[all …]
/linux/drivers/media/i2c/
H A Dov13858.c17 #define OV13858_REG_MODE_SELECT 0x0100
18 #define OV13858_MODE_STANDBY 0x00
19 #define OV13858_MODE_STREAMING 0x01
21 #define OV13858_REG_SOFTWARE_RST 0x0103
22 #define OV13858_SOFTWARE_RST 0x01
25 #define OV13858_REG_PLL1_CTRL_0 0x0300
26 #define OV13858_REG_PLL1_CTRL_1 0x0301
27 #define OV13858_REG_PLL1_CTRL_2 0x0302
28 #define OV13858_REG_PLL1_CTRL_3 0x0303
29 #define OV13858_REG_PLL1_CTRL_4 0x0304
[all …]
/linux/sound/soc/codecs/
H A Dcs35l36.h16 #define CS35L36_FIRSTREG 0x00000000
17 #define CS35L36_LASTREG 0x00E037FC
18 #define CS35L36_SW_RESET 0x00000000
19 #define CS35L36_SW_REV 0x00000004
20 #define CS35L36_HW_REV 0x00000008
21 #define CS35L36_TESTKEY_CTRL 0x00000020
22 #define CS35L36_USERKEY_CTL 0x00000024
23 #define CS35L36_OTP_MEM30 0x00000478
24 #define CS35L36_OTP_CTRL1 0x00000500
25 #define CS35L36_OTP_CTRL2 0x00000504
[all …]

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