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/linux/arch/s390/kernel/
H A Debcdic.c22 0x00, 0x01, 0x02, 0x03, 0x37, 0x2D, 0x2E, 0x2F,
25 0x16, 0x05, 0x15, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
27 0x10, 0x11, 0x12, 0x13, 0x3C, 0x3D, 0x32, 0x26,
30 0x18, 0x19, 0x3F, 0x27, 0x22, 0x1D, 0x1E, 0x1F,
32 0x40, 0x5A, 0x7F, 0x7B, 0x5B, 0x6C, 0x50, 0x7D,
34 0x4D, 0x5D, 0x5C, 0x4E, 0x6B, 0x60, 0x4B, 0x61,
35 /*30 0 1 2 3 4 5 6 7 */
36 0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7,
38 0xF8, 0xF9, 0x7A, 0x5E, 0x4C, 0x7E, 0x6E, 0x6F,
40 0x7C, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7,
[all …]
/linux/drivers/net/wireless/mediatek/mt76/mt76x0/
H A Dinitvals_phy.h12 { MT_RF(0, 1), 0x01 },
13 { MT_RF(0, 2), 0x11 },
15 { MT_RF(0, 3), 0x73 }, /* VCO Freq Cal */
16 { MT_RF(0, 4), 0x30 }, /* R4 b<7>=1, VCO cal */
17 { MT_RF(0, 5), 0x00 },
18 { MT_RF(0, 6), 0x41 },
19 { MT_RF(0, 7), 0x00 },
20 { MT_RF(0, 8), 0x00 },
21 { MT_RF(0, 9), 0x00 },
22 { MT_RF(0, 10), 0x0C },
[all …]
/linux/drivers/gpu/drm/panel/
H A Dpanel-raydium-rm68200.c21 #define MCS_CMD_MODE_SW 0xFE /* CMD Mode Switch */
22 #define MCS_CMD1_UCS 0x00 /* User Command Set (UCS = CMD1) */
23 #define MCS_CMD2_P0 0x01 /* Manufacture Command Set Page0 (CMD2 P0) */
24 #define MCS_CMD2_P1 0x02 /* Manufacture Command Set Page1 (CMD2 P1) */
25 #define MCS_CMD2_P2 0x03 /* Manufacture Command Set Page2 (CMD2 P2) */
26 #define MCS_CMD2_P3 0x04 /* Manufacture Command Set Page3 (CMD2 P3) */
29 #define MCS_STBCTR 0x12 /* TE1 Output Setting Zig-Zag Connection */
30 #define MCS_SGOPCTR 0x16 /* Source Bias Current */
31 #define MCS_SDCTR 0x1A /* Source Output Delay Time */
32 #define MCS_INVCTR 0x1B /* Inversion Type */
[all …]
/linux/drivers/staging/fbtft/
H A Dfb_s6d1121.c24 #define DEFAULT_GAMMA "26 09 24 2C 1F 23 24 25 22 26 25 23 0D 00\n" \
25 "1C 1A 13 1D 0B 11 12 10 13 15 36 19 00 0D"
33 write_reg(par, 0x0011, 0x2004); in init_display()
34 write_reg(par, 0x0013, 0xCC00); in init_display()
35 write_reg(par, 0x0015, 0x2600); in init_display()
36 write_reg(par, 0x0014, 0x252A); in init_display()
37 write_reg(par, 0x0012, 0x0033); in init_display()
38 write_reg(par, 0x0013, 0xCC04); in init_display()
39 write_reg(par, 0x0013, 0xCC06); in init_display()
40 write_reg(par, 0x0013, 0xCC4F); in init_display()
[all …]
/linux/sound/soc/codecs/
H A Dcs42l73.c54 { 6, 0xF1 }, /* r06 - Power Ctl 1 */
55 { 7, 0xDF }, /* r07 - Power Ctl 2 */
56 { 8, 0x3F }, /* r08 - Power Ctl 3 */
57 { 9, 0x50 }, /* r09 - Charge Pump Freq */
58 { 10, 0x53 }, /* r0A - Output Load MicBias Short Detect */
59 { 11, 0x00 }, /* r0B - DMIC Master Clock Ctl */
60 { 12, 0x00 }, /* r0C - Aux PCM Ctl */
61 { 13, 0x15 }, /* r0D - Aux PCM Master Clock Ctl */
62 { 14, 0x0
[all...]
/linux/drivers/video/fbdev/via/
H A Dhw.c13 {19, 19, 4, 0},
14 {26, 102, 5, 0},
15 {53, 112, 6, 0},
16 {41, 100, 7, 0},
17 {83, 108, 8, 0},
18 {87, 118, 9, 0},
19 {95, 115, 12, 0},
20 {108, 108, 13, 0},
21 {83, 83, 17, 0},
22 {67, 98, 20, 0},
[all …]
/linux/drivers/accel/habanalabs/include/goya/asic_reg/
H A Dmme1_rtr_masks.h23 #define MME1_RTR_HBW_RD_RQ_E_ARB_W_SHIFT 0
24 #define MME1_RTR_HBW_RD_RQ_E_ARB_W_MASK 0x7
26 #define MME1_RTR_HBW_RD_RQ_E_ARB_S_MASK 0x700
28 #define MME1_RTR_HBW_RD_RQ_E_ARB_N_MASK 0x70000
30 #define MME1_RTR_HBW_RD_RQ_E_ARB_L_MASK 0x7000000
33 #define MME1_RTR_HBW_RD_RQ_W_ARB_E_SHIFT 0
34 #define MME1_RTR_HBW_RD_RQ_W_ARB_E_MASK 0x7
36 #define MME1_RTR_HBW_RD_RQ_W_ARB_S_MASK 0x700
38 #define MME1_RTR_HBW_RD_RQ_W_ARB_N_MASK 0x70000
40 #define MME1_RTR_HBW_RD_RQ_W_ARB_L_MASK 0x7000000
[all …]
H A Dpci_nrtr_masks.h23 #define PCI_NRTR_HBW_MAX_CRED_WR_RQ_SHIFT 0
24 #define PCI_NRTR_HBW_MAX_CRED_WR_RQ_MASK 0x3F
26 #define PCI_NRTR_HBW_MAX_CRED_WR_RS_MASK 0x3F00
28 #define PCI_NRTR_HBW_MAX_CRED_RD_RQ_MASK 0x3F0000
30 #define PCI_NRTR_HBW_MAX_CRED_RD_RS_MASK 0x3F000000
33 #define PCI_NRTR_LBW_MAX_CRED_WR_RQ_SHIFT 0
34 #define PCI_NRTR_LBW_MAX_CRED_WR_RQ_MASK 0x3F
36 #define PCI_NRTR_LBW_MAX_CRED_WR_RS_MASK 0x3F00
38 #define PCI_NRTR_LBW_MAX_CRED_RD_RQ_MASK 0x3F0000
40 #define PCI_NRTR_LBW_MAX_CRED_RD_RS_MASK 0x3F000000
[all …]
H A Dtpc0_nrtr_masks.h23 #define TPC0_NRTR_HBW_MAX_CRED_WR_RQ_SHIFT 0
24 #define TPC0_NRTR_HBW_MAX_CRED_WR_RQ_MASK 0x3F
26 #define TPC0_NRTR_HBW_MAX_CRED_WR_RS_MASK 0x3F00
28 #define TPC0_NRTR_HBW_MAX_CRED_RD_RQ_MASK 0x3F0000
30 #define TPC0_NRTR_HBW_MAX_CRED_RD_RS_MASK 0x3F000000
33 #define TPC0_NRTR_LBW_MAX_CRED_WR_RQ_SHIFT 0
34 #define TPC0_NRTR_LBW_MAX_CRED_WR_RQ_MASK 0x3F
36 #define TPC0_NRTR_LBW_MAX_CRED_WR_RS_MASK 0x3F00
38 #define TPC0_NRTR_LBW_MAX_CRED_RD_RQ_MASK 0x3F0000
40 #define TPC0_NRTR_LBW_MAX_CRED_RD_RS_MASK 0x3F000000
[all …]
H A Ddma_nrtr_masks.h23 #define DMA_NRTR_HBW_MAX_CRED_WR_RQ_SHIFT 0
24 #define DMA_NRTR_HBW_MAX_CRED_WR_RQ_MASK 0x3F
26 #define DMA_NRTR_HBW_MAX_CRED_WR_RS_MASK 0x3F00
28 #define DMA_NRTR_HBW_MAX_CRED_RD_RQ_MASK 0x3F0000
30 #define DMA_NRTR_HBW_MAX_CRED_RD_RS_MASK 0x3F000000
33 #define DMA_NRTR_LBW_MAX_CRED_WR_RQ_SHIFT 0
34 #define DMA_NRTR_LBW_MAX_CRED_WR_RQ_MASK 0x3F
36 #define DMA_NRTR_LBW_MAX_CRED_WR_RS_MASK 0x3F00
38 #define DMA_NRTR_LBW_MAX_CRED_RD_RQ_MASK 0x3F0000
40 #define DMA_NRTR_LBW_MAX_CRED_RD_RS_MASK 0x3F000000
[all …]
/linux/drivers/gpu/drm/radeon/
H A Dnid.h33 #define CAYMAN_MAX_BACKENDS_MASK 0xFF
34 #define CAYMAN_MAX_BACKENDS_PER_SE_MASK 0xF
36 #define CAYMAN_MAX_SIMDS_MASK 0xFFFF
37 #define CAYMAN_MAX_SIMDS_PER_SE_MASK 0xFFF
39 #define CAYMAN_MAX_PIPES_MASK 0xFF
40 #define CAYMAN_MAX_LDS_NUM 0xFFFF
42 #define CAYMAN_MAX_TCC_MASK 0xFF
44 #define CAYMAN_GB_ADDR_CONFIG_GOLDEN 0x02011003
45 #define ARUBA_GB_ADDR_CONFIG_GOLDEN 0x12010001
47 #define DMIF_ADDR_CONFIG 0xBD4
[all …]
/linux/drivers/net/wireless/broadcom/b43/
H A Dradio_2059.c17 { 0x051, 0x70 }, { 0x05a, 0x03 }, { 0x079, 0x01 }, { 0x082, 0x70 },
18 { 0x083, 0x00 }, { 0x084, 0x70 }, { 0x09a, 0x7f }, { 0x0b6, 0x10 },
19 { 0x188, 0x05 },
61 RADIOREGS(0x48, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x6c,
62 0x09, 0x0f, 0x0a, 0x00, 0x0a, 0x00, 0x61, 0x73,
63 0x00, 0x00, 0x00, 0xd0, 0x00),
64 PHYREGS(0x03c9, 0x03c5, 0x03c1, 0x043a, 0x043f, 0x0443),
68 RADIOREGS(0x4b, 0x16, 0x30, 0x1b, 0x0a, 0x0a, 0x30, 0x71,
69 0x09, 0x0f, 0x0a, 0x00, 0x0a, 0x00, 0x61, 0x73,
70 0x00, 0x00, 0x00, 0xd0, 0x00),
[all …]
/linux/drivers/gpu/drm/i915/display/
H A Di9xx_wm_regs.h9 #define DSPARB(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70030)
10 #define DSPARB_CSTART_MASK (0x7f << 7)
12 #define DSPARB_BSTART_MASK (0x7f)
13 #define DSPARB_BSTART_SHIFT 0
15 #define DSPARB_AEND_SHIFT 0
16 #define DSPARB_SPRITEA_SHIFT_VLV 0
17 #define DSPARB_SPRITEA_MASK_VLV (0xff << 0)
19 #define DSPARB_SPRITEB_MASK_VLV (0xff << 8)
21 #define DSPARB_SPRITEC_MASK_VLV (0xff << 16)
23 #define DSPARB_SPRITED_MASK_VLV (0xff << 24)
[all …]
/linux/include/linux/mfd/da9052/
H A Dreg.h14 #define DA9052_PAGE0_CON_REG 0
176 #define DA9052_PAGE_CONF 0X80
179 #define DA9052_STATUSA_VDATDET 0X80
180 #define DA9052_STATUSA_VBUSSEL 0X40
181 #define DA9052_STATUSA_DCINSEL 0X20
182 #define DA9052_STATUSA_VBUSDET 0X10
183 #define DA9052_STATUSA_DCINDET 0X08
184 #define DA9052_STATUSA_IDGND 0X04
185 #define DA9052_STATUSA_IDFLOAT 0X02
186 #define DA9052_STATUSA_NONKEY 0X01
[all …]
/linux/drivers/video/fbdev/sis/
H A Dinit.h70 static const unsigned short ModeIndex_320x200[] = {0x59, 0x41, 0x00, 0x4f};
71 static const unsigned short ModeIndex_320x240[] = {0x50, 0x56, 0x00, 0x53};
72 static const unsigned short ModeIndex_320x240_FSTN[] = {0x5a, 0x5b, 0x00, 0x00}; /* FSTN */
73 static const unsigned short ModeIndex_400x300[] = {0x51, 0x57, 0x00, 0x54};
74 static const unsigned short ModeIndex_512x384[] = {0x52, 0x58, 0x00, 0x5c};
75 static const unsigned short ModeIndex_640x400[] = {0x2f, 0x5d, 0x00, 0x5e};
76 static const unsigned short ModeIndex_640x480[] = {0x2e, 0x44, 0x00, 0x62};
77 static const unsigned short ModeIndex_720x480[] = {0x31, 0x33, 0x00, 0x35};
78 static const unsigned short ModeIndex_720x576[] = {0x32, 0x34, 0x00, 0x36};
79 static const unsigned short ModeIndex_768x576[] = {0x5f, 0x60, 0x00, 0x61};
[all …]
/linux/drivers/staging/sm750fb/
H A Dddk750_reg.h6 #define DE_STATE1 0x100054
7 #define DE_STATE1_DE_ABORT BIT(0)
9 #define DE_STATE2 0x100058
14 #define SYSTEM_CTRL 0x000000
15 #define SYSTEM_CTRL_DPMS_MASK (0x3 << 30)
16 #define SYSTEM_CTRL_DPMS_VPHP (0x0 << 30)
17 #define SYSTEM_CTRL_DPMS_VPHN (0x1 << 30)
18 #define SYSTEM_CTRL_DPMS_VNHP (0x2 << 30)
19 #define SYSTEM_CTRL_DPMS_VNHN (0x3 << 30)
35 #define SYSTEM_CTRL_PCI_SLAVE_BURST_READ_SIZE_MASK (0x3 << 4)
[all …]
/linux/include/linux/mfd/
H A Dtps6507x.h22 #define TPS6507X_REG_PPATH1 0X01
28 #define TPS6507X_CHG_USB_CURRENT BIT(0)
30 #define TPS6507X_REG_INT 0X02
37 #define TPS6507X_REG_AC_USB_REMOVED BIT(0)
39 #define TPS6507X_REG_CHGCONFIG0 0X03
41 #define TPS6507X_REG_CHGCONFIG1 0X04
46 #define TPS6507X_CON_CTRL1_LDO2_ENABLE BIT(0)
48 #define TPS6507X_REG_CHGCONFIG2 0X05
50 #define TPS6507X_REG_CHGCONFIG3 0X06
52 #define TPS6507X_REG_ADCONFIG 0X07
[all …]
/linux/drivers/media/tuners/
H A De4000_priv.h48 { 72400000, 0x0f, 48 }, /* .......... 3475200000 */
49 { 81200000, 0x0e, 40 }, /* 2896000000 3248000000 */
50 { 108300000, 0x0d, 32 }, /* 2598400000 3465600000 */
51 { 162500000, 0x0c, 24 }, /* 2599200000 3900000000 */
52 { 216600000, 0x0b, 16 }, /* 2600000000 3465600000 */
53 { 325000000, 0x0a, 12 }, /* 2599200000 3900000000 */
54 { 350000000, 0x09, 8 }, /* 2600000000 2800000000 */
55 { 432000000, 0x03, 8 }, /* 2800000000 3456000000 */
56 { 667000000, 0x02, 6 }, /* 2592000000 4002000000 */
57 { 1200000000, 0x01, 4 }, /* 2668000000 4800000000 */
[all …]
/linux/arch/arm/mach-imx/
H A Dcrmregs-imx3.h17 #define MXC_CCM_CCMR 0x00
18 #define MXC_CCM_PDR0 0x04
19 #define MXC_CCM_PDR1 0x08
20 #define MX35_CCM_PDR2 0x0C
21 #define MXC_CCM_RCSR 0x0C
22 #define MX35_CCM_PDR3 0x10
23 #define MXC_CCM_MPCTL 0x10
24 #define MX35_CCM_PDR4 0x14
25 #define MXC_CCM_UPCTL 0x14
26 #define MX35_CCM_RCSR 0x18
[all …]
/linux/Documentation/devicetree/bindings/display/
H A Dsolomon,ssd1307fb.yaml49 default: 0
70 default: 0
96 minimum: 0
223 #size-cells = <0>;
227 reg = <0x3c>;
234 reg = <0x3d>;
240 solomon,lookup-table = /bits/ 8 <0x3f 0x3f 0x3f 0x3f>;
246 #size-cells = <0>;
248 ssd1307_spi: oled@0 {
250 reg = <0x0>;
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/
H A Dcom.fuc35 ld b32 $r8 D[$r13 + 0x0] // GET
36 ld b32 $r9 D[$r13 + 0x4] // PUT
50 st b32 D[$r8 + 0x0] $r14
51 st b32 D[$r8 + 0x4] $r15
55 and $r9 0xf
56 st b32 D[$r13 + 0x4] $r9
69 ld b32 $r8 D[$r13 + 0x0] // GET
70 ld b32 $r9 D[$r13 + 0x4] // PUT
78 ld b32 $r14 D[$r9 + 0x0]
79 ld b32 $r15 D[$r9 + 0x4]
[all …]
/linux/Documentation/admin-guide/
H A Dbtmrvl.rst14 bit 8:0 -- Gap
18 It could be any valid GPIO pin# (e.g. 0-7) or 0xff (SDIO interface
22 wakeup event, or 0xff for special host sleep setting.
26 # Use SDIO interface to wake up the host and set GAP to 0x80:
27 echo 0xff80 > /debug/btmrvl/config/gpiogap
30 # Use GPIO pin #3 to wake up the host and set GAP to 0xff:
31 echo 0x03ff > /debug/btmrvl/config/gpiogap
40 0 -- Disable auto sleep mode
49 echo 0 > /debug/btmrvl/config/psmode
59 0 -- Wake up firmware
[all …]
/linux/drivers/input/joystick/
H A Dgrip.c44 … grip_btn_gpp[] = { BTN_START, BTN_SELECT, BTN_TR2, BTN_Y, 0, BTN_TL2, BTN_A, BTN_B, BTN_X, 0, BTN…
58 static char grip_anx[] = { 0, 0, 3, 5, 5 };
59 static char grip_cen[] = { 0, 0, 2, 2, 4 };
74 data[0] = 0; in grip_gpp_read_packet()
76 i = 0; in grip_gpp_read_packet()
86 data[0] |= (v >> 1) << i++; in grip_gpp_read_packet()
89 } while (i < GRIP_LENGTH_GPP && t > 0); in grip_gpp_read_packet()
95 for (i = 0; i < GRIP_LENGTH_GPP && (data[0] & 0xfe4210) ^ 0x7c0000; i++) in grip_gpp_read_packet()
96 data[0] = data[0] >> 1 | (data[0] & 1) << (GRIP_LENGTH_GPP - 1); in grip_gpp_read_packet()
115 data[0] = data[1] = data[2] = data[3] = 0; in grip_xt_read_packet()
[all …]
/linux/arch/mips/include/asm/octeon/
H A Dcvmx-ciu-defs.h13 (CVMX_ADD_IO_SEG(0x0001070000000000ull + addr##ull) + \
16 #define CVMX_CIU_EN2_PPX_IP4(c) CVMX_CIU_ADDR(0xA400, c, 0x0F, 8)
17 #define CVMX_CIU_EN2_PPX_IP4_W1C(c) CVMX_CIU_ADDR(0xCC00, c, 0x0F, 8)
18 #define CVMX_CIU_EN2_PPX_IP4_W1S(c) CVMX_CIU_ADDR(0xAC00, c, 0x0F, 8)
19 #define CVMX_CIU_FUSE CVMX_CIU_ADDR(0x0728, 0, 0x00, 0)
20 #define CVMX_CIU_INT_SUM1 CVMX_CIU_ADDR(0x0108, 0, 0x00, 0)
21 #define CVMX_CIU_INTX_EN0(c) CVMX_CIU_ADDR(0x0200, c, 0x3F, 16)
22 #define CVMX_CIU_INTX_EN0_W1C(c) CVMX_CIU_ADDR(0x2200, c, 0x3F, 16)
23 #define CVMX_CIU_INTX_EN0_W1S(c) CVMX_CIU_ADDR(0x6200, c, 0x3F, 16)
24 #define CVMX_CIU_INTX_EN1(c) CVMX_CIU_ADDR(0x0208, c, 0x3F, 16)
[all …]
/linux/drivers/usb/misc/sisusbvga/
H A Dsisusb_tables.h58 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
59 0x15, 0x15, 0x15, 0x15, 0x15, 0x15, 0x15, 0x15,
60 0x15, 0x15, 0x15, 0x15, 0x15, 0x15, 0x15, 0x15,
61 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F,
62 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
63 0x15, 0x15, 0x15, 0x15, 0x15, 0x15, 0x15, 0x15,
64 0x15, 0x15, 0x15, 0x15, 0x15, 0x15, 0x15, 0x15,
65 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F
69 0x00, 0x10, 0x04, 0x14, 0x01, 0x11, 0x09, 0x15,
70 0x00, 0x10, 0x04, 0x14, 0x01, 0x11, 0x09, 0x15,
[all …]

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