/linux/drivers/accel/habanalabs/include/gaudi2/asic_reg/ |
H A D | dcore0_tpc0_eml_stm_regs.h | 23 #define mmDCORE0_TPC0_EML_STM_STMDMASTARTR 0x3C04 25 #define mmDCORE0_TPC0_EML_STM_STMDMASTOPR 0x3C08 27 #define mmDCORE0_TPC0_EML_STM_STMDMASTATR 0x3C0C 29 #define mmDCORE0_TPC0_EML_STM_STMDMACTLR 0x3C10 31 #define mmDCORE0_TPC0_EML_STM_STMDMAIDR 0x3CFC 33 #define mmDCORE0_TPC0_EML_STM_STMHEER 0x3D00 35 #define mmDCORE0_TPC0_EML_STM_STMHETER 0x3D20 37 #define mmDCORE0_TPC0_EML_STM_STMHEBSR 0x3D60 39 #define mmDCORE0_TPC0_EML_STM_STMHEMCR 0x3D64 41 #define mmDCORE0_TPC0_EML_STM_STMHEEXTMUXR 0x3D68 [all …]
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/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/ |
H A D | uvd_3_1_d.h | 27 #define mmUVD_SEMA_ADDR_LOW 0x3bc0 28 #define mmUVD_SEMA_ADDR_HIGH 0x3bc1 29 #define mmUVD_SEMA_CMD 0x3bc2 30 #define mmUVD_GPCOM_VCPU_CMD 0x3bc3 31 #define mmUVD_GPCOM_VCPU_DATA0 0x3bc4 32 #define mmUVD_GPCOM_VCPU_DATA1 0x3bc5 33 #define mmUVD_ENGINE_CNTL 0x3bc6 34 #define mmUVD_UDEC_ADDR_CONFIG 0x3bd3 35 #define mmUVD_UDEC_DB_ADDR_CONFIG 0x3bd4 36 #define mmUVD_UDEC_DBW_ADDR_CONFIG 0x3bd5 [all …]
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H A D | uvd_4_0_d.h | 26 #define ixUVD_CGC_CTRL2 0x00C1 27 #define ixUVD_CGC_MEM_CTRL 0x00C0 28 #define ixUVD_LMI_ADDR_EXT2 0x00AB 29 #define ixUVD_LMI_CACHE_CTRL 0x009B 30 #define ixUVD_LMI_SWAP_CNTL2 0x00AA 31 #define ixUVD_MIF_CURR_ADDR_CONFIG 0x0048 32 #define ixUVD_MIF_RECON1_ADDR_CONFIG 0x0114 33 #define ixUVD_MIF_REF_ADDR_CONFIG 0x004C 34 #define mmUVD_CGC_CTRL 0x3D2C 35 #define mmUVD_CGC_GATE 0x3D2A [all …]
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H A D | uvd_4_2_d.h | 27 #define mmUVD_SEMA_ADDR_LOW 0x3bc0 28 #define mmUVD_SEMA_ADDR_HIGH 0x3bc1 29 #define mmUVD_SEMA_CMD 0x3bc2 30 #define mmUVD_GPCOM_VCPU_CMD 0x3bc3 31 #define mmUVD_GPCOM_VCPU_DATA0 0x3bc4 32 #define mmUVD_GPCOM_VCPU_DATA1 0x3bc5 33 #define mmUVD_ENGINE_CNTL 0x3bc6 34 #define mmUVD_UDEC_ADDR_CONFIG 0x3bd3 35 #define mmUVD_UDEC_DB_ADDR_CONFIG 0x3bd4 36 #define mmUVD_UDEC_DBW_ADDR_CONFIG 0x3bd5 [all …]
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H A D | uvd_5_0_d.h | 27 #define mmUVD_SEMA_ADDR_LOW 0x3bc0 28 #define mmUVD_SEMA_ADDR_HIGH 0x3bc1 29 #define mmUVD_SEMA_CMD 0x3bc2 30 #define mmUVD_GPCOM_VCPU_CMD 0x3bc3 31 #define mmUVD_GPCOM_VCPU_DATA0 0x3bc4 32 #define mmUVD_GPCOM_VCPU_DATA1 0x3bc5 33 #define mmUVD_ENGINE_CNTL 0x3bc6 34 #define mmUVD_UDEC_ADDR_CONFIG 0x3bd3 35 #define mmUVD_UDEC_DB_ADDR_CONFIG 0x3bd4 36 #define mmUVD_UDEC_DBW_ADDR_CONFIG 0x3bd5 [all …]
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H A D | uvd_6_0_d.h | 27 #define mmUVD_SEMA_ADDR_LOW 0x3bc0 28 #define mmUVD_SEMA_ADDR_HIGH 0x3bc1 29 #define mmUVD_SEMA_CMD 0x3bc2 30 #define mmUVD_GPCOM_VCPU_CMD 0x3bc3 31 #define mmUVD_GPCOM_VCPU_DATA0 0x3bc4 32 #define mmUVD_GPCOM_VCPU_DATA1 0x3bc5 33 #define mmUVD_ENGINE_CNTL 0x3bc6 34 #define mmUVD_UDEC_ADDR_CONFIG 0x3bd3 35 #define mmUVD_UDEC_DB_ADDR_CONFIG 0x3bd4 36 #define mmUVD_UDEC_DBW_ADDR_CONFIG 0x3bd5 [all …]
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/linux/Documentation/devicetree/bindings/i2c/ |
H A D | i2c-mpc.yaml | 69 #size-cells = <0>; 71 reg = <0x1740 0x20>; 72 interrupts = <11 0x8>; 81 #size-cells = <0>; 83 reg = <0x3d00 0x40>; 84 interrupts = <2 15 0>; 93 #size-cells = <0>; 95 reg = <0x3100 0x100>;
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/linux/Documentation/devicetree/bindings/phy/ |
H A D | mediatek,xsphy.yaml | 20 u2 port0 0x0000 MISC 21 0x0100 FMREG 22 0x0300 U2PHY_COM 23 u2 port1 0x1000 MISC 24 0x1100 FMREG 25 0x1300 U2PHY_COM 26 u2 port2 0x2000 MISC 28 u31 common 0x3000 DIG_GLB 29 0x3100 PHYA_GLB 30 u31 port0 0x3400 DIG_LN_TOP [all …]
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/linux/arch/powerpc/boot/dts/ |
H A D | ep88xc.dts | 19 #size-cells = <0>; 21 PowerPC,885@0 { 23 reg = <0x0>; 28 timebase-frequency = <0>; 29 bus-frequency = <0>; 30 clock-frequency = <0>; 38 reg = <0x0 0x0>; 45 reg = <0xfa200100 0x40>; 48 0x0 0x0 0xfc000000 0x4000000 49 0x3 0x0 0xfa000000 0x1000000 [all …]
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H A D | charon.dts | 23 #size-cells = <0>; 25 PowerPC,5200@0 { 27 reg = <0>; 30 d-cache-size = <0x4000>; // L1, 16K 31 i-cache-size = <0x4000>; // L1, 16K 32 timebase-frequency = <0>; // from bootloader 33 bus-frequency = <0>; // from bootloader 34 clock-frequency = <0>; // from bootloader 38 memory@0 { 40 reg = <0x00000000 0x08000000>; // 128MB [all …]
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H A D | lite5200.dts | 20 #size-cells = <0>; 22 PowerPC,5200@0 { 24 reg = <0>; 27 d-cache-size = <0x4000>; // L1, 16K 28 i-cache-size = <0x4000>; // L1, 16K 29 timebase-frequency = <0>; // from bootloader 30 bus-frequency = <0>; // from bootloader 31 clock-frequency = <0>; // from bootloader 35 memory@0 { 37 reg = <0x00000000 0x04000000>; // 64MB [all …]
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H A D | mpc5200b.dtsi | 21 #size-cells = <0>; 23 powerpc: PowerPC,5200@0 { 25 reg = <0>; 28 d-cache-size = <0x4000>; // L1, 16K 29 i-cache-size = <0x4000>; // L1, 16K 30 timebase-frequency = <0>; // from bootloader 31 bus-frequency = <0>; // from bootloader 32 clock-frequency = <0>; // from bootloader 36 memory: memory@0 { 38 reg = <0x00000000 0x04000000>; // 64MB [all …]
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/linux/drivers/gpu/drm/mgag200/ |
H A D | mgag200_reg.h | 24 #define MGAREG_DWGCTL 0x1c00 25 #define MGAREG_MACCESS 0x1c04 27 #define MGAREG_MCTLWTST 0x1c08 28 #define MGAREG_ZORG 0x1c0c 30 #define MGAREG_PAT0 0x1c10 31 #define MGAREG_PAT1 0x1c14 32 #define MGAREG_PLNWT 0x1c1c 34 #define MGAREG_BCOL 0x1c20 35 #define MGAREG_FCOL 0x1c24 37 #define MGAREG_SRC0 0x1c30 [all …]
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/linux/drivers/net/ethernet/amd/ |
H A D | ariadne.h | 17 * Publication #16907, Rev. B, Amendment/0, May 1994 62 #define CSR0 0x0000 /* - PCnet-ISA Controller Status */ 63 #define CSR1 0x0100 /* - IADR[15:0] */ 64 #define CSR2 0x0200 /* - IADR[23:16] */ 65 #define CSR3 0x0300 /* - Interrupt Masks and Deferral Control */ 66 #define CSR4 0x0400 /* - Test and Features Control */ 67 #define CSR6 0x0600 /* RCV/XMT Descriptor Table Length */ 68 #define CSR8 0x0800 /* - Logical Address Filter, LADRF[15:0] */ 69 #define CSR9 0x0900 /* - Logical Address Filter, LADRF[31:16] */ 70 #define CSR10 0x0a00 /* - Logical Address Filter, LADRF[47:32] */ [all …]
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/linux/drivers/media/dvb-frontends/ |
H A D | s5h1411.c | 42 } while (0) 50 { S5H1411_I2C_TOP_ADDR, 0x00, 0x0071, }, 51 { S5H1411_I2C_TOP_ADDR, 0x08, 0x0047, }, 52 { S5H1411_I2C_TOP_ADDR, 0x1c, 0x0400, }, 53 { S5H1411_I2C_TOP_ADDR, 0x1e, 0x0370, }, 54 { S5H1411_I2C_TOP_ADDR, 0x1f, 0x342c, }, 55 { S5H1411_I2C_TOP_ADDR, 0x24, 0x0231, }, 56 { S5H1411_I2C_TOP_ADDR, 0x25, 0x1011, }, 57 { S5H1411_I2C_TOP_ADDR, 0x26, 0x0f07, }, 58 { S5H1411_I2C_TOP_ADDR, 0x27, 0x0f04, }, [all …]
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/linux/drivers/media/platform/renesas/vsp1/ |
H A D | vsp1_regs.h | 17 #define VI6_CMD(n) (0x0000 + (n) * 4) 19 #define VI6_CMD_STRCMD BIT(0) 21 #define VI6_CLK_DCSWT 0x0018 22 #define VI6_CLK_DCSWT_CSTPW_MASK (0xff << 8) 24 #define VI6_CLK_DCSWT_CSTRW_MASK (0xff << 0) 25 #define VI6_CLK_DCSWT_CSTRW_SHIFT 0 27 #define VI6_SRESET 0x0028 30 #define VI6_STATUS 0x0038 34 #define VI6_WPF_IRQ_ENB(n) (0x0048 + (n) * 12) 37 #define VI6_WPF_IRQ_ENB_FREE BIT(0) [all …]
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/linux/drivers/scsi/ |
H A D | sense_codes.h | 7 SENSE_CODE(0x0000, "No additional sense information") 8 SENSE_CODE(0x0001, "Filemark detected") 9 SENSE_CODE(0x0002, "End-of-partition/medium detected") 10 SENSE_CODE(0x0003, "Setmark detected") 11 SENSE_CODE(0x0004, "Beginning-of-partition/medium detected") 12 SENSE_CODE(0x0005, "End-of-data detected") 13 SENSE_CODE(0x0006, "I/O process terminated") 14 SENSE_CODE(0x0007, "Programmable early warning detected") 15 SENSE_CODE(0x0011, "Audio play operation in progress") 16 SENSE_CODE(0x0012, "Audio play operation paused") [all …]
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/linux/drivers/media/i2c/ |
H A D | ar0521.c | 31 #define AR0521_MIN_X_ADDR_START 0u 32 #define AR0521_MIN_Y_ADDR_START 0u 46 #define AR0521_ANA_GAIN_MIN 0x00 47 #define AR0521_ANA_GAIN_MAX 0x3f 48 #define AR0521_ANA_GAIN_STEP 0x01 49 #define AR0521_ANA_GAIN_DEFAULT 0x00 52 #define AR0521_REG_VT_PIX_CLK_DIV 0x0300 53 #define AR0521_REG_FRAME_LENGTH_LINES 0x0340 55 #define AR0521_REG_CHIP_ID 0x3000 56 #define AR0521_REG_COARSE_INTEGRATION_TIME 0x3012 [all …]
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H A D | ov5648.c | 30 #define OV5648_SW_STANDBY_REG 0x100 31 #define OV5648_SW_STANDBY_STREAM_ON BIT(0) 33 #define OV5648_SW_RESET_REG 0x103 34 #define OV5648_SW_RESET_RESET BIT(0) 36 #define OV5648_PAD_OEN0_REG 0x3000 37 #define OV5648_PAD_OEN1_REG 0x3001 38 #define OV5648_PAD_OEN2_REG 0x3002 39 #define OV5648_PAD_OUT0_REG 0x3008 40 #define OV5648_PAD_OUT1_REG 0x3009 42 #define OV5648_CHIP_ID_H_REG 0x300a [all …]
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/linux/drivers/clk/qcom/ |
H A D | gcc-ipq806x.c | 33 .l_reg = 0x30c4, 34 .m_reg = 0x30c8, 35 .n_reg = 0x30cc, 36 .config_reg = 0x30d4, 37 .mode_reg = 0x30c0, 38 .status_reg = 0x30d8, 49 .enable_reg = 0x34c0, 50 .enable_mask = BIT(0), 62 .l_reg = 0x3164, 63 .m_reg = 0x3168, [all …]
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/linux/drivers/gpu/drm/meson/ |
H A D | meson_registers.h | 18 #define VPP2_DUMMY_DATA 0x1900 19 #define VPP2_LINE_IN_LENGTH 0x1901 20 #define VPP2_PIC_IN_HEIGHT 0x1902 21 #define VPP2_SCALE_COEF_IDX 0x1903 22 #define VPP2_SCALE_COEF 0x1904 23 #define VPP2_VSC_REGION12_STARTP 0x1905 24 #define VPP2_VSC_REGION34_STARTP 0x1906 25 #define VPP2_VSC_REGION4_ENDP 0x1907 26 #define VPP2_VSC_START_PHASE_STEP 0x1908 27 #define VPP2_VSC_REGION0_PHASE_SLOPE 0x1909 [all …]
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/linux/drivers/net/wireless/realtek/rtlwifi/rtl8192ee/ |
H A D | hw.c | 42 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64); in _rtl92ee_stop_tx_beacon() 44 tmp &= ~(BIT(0)); in _rtl92ee_stop_tx_beacon() 55 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); in _rtl92ee_resume_tx_beacon() 57 tmp |= BIT(0); in _rtl92ee_resume_tx_beacon() 63 _rtl92ee_set_bcn_ctrl_reg(hw, 0, BIT(1)); in _rtl92ee_enable_bcn_sub_func() 68 _rtl92ee_set_bcn_ctrl_reg(hw, BIT(1), 0); in _rtl92ee_disable_bcn_sub_func() 77 u32 count = 0, isr_regaddr, content; in _rtl92ee_set_fw_clock_on() 120 rtl_write_word(rtlpriv, isr_regaddr, 0x0100); in _rtl92ee_set_fw_clock_on() 163 for (queue = 0; queue < RTL_PCI_MAX_TX_QUEUE_COUNT; queue++) { in _rtl92ee_set_fw_clock_off() 183 rtl_write_word(rtlpriv, REG_HISR, 0x0100); in _rtl92ee_set_fw_clock_off() [all …]
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/linux/drivers/net/usb/ |
H A D | lan78xx.c | 50 #define FLOW_THRESHOLD(n) ((((n) + 511) / 512) & 0x7F) 51 #define FLOW_CTRL_THRESHOLD(on, off) ((FLOW_THRESHOLD(on) << 0) | \ 63 #define DEFAULT_BULK_IN_DELAY (0x0800) 73 #define LAN78XX_USB_VENDOR_ID (0x0424) 74 #define LAN7800_USB_PRODUCT_ID (0x7800) 75 #define LAN7850_USB_PRODUCT_ID (0x7850) 76 #define LAN7801_USB_PRODUCT_ID (0x7801) 77 #define LAN78XX_EEPROM_MAGIC (0x78A5) 78 #define LAN78XX_OTP_MAGIC (0x78F3) 79 #define AT29M2AF_USB_VENDOR_ID (0x07C9) [all …]
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/linux/drivers/gpu/drm/amd/include/asic_reg/gc/ |
H A D | gc_9_4_2_offset.h | 29 // base address: 0x0 30 …DIDT_SQ_CTRL0 0x0000 31 …DIDT_SQ_CTRL2 0x0002 32 …DIDT_SQ_STALL_CTRL 0x0004 33 …DIDT_SQ_TUNING_CTRL 0x0005 34 …DIDT_SQ_STALL_AUTO_RELEASE_CTRL 0x0006 35 …DIDT_SQ_CTRL3 0x0007 36 …DIDT_SQ_STALL_PATTERN_1_2 0x0008 37 …DIDT_SQ_STALL_PATTERN_3_4 0x0009 38 …DIDT_SQ_STALL_PATTERN_5_6 0x000a [all …]
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H A D | gc_9_1_offset.h | 24 …SQ_DEBUG_STS_GLOBAL 0x0309 25 …ne mmSQ_DEBUG_STS_GLOBAL_BASE_IDX 0 26 …SQ_DEBUG_STS_GLOBAL2 0x0310 27 …ne mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX 0 28 …SQ_DEBUG_STS_GLOBAL3 0x0311 29 …ne mmSQ_DEBUG_STS_GLOBAL3_BASE_IDX 0 32 // base address: 0x8000 33 …GRBM_CNTL 0x0000 34 …ne mmGRBM_CNTL_BASE_IDX 0 35 …GRBM_SKEW_CNTL 0x0001 [all …]
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