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/freebsd/stand/i386/libi386/
H A Dbiosmem.c47 #define B_BASEMEM_E820 0x1
48 #define B_BASEMEM_12 0x2
49 #define B_EXTMEM_E820 0x4
50 #define B_EXTMEM_E801 0x8
51 #define B_EXTMEM_8800 0x10
64 #define BQ_DISTRUST_E820_EXTMEM 0x1
75 {NULL, NULL, NULL, 0}
83 for (i = 0; quirks[i].quirk != 0; ++i) { in bios_getquirks()
89 return (0); in bios_getquirks()
98 v86.ebx = 0; in bios_getmem()
[all …]
/freebsd/sys/contrib/device-tree/src/loongarch/
H A Dloongson-2k0500.dtsi17 #size-cells = <0>;
19 cpu0: cpu@0 {
22 reg = <0x0>;
29 #clock-cells = <0>;
44 thermal-sensors = <&tsensor 0>;
64 ranges = <0x0 0x10000000 0x0 0x10000000 0x0 0x10000000>,
65 <0x0 0x02000000 0x0 0x02000000 0x0 0x02000000>,
66 <0x0 0x20000000 0x0 0x20000000 0x0 0x10000000>,
67 <0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>,
68 <0xfe 0x0 0xfe 0x0 0x0 0x40000000>;
[all …]
H A Dloongson-2k2000.dtsi17 #size-cells = <0>;
22 reg = <0x0>;
29 reg = <0x1>;
36 #clock-cells = <0>;
51 thermal-sensors = <&tsensor 0>;
71 ranges = <0x0 0x10000000 0x0 0x10000000 0x0 0x10000000>,
72 <0x0 0x02000000 0x0 0x02000000 0x0 0x02000000>,
73 <0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>,
74 <0xfe 0x0 0xfe 0x0 0x0 0x40000000>;
82 ranges = <1 0x0 0x0 0x18400000 0x4000>;
[all …]
H A Dloongson-2k1000.dtsi18 #size-cells = <0>;
20 cpu0: cpu@0 {
23 reg= <0x0>;
30 reg = <0x1>;
37 #clock-cells = <0>;
49 i2c-gpio-0 {
51 scl-gpios = <&gpio0 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
55 #size-cells = <0>;
66 #size-cells = <0>;
74 thermal-sensors = <&tsensor 0>;
[all …]
/freebsd/sys/dev/rtwn/rtl8812a/
H A Dr12a_rx_desc.h34 #define R12A_RXDW1_AMSDU 0x00002000
35 #define R12A_RXDW1_AMPDU 0x00008000
36 #define R12A_RXDW1_CKSUM_ERR 0x00100000
37 #define R12A_RXDW1_IPV6 0x00200000
38 #define R12A_RXDW1_UDP 0x00400000
39 #define R12A_RXDW1_CKSUM 0x00800000
41 #define R12A_RXDW2_RPT_C2H 0x10000000
43 #define R12A_RXDW3_RATE_M 0x0000007f
44 #define R12A_RXDW3_RATE_S 0
46 #define R12A_RXDW4_SPLCP 0x00000001
[all …]
/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dphy-mtk-xsphy.txt59 u2 port0 0x0000 MISC
60 0x0100 FMREG
61 0x0300 U2PHY_COM
62 u2 port1 0x1000 MISC
63 0x1100 FMREG
64 0x1300 U2PHY_COM
65 u2 port2 0x2000 MISC
67 u31 common 0x3000 DIG_GLB
68 0x3100 PHYA_GLB
69 u31 port0 0x3400 DIG_LN_TOP
[all …]
H A Dmediatek,xsphy.yaml20 u2 port0 0x0000 MISC
21 0x0100 FMREG
22 0x0300 U2PHY_COM
23 u2 port1 0x1000 MISC
24 0x1100 FMREG
25 0x1300 U2PHY_COM
26 u2 port2 0x2000 MISC
28 u31 common 0x3000 DIG_GLB
29 0x3100 PHYA_GLB
30 u31 port0 0x3400 DIG_LN_TOP
[all …]
/freebsd/sys/libkern/
H A Dcrc16.c32 /* CRC table for the CRC-16. The poly is 0x8005 (x16 + x15 + x2 + 1). */
34 0x0000, 0xC0C1, 0xC181, 0x0140, 0xC301, 0x03C0, 0x0280, 0xC241,
35 0xC601, 0x06C0, 0x0780, 0xC741, 0x0500, 0xC5C1, 0xC481, 0x0440,
36 0xCC01, 0x0CC0, 0x0D80, 0xCD41, 0x0F00, 0xCFC1, 0xCE81, 0x0E40,
37 0x0A00, 0xCAC1, 0xCB81, 0x0B40, 0xC901, 0x09C0, 0x0880, 0xC841,
38 0xD801, 0x18C0, 0x1980, 0xD941, 0x1B00, 0xDBC1, 0xDA81, 0x1A40,
39 0x1E00, 0xDEC1, 0xDF81, 0x1F40, 0xDD01, 0x1DC0, 0x1C80, 0xDC41,
40 0x1400, 0xD4C1, 0xD581, 0x1540, 0xD701, 0x17C0, 0x1680, 0xD641,
41 0xD201, 0x12C0, 0x1380, 0xD341, 0x1100, 0xD1C1, 0xD081, 0x1040,
42 0xF001, 0x30C0, 0x3180, 0xF141, 0x3300, 0xF3C1, 0xF281, 0x3240,
[all …]
/freebsd/tools/diag/dumpvfscache/
H A Ddumpvfscache.c16 0x0000, 0xCC01, 0xD801, 0x1400,
17 0xF001, 0x3C00, 0x2800, 0xE401,
18 0xA001, 0x6C00, 0x7800, 0xB401,
19 0x5000, 0x9C01, 0x8801, 0x4400
31 char nc_name[0];
37 u_short crc = 0; in wlpsacrc()
40 for (i = 0; i < len; i++, buf++) { in wlpsacrc()
42 r1 = crc16_table[crc & 0xF]; in wlpsacrc()
43 crc = (crc >> 4) & 0x0FFF; in wlpsacrc()
44 crc = crc ^ r1 ^ crc16_table[*buf & 0xF]; in wlpsacrc()
[all …]
/freebsd/contrib/arm-optimized-routines/math/aarch64/experimental/
H A Dlog1p_2u.c13 #define Ln2Hi 0x1.62e42fefa3800p-1
14 #define Ln2Lo 0x1.ef35793c76730p-45
15 #define HfRt2Top 0x3fe6a09e /* top32(asuint64(sqrt(2)/2)). */
17 0x00095f62 /* top32(asuint64(1)) - top32(asuint64(sqrt(2)/2)). */
18 #define OneTop12 0x3ff
19 #define BottomMask 0xffffffff
20 #define OneMHfRt2 0x3fd2bec333018866
21 #define Rt2MOne 0x3fda827999fcef32
22 #define AbsMask 0x7fffffffffffffff
23 #define ExpM63 0x3c00
[all …]
/freebsd/sys/contrib/device-tree/src/powerpc/
H A Dmpc866ads.dts19 #size-cells = <0>;
21 PowerPC,866@0 {
23 reg = <0x0>;
26 d-cache-size = <0x2000>; // L1, 8K
27 i-cache-size = <0x4000>; // L1, 16K
28 timebase-frequency = <0>;
29 bus-frequency = <0>;
30 clock-frequency = <0>;
38 reg = <0x0 0x800000>;
45 reg = <0xff000100 0x40>;
[all …]
H A Dtqm8xx.dts26 #size-cells = <0>;
28 PowerPC,860@0 {
30 reg = <0x0>;
33 d-cache-size = <0x1000>; // L1, 4K
34 i-cache-size = <0x1000>; // L1, 4K
35 timebase-frequency = <0>;
36 bus-frequency = <0>;
37 clock-frequency = <0>;
45 reg = <0x0 0x2000000>;
52 reg = <0xfff00100 0x40>;
[all …]
H A Dmpc5200b.dtsi21 #size-cells = <0>;
23 powerpc: PowerPC,5200@0 {
25 reg = <0>;
28 d-cache-size = <0x4000>; // L1, 16K
29 i-cache-size = <0x4000>; // L1, 16K
30 timebase-frequency = <0>; // from bootloader
31 bus-frequency = <0>; // from bootloader
32 clock-frequency = <0>; // from bootloader
36 memory: memory@0 {
38 reg = <0x00000000 0x04000000>; // 64MB
[all …]
/freebsd/sys/dev/bnxt/bnxt_re/
H A Dib_verbs.h41 #define BNXT_RE_ROCE_V2_UDP_SPORT 0x8CD1
42 #define BNXT_RE_QP_RANDOM_QKEY 0x81818181
97 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_256MB 0x1cUL
488 return 0; in bnxt_re_init_pow2_flag()
508 return 0; in bnxt_re_init_rsvd_wqe_flag()
516 return _is_chip_gen_p5_p7(cctx) ? 0 : BNXT_QPLIB_RESERVED_QP_WRS; in bnxt_re_get_diff()
518 return 0; in bnxt_re_get_diff()
559 return (*(u16 *)a ^ *(u16 *)b) | (a32[0] ^ b32[0]) | in compare_ether_header()
572 /* CRC table for the CRC-16. The poly is 0x8005 (x16 + x15 + x2 + 1). */ in crc16()
574 0x0000, 0xC0C1, 0xC181, 0x0140, 0xC301, 0x03C0, 0x0280, 0xC241, in crc16()
[all …]
/freebsd/sys/net/
H A Dethernet.h37 ((hasfcs) ? ETHER_CRC_LEN : 0) + \
38 (((etype) == ETHERTYPE_VLAN) ? ETHER_VLAN_ENCAP_LEN : 0))
48 #define ETHER_CRC_POLY_LE 0xedb88320
49 #define ETHER_CRC_POLY_BE 0x04c11db6
73 #define ETHER_IS_MULTICAST(addr) (*(addr) & 0x01) /* is address mcast/bcast? */
75 (((addr)[0] == 0x33) && ((addr)[1] == 0x33))
77 (((addr)[0] & (addr)[1] & (addr)[2] & \
78 (addr)[3] & (addr)[4] & (addr)[5]) == 0xf
[all...]
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DAMDGPUMCCodeEmitter.cpp3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
107 // immediate value, or 0 if it is not.
110 if (Imm >= 0 && Imm <= 64) in getIntInlineImmEncoding()
116 return 0; in getIntInlineImmEncoding()
121 if (IntImm != 0) in getLit16Encoding()
124 if (Val == 0x3800) // 0.5 in getLit16Encoding()
127 if (Val == 0xB800) // -0.5 in getLit16Encoding()
130 if (Val == 0x3C00) // 1.0 in getLit16Encoding()
133 if (Val == 0xBC00) // -1.0 in getLit16Encoding()
136 if (Val == 0x4000) // 2.0 in getLit16Encoding()
[all …]
H A DAMDGPUInstPrinter.cpp3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
53 O << formatHex(MI->getOperand(OpNo).getImm() & 0xf); in printU4ImmOperand()
69 O << formatHex(static_cast<uint64_t>(Imm & 0xffff)); in printU16ImmOperand()
76 O << formatDec(MI->getOperand(OpNo).getImm() & 0xf); in printU4ImmDecOperand()
81 O << formatDec(MI->getOperand(OpNo).getImm() & 0xff); in printU8ImmDecOperand()
86 O << formatDec(MI->getOperand(OpNo).getImm() & 0xffff); in printU16ImmDecOperand()
92 O << formatHex(MI->getOperand(OpNo).getImm() & 0xffffffff); in printU32ImmOperand()
106 if (Imm != 0) { in printOffset()
123 if (Imm != 0) { in printFlatOffset()
211 // For th = 0 do not print this field in printTH()
[all …]
/freebsd/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dar9300_misc.c37 *hangs = 0; in ar9300_get_hw_hangs()
39 if (ar9300_get_capability(ah, HAL_CAP_BB_RIFS_HANG, 0, AH_NULL) == HAL_OK) { in ar9300_get_hw_hangs()
42 if (ar9300_get_capability(ah, HAL_CAP_BB_DFS_HANG, 0, AH_NULL) == HAL_OK) { in ar9300_get_hw_hangs()
45 if (ar9300_get_capability(ah, HAL_CAP_BB_RX_CLEAR_STUCK_HANG, 0, AH_NULL) in ar9300_get_hw_hangs()
50 if (ar9300_get_capability(ah, HAL_CAP_MAC_HANG, 0, AH_NULL) == HAL_OK) { in ar9300_get_hw_hangs()
53 if (ar9300_get_capability(ah, HAL_CAP_PHYRESTART_CLR_WAR, 0, AH_NULL) in ar9300_get_hw_hangs()
69 #if 0 in ar9300_mac_to_usec()
84 #if 0 in ar9300_mac_to_clks()
145 if (AH_PRIVATE(ah)->ah_currentRD == 0) { in ar9300_set_regulatory_domain()
151 #if 0 in ar9300_set_regulatory_domain()
[all …]
H A Dar9300phy.h55 #define AR_PHY_TIMING11_SPUR_FREQ_SD 0x3FF00000
58 #define AR_PHY_TIMING11_SPUR_DELTA_PHASE 0x000FFFFF
59 #define AR_PHY_TIMING11_SPUR_DELTA_PHASE_S 0
61 #define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC 0x40000000
64 #define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR 0x80000000
68 #define AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT 0x4000000
71 #define AR_PHY_SPUR_REG_ENABLE_MASK_PPM 0x20000 /* bins move with freq offset */
73 #define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH 0x000000FF
74 #define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_S 0
75 #define AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI 0x00000100
[all …]
/freebsd/sys/dev/neta/
H A Dif_mvnetareg.h39 #define MVNETA_SIZE 0x4000
53 #if MVNETA_TX_QNUM_MAX & (MVNETA_TX_QNUM_MAX - 1) != 0
56 #if MVNETA_RX_QNUM_MAX & (MVNETA_RX_QNUM_MAX - 1) != 0
61 #define MVNETA_QUEUE_ALL 0xff
67 * GbE0 BASE 0x00007.0000 SIZE 0x4000
68 * GbE1 BASE 0x00007.4000 SIZE 0x4000
73 #define MVNETA_BASEADDR(n) (0x2200 + ((n) << 3)) /* Base Address */
74 #define MVNETA_S(n) (0x2204 + ((n) << 3)) /* Size */
75 #define MVNETA_HA(n) (0x2280 + ((n) << 2)) /* High Address Remap */
76 #define MVNETA_BARE 0x2290 /* Base Address Enable */
[all …]
/freebsd/sys/dev/qlnx/qlnxe/
H A Dcommon_hsi.h50 #define ISCSI_CDU_TASK_SEG_TYPE 0
51 #define FCOE_CDU_TASK_SEG_TYPE 0
65 #define YSTORM_QZONE_SIZE 0
66 #define PSTORM_QZONE_SIZE 0
104 #define FW_ENGINEERING_VERSION 0
182 #define CDU_SEG_TYPE_OFFSET_REG_OFFSET_MASK (0x1ffff)
185 #define CDU_VF_FL_SEG_TYPE_OFFSET_REG_OFFSET_MASK (0xfff)
187 #define CDU_CONTEXT_VALIDATION_CFG_ENABLE_SHIFT (0)
199 #define DQ_DEMS_LEGACY 0
205 #define DQ_XCM_AGG_VAL_SEL_WORD2 0
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstructions.td3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
15 int Flat = 0;
29 field bit isRegisterLoad = 0;
30 field bit isRegisterStore = 0;
43 field bits<96> SoftFail = 0;
54 field bits<32> Inst = 0xffffffff;
71 bit hasIEEEFlag = 0;
72 bit hasZeroOpFlag = 0;
73 let mayLoad = 0;
74 let mayStore = 0;
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/Utils/
H A DAMDGPUBaseInfo.cpp3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
66 return VersionMajor >= 11 ? 10 : 0; in getVmcntBitShiftLo()
76 return VersionMajor >= 11 ? 0 : 4; in getExpcntBitShift()
97 return (VersionMajor == 9 || VersionMajor == 10) ? 2 : 0; in getVmcntBitWidthHi()
102 return VersionMajor >= 12 ? 6 : 0; in getLoadcntBitWidth()
107 return VersionMajor >= 12 ? 6 : 0; in getSamplecntBitWidth()
112 return VersionMajor >= 12 ? 3 : 0; in getBvhcntBitWidth()
117 return VersionMajor >= 12 ? 6 : 0; in getDscntBitWidth()
121 unsigned getDscntBitShift(unsigned VersionMajor) { return 0; } in getDscntBitShift()
125 return VersionMajor >= 10 ? 6 : 0; in getStorecntBitWidth()
[all …]
/freebsd/sys/dev/syscons/
H A Dscvgarndr.c54 #define SC_RENDER_DEBUG 0
108 RENDERER(mda, 0, txtrndrsw, vga_set);
109 RENDERER(cga, 0, txtrndrsw, vga_set);
110 RENDERER(ega, 0, txtrndrsw, vga_set);
111 RENDERER(vga, 0, txtrndrsw, vga_set);
161 0xC000, 0xA000, 0x9000, 0x8800, 0x8400, 0x8200, 0x8100, 0x8200,
162 0x8400, 0x8400, 0x8400, 0x9200, 0xB200, 0xA900, 0xC900, 0x8600, }, {
163 0x0000, 0x4000, 0x6000, 0x7000, 0x7800, 0x7C00, 0x7E00, 0x7C00,
164 0x7800, 0x7800, 0x7800, 0x6C00, 0x4C00, 0x4600, 0x0600, 0x0000, },
169 0xC000, 0xA000, 0x9000, 0x8800, 0x8400, 0x8200, 0x8100, 0x8700,
[all …]
/freebsd/contrib/expat/lib/
H A Dxmltok.c81 (namingBitmap[(pages[hi] << 3) + ((lo) >> 5)] & (1u << ((lo) & 0x1F)))
88 (namingBitmap[((pages)[(((byte)[0]) >> 2) & 7] << 3) \
89 + ((((byte)[0]) & 3) << 1) + ((((byte)[1]) >> 5) & 1)] \
90 & (1u << (((byte)[1]) & 0x1F)))
99 [((pages)[((((byte)[0]) & 0xF) << 4) + ((((byte)[1]) >> 2) & 0xF)] \
102 & (1u << (((byte)[2]) & 0x1F)))
107 code points 0xFFFF and 0xFFFE (sequences EF,BF,BF and EF,BF,BE).
109 (A & 0x80) == 0 means A < 0x80
111 (A & 0xC0) == 0xC0 means A > 0xBF
115 ((*p) < 0xC2 || ((p)[1] & 0x80) == 0 || ((p)[1] & 0xC0) == 0xC0)
[all …]

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