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/linux/drivers/gpu/drm/vboxvideo/
H A Dvboxvideo_vbe.h9 #define VBE_DISPI_BANK_ADDRESS 0xA0000
16 #define VBE_DISPI_IOPORT_INDEX 0x01CE
17 #define VBE_DISPI_IOPORT_DATA 0x01CF
19 #define VBE_DISPI_IOPORT_DAC_WRITE_INDEX 0x03C8
20 #define VBE_DISPI_IOPORT_DAC_DATA 0x03C9
22 #define VBE_DISPI_INDEX_ID 0x0
23 #define VBE_DISPI_INDEX_XRES 0x1
24 #define VBE_DISPI_INDEX_YRES 0x2
25 #define VBE_DISPI_INDEX_BPP 0x3
26 #define VBE_DISPI_INDEX_ENABLE 0x4
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/linux/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_hwio.h13 #define DISP_INTF_SEL 0x004
14 #define INTR_EN 0x010
15 #define INTR_STATUS 0x014
16 #define INTR_CLEAR 0x018
17 #define INTR2_EN 0x008
18 #define INTR2_STATUS 0x00c
19 #define SSPP_SPARE 0x028
20 #define INTR2_CLEAR 0x02c
21 #define HIST_INTR_EN 0x01c
22 #define HIST_INTR_STATUS 0x020
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/linux/Documentation/devicetree/bindings/pinctrl/
H A Dfsl,imxrt1170.yaml71 reg = <0x400e8000 0x4000>;
74 <0x16C 0x3B0 0x620 0x0 0x0 0xf1>,
75 <0x170 0x3B4 0x61C 0x0 0x0 0xf1>;
/linux/drivers/video/
H A Dvgastate.c37 vga_w(regbase, iobase + 0x4, reg); in vga_rcrtcs()
38 return vga_r(regbase, iobase + 0x5); in vga_rcrtcs()
44 vga_w(regbase, iobase + 0x4, reg); in vga_wcrtcs()
45 vga_w(regbase, iobase + 0x5, val); in vga_wcrtcs()
57 iobase = (misc & 1) ? 0x3d0 : 0x3b0; in save_vga_text()
59 vga_r(state->vgabase, iobase + 0xa); in save_vga_text()
60 vga_w(state->vgabase, VGA_ATT_W, 0x00); in save_vga_text()
61 attr10 = vga_rattr(state->vgabase, 0x10); in save_vga_text()
62 vga_r(state->vgabase, iobase + 0xa); in save_vga_text()
63 vga_w(state->vgabase, VGA_ATT_W, 0x20); in save_vga_text()
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/linux/arch/alpha/include/asm/
H A Dvga.h59 (((a) >= 0x3b0) && ((a) < 0x3e0) && \
60 ((a) != 0x3b3) && ((a) != 0x3d3))
63 (((a) >= 0xa0000) && ((a) <= 0xc0000))
68 } while(0)
73 } while(0)
76 # define pci_vga_hose 0
77 # define __is_port_vga(a) 0
78 # define __is_mem_vga(a) 0
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimxrt1050-pinfunc.h10 #define IMX_PAD_SION 0x40000000
17 #define MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00 0x014 0x204 0x000 0x0 0x0
18 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A 0x014 0x204 0x494 0x1 0x0
19 #define MXRT1050_IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x014 0x204 0x500 0x2 0x1
20 #define MXRT1050_IOMUXC_GPIO_EMC_00_XBAR_INOUT2 0x014 0x204 0x60C 0x3 0x0
21 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXIO1_D00 0x014 0x204 0x000 0x4 0x0
22 #define MXRT1050_IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x014 0x204 0x000 0x5 0x0
24 #define MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01 0x018 0x208 0x000 0x0 0x0
25 #define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B 0x018 0x208 0x000 0x1 0x0
26 #define MXRT1050_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x018 0x208 0x4FC 0x2 0x1
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H A Dimxrt1170-pinfunc.h10 #define IMX_PAD_SION 0x40000000
17 #define IOMUXC_GPIO_LPSR_00_FLEXCAN3_TX 0x000 0x040 0x0 0x0 0x0
18 #define IOMUXC_GPIO_LPSR_00_MIC_CLK 0x000 0x040 0x0 0x1 0x0
19 #define IOMUXC_GPIO_LPSR_00_MQS_RIGHT 0x000 0x040 0x0 0x2 0x0
20 #define IOMUXC_GPIO_LPSR_00_ARM_CM4_EVENTO 0x000 0x040 0x0 0x3 0x0
21 #define IOMUXC_GPIO_LPSR_00_GPIO_MUX6_IO00 0x000 0x040 0x0 0x5 0x0
22 #define IOMUXC_GPIO_LPSR_00_LPUART12_TXD 0x000 0x040 0x0B0 0x6 0x0
23 #define IOMUXC_GPIO_LPSR_00_SAI4_MCLK 0x000 0x040 0x0C8 0x7 0x0
24 #define IOMUXC_GPIO_LPSR_00_GPIO12_IO00 0x000 0x040 0x0 0xA 0x0
26 #define IOMUXC_GPIO_LPSR_01_FLEXCAN3_RX 0x004 0x044 0x080 0x0 0x0
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H A Dimx6q-pinfunc.h13 #define MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x04c 0x360 0x000 0x0 0x0
14 #define MX6QDL_PAD_SD2_DAT1__ECSPI5_SS0 0x04c 0x360 0x834 0x1 0x0
15 #define MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0x04c 0x360 0x000 0x2 0x0
16 #define MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x04c 0x360 0x7c8 0x3 0x0
17 #define MX6QDL_PAD_SD2_DAT1__KEY_COL7 0x04c 0x360 0x8f0 0x4 0x0
18 #define MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x04c 0x360 0x000 0x5 0x0
19 #define MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x050 0x364 0x000 0x0 0x0
20 #define MX6QDL_PAD_SD2_DAT2__ECSPI5_SS1 0x050 0x364 0x838 0x1 0x0
21 #define MX6QDL_PAD_SD2_DAT2__EIM_CS3_B 0x050 0x364 0x000 0x2 0x0
22 #define MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x050 0x364 0x7b8 0x3 0x0
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H A Dimx25-pinfunc.h16 #define MX25_PAD_A10__A10 0x008 0x000 0x000 0x00 0x000
17 #define MX25_PAD_A10__GPIO_4_0 0x008 0x000 0x000 0x05 0x000
19 #define MX25_PAD_A13__A13 0x00c 0x22C 0x000 0x00 0x000
20 #define MX25_PAD_A13__GPIO_4_1 0x00c 0x22C 0x000 0x05 0x000
21 #define MX25_PAD_A13__LCDC_CLS 0x00c 0x22C 0x000 0x07 0x000
23 #define MX25_PAD_A14__A14 0x010 0x230 0x000 0x00 0x000
24 #define MX25_PAD_A14__GPIO_2_0 0x010 0x230 0x000 0x05 0x000
25 #define MX25_PAD_A14__SIM1_CLK1 0x010 0x230 0x000 0x06 0x000
26 #define MX25_PAD_A14__LCDC_SPL 0x010 0x230 0x000 0x07 0x000
28 #define MX25_PAD_A15__A15 0x014 0x234 0x000 0x00 0x000
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H A Dimx53-pinfunc.h13 #define MX53_PAD_GPIO_19__KPP_COL_5 0x020 0x348 0x840 0x0 0x0
14 #define MX53_PAD_GPIO_19__GPIO4_5 0x020 0x348 0x000 0x1 0x0
15 #define MX53_PAD_GPIO_19__CCM_CLKO 0x020 0x348 0x000 0x2 0x0
16 #define MX53_PAD_GPIO_19__SPDIF_OUT1 0x020 0x348 0x000 0x3 0x0
17 #define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 0x020 0x348 0x000 0x4 0x0
18 #define MX53_PAD_GPIO_19__ECSPI1_RDY 0x020 0x348 0x000 0x5 0x0
19 #define MX53_PAD_GPIO_19__FEC_TDATA_3 0x020 0x348 0x000 0x6 0x0
20 #define MX53_PAD_GPIO_19__SRC_INT_BOOT 0x020 0x348 0x000 0x7 0x0
21 #define MX53_PAD_KEY_COL0__KPP_COL_0 0x024 0x34c 0x000 0x0 0x0
22 #define MX53_PAD_KEY_COL0__GPIO4_6 0x024 0x34c 0x000 0x1 0x0
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H A Dimx6sl-pinfunc.h13 #define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x04c 0x2a4 0x000 0x0 0x0
14 #define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0
15 #define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x0
16 #define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0
17 #define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0
18 #define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x0
19 #define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x04c 0x2a4 0x7f4 0x6 0x0
20 #define MX6SL_PAD_AUD_RXC__AUD3_RXC 0x050 0x2a8 0x000 0x0 0x0
21 #define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0
22 #define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0
[all …]
/linux/Documentation/devicetree/bindings/gpio/
H A Dst,spear-spics-gpio.yaml74 reg = <0xe0700000 0x1000>;
75 st-spics,peripcfg-reg = <0x3b0>;
/linux/drivers/video/fbdev/
H A Dhgafb.c23 * module parameter 'nologo={0|1}'
25 * - Revision 0.1.0 (6 Dec 1999): faster scrolling and minor fixes
47 #if 0
53 #if 0
65 #define HGA_TXT 0
73 static int hga_mode = -1; /* 0 = txt, 1 = gfx mode */
78 #define HGA_INDEX_PORT 0x3b4 /* Register select port */
79 #define HGA_VALUE_PORT 0x3b5 /* Register value port */
80 #define HGA_MODE_PORT 0x3b8 /* Mode control port */
81 #define HGA_STATUS_PORT 0x3ba /* Status and Config port */
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H A Di740_reg.h37 #define XRX 0x3D6
38 #define MRX 0x3D2
41 #define DACMASK 0x3C6
42 #define DACSTATE 0x3C7
43 #define DACRX 0x3C7
44 #define DACWX 0x3C8
45 #define DACDATA 0x3C9
48 #define START_ADDR_HI 0x0C
49 #define START_ADDR_LO 0x0D
50 #define VERT_SYNC_END 0x11
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/linux/arch/sh/include/mach-sdk7786/mach/
H A Dfpga.h9 #define SRSTR 0x000
10 #define SRSTR_MAGIC 0x1971 /* Fixed magical read value */
12 #define INTASR 0x010
13 #define INTAMR 0x020
14 #define MODSWR 0x030
15 #define INTTESTR 0x040
16 #define SYSSR 0x050
17 #define NRGPR 0x060
19 #define NMISR 0x070
20 #define NMISR_MAN_NMI BIT(0)
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/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mp-pinfunc.h10 #define MX8MP_DSE_X1 0x0
11 #define MX8MP_DSE_X2 0x4
12 #define MX8MP_DSE_X4 0x2
13 #define MX8MP_DSE_X6 0x6
16 #define MX8MP_FSEL_FAST 0x10
17 #define MX8MP_FSEL_SLOW 0x0
20 #define MX8MP_ODE_ENABLE 0x20
21 #define MX8MP_ODE_DISABLE 0x0
23 #define MX8MP_PULL_DOWN 0x0
24 #define MX8MP_PULL_UP 0x40
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H A Dimx8mm-pinfunc.h14 #define MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
15 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
16 #define MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
17 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
18 #define MX8MM_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
19 #define MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0…
20 #define MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0…
21 #define MX8MM_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0…
22 #define MX8MM_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0…
23 #define MX8MM_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0…
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H A Dimx8mq-pinfunc.h15 #define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0…
16 #define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0…
17 #define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0…
18 #define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0…
19 #define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0…
20 #define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
21 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
22 #define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
23 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
24 #define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
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/linux/drivers/infiniband/hw/hns/
H A Dhns_roce_common.h53 } while (0)
108 #define ROCEE_VENDOR_ID_REG 0x0
109 #define ROCEE_VENDOR_PART_ID_REG 0x4
111 #define ROCEE_SYS_IMAGE_GUID_L_REG 0xC
112 #define ROCEE_SYS_IMAGE_GUID_H_REG 0x10
114 #define ROCEE_PORT_GID_L_0_REG 0x50
115 #define ROCEE_PORT_GID_ML_0_REG 0x54
116 #define ROCEE_PORT_GID_MH_0_REG 0x58
117 #define ROCEE_PORT_GID_H_0_REG 0x5C
119 #define ROCEE_BT_CMD_H_REG 0x204
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/linux/drivers/net/wireless/realtek/rtw88/
H A Dpci.h17 #define RTK_PCI_CTRL 0x300
20 #define REG_DBI_WDATA_V1 0x03E8
21 #define REG_DBI_RDATA_V1 0x03EC
22 #define REG_DBI_FLAG_V1 0x03F0
28 #define REG_MDIO_V1 0x03F4
29 #define REG_PCIE_MIX_CFG 0x03F8
30 #define BITS_MDIO_ADDR_MASK GENMASK(4, 0)
33 #define RTW_PCI_MDIO_PG_OFFS_G1 0
37 #define RTK_PCIE_LINK_CFG 0x0719
40 #define BIT_CLKREQ_N_PAD BIT(0)
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/linux/drivers/crypto/qce/
H A Dregs-v5.h11 #define REG_VERSION 0x000
12 #define REG_STATUS 0x100
13 #define REG_STATUS2 0x104
14 #define REG_ENGINES_AVAIL 0x108
15 #define REG_FIFO_SIZES 0x10c
16 #define REG_SEG_SIZE 0x110
17 #define REG_GOPROC 0x120
18 #define REG_ENCR_SEG_CFG 0x200
19 #define REG_ENCR_SEG_SIZE 0x204
20 #define REG_ENCR_SEG_START 0x208
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/linux/drivers/phy/qualcomm/
H A Dphy-qcom-qmp-qserdes-txrx-v5_5nm.h10 #define QSERDES_V5_5NM_TX_BIST_MODE_LANENO 0x00
11 #define QSERDES_V5_5NM_TX_BIST_INVERT 0x04
12 #define QSERDES_V5_5NM_TX_CLKBUF_ENABLE 0x08
13 #define QSERDES_V5_5NM_TX_TX_EMP_POST1_LVL 0x0c
14 #define QSERDES_V5_5NM_TX_TX_IDLE_LVL_LARGE_AMP 0x10
15 #define QSERDES_V5_5NM_TX_TX_DRV_LVL 0x14
16 #define QSERDES_V5_5NM_TX_TX_DRV_LVL_OFFSET 0x18
17 #define QSERDES_V5_5NM_TX_RESET_TSYNC_EN 0x1c
18 #define QSERDES_V5_5NM_TX_PRE_STALL_LDO_BOOST_EN 0x20
19 #define QSERDES_V5_5NM_TX_LPB_EN 0x24
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/linux/drivers/scsi/qla4xxx/
H A Dql4_nvram.h13 #define FM93C56A_SIZE_8 0x100
14 #define FM93C56A_SIZE_16 0x80
15 #define FM93C66A_SIZE_8 0x200
16 #define FM93C66A_SIZE_16 0x100/* 4010 */
17 #define FM93C86A_SIZE_16 0x400/* 4022 */
19 #define FM93C56A_START 0x1
22 #define FM93C56A_READ 0x2
23 #define FM93C56A_WEN 0x0
24 #define FM93C56A_WRITE 0x1
25 #define FM93C56A_WRITE_ALL 0x0
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/linux/arch/arm/boot/dts/st/
H A Dspear1310.dtsi16 reg = <0xe0700000 0x1000>;
17 st-spics,peripcfg-reg = <0x3b0>;
28 reg = <0xeb800000 0x4000>;
30 phy-id = <0>;
37 reg = <0xeb804000 0x4000>;
46 reg = <0xeb808000 0x4000>;
55 reg = <0xb1000000 0x10000>;
56 interrupts = <0 68 0x4>;
57 phys = <&miphy0 0>;
64 reg = <0xb1800000 0x10000>;
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/linux/drivers/net/wireless/mediatek/mt76/mt7615/
H A Deeprom.c20 val |= FIELD_PREP(MT_EFUSE_CTRL_AIN, addr & ~0xf); in mt7615_efuse_read()
24 if (!mt76_poll(dev, base + MT_EFUSE_CTRL, MT_EFUSE_CTRL_KICK, 0, 1000)) in mt7615_efuse_read()
32 memset(data, 0x0, 16); in mt7615_efuse_read()
33 return 0; in mt7615_efuse_read()
36 for (i = 0; i < 4; i++) { in mt7615_efuse_read()
41 return 0; in mt7615_efuse_read()
55 return 0; in mt7615_efuse_init()
63 for (i = 0; i + 16 <= len; i += 16) { in mt7615_efuse_init()
71 return 0; in mt7615_efuse_init()
81 if (ret < 0) in mt7615_eeprom_load()
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