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/freebsd/sys/contrib/device-tree/src/powerpc/fsl/
H A Dmpc8548cds.dtsi36 nor@0,0 {
40 reg = <0x0 0x0 0x01000000>;
44 partition@0 {
45 reg = <0x0 0x0b00000>;
50 reg = <0x0b00000 0x0400000>;
55 reg = <0x0f00000 0x060000>;
60 reg = <0x0f60000 0x020000>;
66 reg = <0x0f80000 0x080000>;
72 board-control@1,0 {
74 reg = <0x1 0x0 0x1000>;
[all …]
/freebsd/sys/dev/cxgb/common/
H A Dcxgb_mc5.c42 DBGI_MODE_MBUS = 0,
47 #define IDT_CMD_READ 0
53 #define IDT_LAR_ADR0 0x180006
54 #define IDT_LAR_MODE144 0xffff0000
57 #define IDT_SCR_ADR0 0x180000
58 #define IDT_SSR0_ADR0 0x180002
59 #define IDT_SSR1_ADR0 0x180004
62 #define IDT_GMR_BASE_ADR0 0x180020
65 #define IDT_DATARY_BASE_ADR0 0
66 #define IDT_MSKARY_BASE_ADR0 0x80000
[all …]
/freebsd/sys/dev/rtwn/rtl8812a/
H A Dr12a_rx_desc.h34 #define R12A_RXDW1_AMSDU 0x00002000
35 #define R12A_RXDW1_AMPDU 0x00008000
36 #define R12A_RXDW1_CKSUM_ERR 0x00100000
37 #define R12A_RXDW1_IPV6 0x00200000
38 #define R12A_RXDW1_UDP 0x00400000
39 #define R12A_RXDW1_CKSUM 0x00800000
41 #define R12A_RXDW2_RPT_C2H 0x10000000
43 #define R12A_RXDW3_RATE_M 0x0000007f
44 #define R12A_RXDW3_RATE_S 0
46 #define R12A_RXDW4_SPLCP 0x00000001
[all …]
/freebsd/sys/amd64/include/
H A Ddb_machdep.h38 #define BKPT_INST 0xcc /* breakpoint instruction */
46 } while(0)
52 } while(0);
67 #define IS_WATCHPOINT_TRAP(type, code) 0
69 #define I_CALL 0xe8
70 #define I_CALLI 0xff
71 #define i_calli(ins) (((ins)&0xff) == I_CALLI && ((ins)&0x3800) == 0x1000)
72 #define I_RET 0xc3
73 #define I_IRET 0xcf
74 #define i_rex(ins) (((ins) & 0xff) == 0x41 || ((ins) & 0xff) == 0x43)
[all …]
/freebsd/sys/i386/include/
H A Ddb_machdep.h37 (kdb_frame->tf_eip & 0xffff) + \
38 ((kdb_frame->tf_cs & 0xffff) << 4) : \
41 #define BKPT_INST 0xcc /* breakpoint instruction */
49 } while(0)
55 } while(0);
70 #define IS_WATCHPOINT_TRAP(type, code) 0
72 #define I_CALL 0xe8
73 #define I_CALLI 0xff
74 #define I_RET 0xc3
75 #define I_IRET 0xcf
[all …]
/freebsd/sys/dev/qat/include/
H A Dadf_dev_err.h10 #define ADF_ERRSOU0 (0x3A000 + 0x00)
11 #define ADF_ERRSOU1 (0x3A000 + 0x04)
12 #define ADF_ERRSOU2 (0x3A000 + 0x08)
13 #define ADF_ERRSOU3 (0x3A000 + 0x0C)
14 #define ADF_ERRSOU4 (0x3A000 + 0xD0)
15 #define ADF_ERRSOU5 (0x3A000 + 0xD8)
16 #define ADF_ERRMSK0 (0x3A000 + 0x10)
17 #define ADF_ERRMSK1 (0x3A000 + 0x14)
18 #define ADF_ERRMSK2 (0x3A000 + 0x18)
19 #define ADF_ERRMSK3 (0x3A000 + 0x1C)
[all …]
/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dphy-mtk-xsphy.txt59 u2 port0 0x0000 MISC
60 0x0100 FMREG
61 0x0300 U2PHY_COM
62 u2 port1 0x1000 MISC
63 0x1100 FMREG
64 0x1300 U2PHY_COM
65 u2 port2 0x2000 MISC
67 u31 common 0x3000 DIG_GLB
68 0x3100 PHYA_GLB
69 u31 port0 0x3400 DIG_LN_TOP
[all …]
H A Dmediatek,xsphy.yaml20 u2 port0 0x0000 MISC
21 0x0100 FMREG
22 0x0300 U2PHY_COM
23 u2 port1 0x1000 MISC
24 0x1100 FMREG
25 0x1300 U2PHY_COM
26 u2 port2 0x2000 MISC
28 u31 common 0x3000 DIG_GLB
29 0x3100 PHYA_GLB
30 u31 port0 0x3400 DIG_LN_TOP
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/synaptics/
H A Dberlin4ct.dtsi27 #size-cells = <0>;
29 cpu0: cpu@0 {
32 reg = <0x0>;
41 reg = <0x1>;
50 reg = <0x2>;
59 reg = <0x3>;
73 CPU_SLEEP_0: cpu-sleep-0 {
76 arm,psci-suspend-param = <0x0010000>;
86 #clock-cells = <0>;
114 ranges = <0 0 0xf7000000 0x1000000>;
[all …]
/freebsd/sys/dts/arm/
H A Dannapurna-alpine.dts41 #size-cells = <0>;
43 cpu@0 {
46 reg = <0x0>;
49 d-cache-size = <0x8000>; // L1, 32K
50 i-cache-size = <0x8000>; // L1, 32K
51 timebase-frequency = <0>;
53 clock-frequency = <0>;
59 reg = <0x0>;
62 d-cache-size = <0x8000>; // L1, 32K
63 i-cache-size = <0x8000>; // L1, 32K
[all …]
/freebsd/sys/dev/ath/ath_hal/ar5212/
H A Dar5212phy.h23 #define AR_PHY_BASE 0x9800 /* base address of phy regs */
26 #define AR_PHY_TEST 0x9800 /* PHY test control */
27 #define PHY_AGC_CLR 0x10000000 /* disable AGC to A2 */
29 #define AR_PHY_TESTCTRL 0x9808 /* PHY Test Control/Status */
30 #define AR_PHY_TESTCTRL_TXHOLD 0x3800 /* Select Tx hold */
31 #define AR_PHY_TESTCTRL_TXSRC_ALT 0x00000080 /* Select input to tsdac along with bit 1 */
33 #define AR_PHY_TESTCTRL_TXSRC_SRC 0x00000002 /* Used with bit 7 */
36 #define AR_PHY_TURBO 0x9804 /* frame control register */
37 #define AR_PHY_FC_TURBO_MODE 0x00000001 /* Set turbo mode bits */
38 #define AR_PHY_FC_TURBO_SHORT 0x00000002 /* Set short symbols to turbo mode setting */
[all …]
/freebsd/sys/contrib/device-tree/src/mips/loongson/
H A Dls7a-pch.dtsi8 ranges = <0 0x10000000 0 0x10000000 0 0x10000000 /* PIO & CONF & APB */
9 0 0x20000000 0 0x2000000
[all...]
/freebsd/sys/contrib/device-tree/src/loongarch/
H A Dloongson-2k2000.dtsi17 #size-cells = <0>;
22 reg = <0x0>;
29 reg = <0x1>;
36 #clock-cells = <0>;
51 thermal-sensors = <&tsensor 0>;
71 ranges = <0x0 0x10000000 0x0 0x10000000 0x0 0x10000000>,
72 <0x0 0x02000000 0x0 0x02000000 0x0 0x02000000>,
73 <0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>,
74 <0xfe 0x0 0xfe 0x0 0x0 0x40000000>;
82 ranges = <1 0x0 0x0 0x18400000 0x4000>;
[all …]
H A Dloongson-2k1000.dtsi18 #size-cells = <0>;
20 cpu0: cpu@0 {
23 reg= <0x0>;
30 reg = <0x1>;
37 #clock-cells = <0>;
49 i2c-gpio-0 {
51 scl-gpios = <&gpio0 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
55 #size-cells = <0>;
66 #size-cells = <0>;
74 thermal-sensors = <&tsensor 0>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/pci/
H A Dmvebu-pci.txt23 0x82000000 0 r MBUS_ID(0xf0, 0x01) r 0 s
32 registers area. This range entry translates the '0x82000000 0 r' PCI
33 address into the 'MBUS_ID(0xf0, 0x01) r' CPU address, which is part
34 of the internal register window (as identified by MBUS_ID(0xf0,
35 0x01)).
39 0x8t000000 s 0 MBUS_ID(w, a) 0 1 0
79 value is 0.
99 bus-range = <0x00 0xff>;
103 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
104 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
[all …]
/freebsd/sys/contrib/device-tree/src/arm/marvell/
H A Darmada-xp-mv78260.dtsi27 #size-cells = <0>;
30 cpu@0 {
33 reg = <0>;
34 clocks = <&cpuclk 0>;
49 * MV78260 has 3 PCIe units Gen2.0: Two units can be
62 bus-range = <0x00 0xff>;
65 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
66 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
67 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
68 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
[all …]
H A Darmada-xp-mv78460.dtsi28 #size-cells = <0>;
31 cpu@0 {
34 reg = <0>;
35 clocks = <&cpuclk 0>;
66 * MV78460 has 4 PCIe units Gen2.0: Two units can be
79 bus-range = <0x00 0xff>;
82 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
83 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
84 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
85 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
[all …]
/freebsd/sys/dev/bxe/
H A D57710_int_offsets.h31 { 0x40, 0x0, 0x0, 0x0, 0x0}, // COMMON_SB_SIZE
32 { 0x40, 0x0, 0x0, 0x0, 0x0}, // COMMON_SB_DATA_SIZE
33 { 0x28, 0x0, 0x0, 0x0, 0x0}, // COMMON_SP_SB_SIZE
34 { 0x10, 0x0, 0x0, 0x0, 0x0}, // COMMON_SP_SB_DATA_SIZE
35 { 0x40, 0x0, 0x0, 0x0, 0x0}, // COMMON_DYNAMIC_HC_CONFIG_SIZE
36 { 0x10, 0x0, 0x0, 0x0, 0x0}, // COMMON_ASM_ASSERT_MSG_SIZE
37 { 0x8, 0x0, 0x0, 0x0, 0x0}, // COMMON_ASM_ASSERT_INDEX_SIZE
38 { 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_ASM_INVALID_ASSERT_OPCODE
39 { 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_RAM1_TEST_EVENT_ID
40 …{ 0x0, 0x0, 0x0, 0x0, 0x0}, // COMMON_INBOUND_INTERRUPT_TEST_AGG_INT_EVEN…
[all …]
/freebsd/sys/contrib/device-tree/src/arm/synaptics/
H A Dberlin2q.dtsi22 #size-cells = <0>;
25 cpu0: cpu@0 {
29 reg = <0>;
113 #clock-cells = <0>;
122 ranges = <0 0xf7000000 0x1000000>;
127 reg = <0xab0000 0x200>;
136 reg = <0xab0800 0x200>;
145 reg = <0xab1000 0x200>;
154 reg = <0xac0000 0x1000>;
163 reg = <0xad0000 0x58>;
[all …]
/freebsd/sys/dev/qat/qat_hw/qat_c4xxx/
H A Dadf_c4xxx_hw_data.h9 #define ADF_C4XXX_SRAM_BAR 0
13 #define ADF_C4XXX_TX_RINGS_MASK 0xF
21 #define ADF_C4XXX_SOFTSTRAPPULL0_OFFSET (0x344)
22 #define ADF_C4XXX_SOFTSTRAPPULL1_OFFSET (0x348)
23 #define ADF_C4XXX_SOFTSTRAPPULL2_OFFSET (0x34C)
26 #define ADF_C4XXX_FUSECTL0_OFFSET (0x350)
27 #define ADF_C4XXX_FUSECTL1_OFFSET (0x354)
28 #define ADF_C4XXX_FUSECTL2_OFFSET (0x358)
30 #define ADF_C4XXX_FUSE_PKE_MASK (0xFFF000)
31 #define ADF_C4XXX_FUSE_COMP_MASK (0x000FFF)
[all …]
/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Dam57xx-cl-som-am57x.dts19 memory@0 {
21 reg = <0x0 0x80000000 0x0 0x20000000>; /* 512 MB - minimal configuration */
27 pinctrl-0 = <&leds_pins_default>;
82 DRA7XX_CORE_IOPAD(0x347c, PIN_OUTPUT | MUX_MODE14) /* gpmc_a15.gpio2_5 */
88 DRA7XX_CORE_IOPAD(0x3800, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda.sda */
89 DRA7XX_CORE_IOPAD(0x3804, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl.scl */
95 DRA7XX_CORE_IOPAD(0x36a4, PIN_INPUT| MUX_MODE10) /* mcasp1_aclkx.i2c3_sda */
96 DRA7XX_CORE_IOPAD(0x36a8, PIN_INPUT| MUX_MODE10) /* mcasp1_fsx.i2c3_scl */
102 DRA7XX_CORE_IOPAD(0x36ac, PIN_INPUT| MUX_MODE10) /* mcasp1_acl.i2c4_sda */
103 DRA7XX_CORE_IOPAD(0x36b0, PIN_INPUT| MUX_MODE10) /* mcasp1_fsr.i2c4_scl */
[all …]
/freebsd/sys/dev/rtsx/
H A Drtsxreg.h30 #define RTSX_HCBAR 0x00
31 #define RTSX_HCBCTLR 0x04
37 #define RTSX_HDBAR 0x08
38 #define RTSX_HDBCTLR 0x0C
45 #define RTSX_BIPR 0x14
62 #define RTSX_HAIMR 0x10
63 #define RTSX_HAIMR_WRITE 0x40000000
64 #define RTSX_HAIMR_BUSY 0x80000000
67 #define RTSX_BIER 0x18
80 #define RTSX_FPDCTL 0xFC00
[all …]
/freebsd/sys/dev/mii/
H A Dbrgphyreg.h42 #define BRGPHY_MII_BMCR 0x00
43 #define BRGPHY_BMCR_RESET 0x8000
44 #define BRGPHY_BMCR_LOOP 0x4000
45 #define BRGPHY_BMCR_SPD0 0x2000 /* Speed select, lower bit */
46 #define BRGPHY_BMCR_AUTOEN 0x1000 /* Autoneg enabled */
47 #define BRGPHY_BMCR_PDOWN 0x0800 /* Power down */
48 #define BRGPHY_BMCR_ISO 0x0400 /* Isolate */
49 #define BRGPHY_BMCR_STARTNEG 0x0200 /* Restart autoneg */
50 #define BRGPHY_BMCR_FDX 0x0100 /* Duplex mode */
51 #define BRGPHY_BMCR_CTEST 0x0080 /* Collision test enable */
[all …]
/freebsd/sys/dev/cxgbe/cudbg/
H A Dcudbg_entity.h42 #define NUM_PCIE_CONFIG_REGS 0x61
51 #define CUDBG_MAX_TCAM_TID 0x800
55 #define SN_REG_ADDR 0x183f
56 #define BN_REG_ADDR 0x1819
57 #define NA_REG_ADDR 0x185a
58 #define MN_REG_ADDR 0x1803
60 #define A_MPS_VF_RPLCT_MAP0 0x1111c
61 #define A_MPS_VF_RPLCT_MAP1 0x11120
62 #define A_MPS_VF_RPLCT_MAP2 0x11124
63 #define A_MPS_VF_RPLCT_MAP3 0x11128
[all …]
/freebsd/sys/contrib/dev/rtw89/
H A Dpci.h10 #define MDIO_PG0_G1 0
14 #define RAC_CTRL_PPR 0x00
15 #define RAC_ANA03 0x03
17 #define RAC_ANA09 0x09
19 #define RAC_ANA0A 0x0A
21 #define RAC_ANA0C 0x0C
23 #define RAC_ANA0D 0x0D
25 #define RAC_ANA10 0x10
26 #define ADDR_SEL_PINOUT_DIS_VAL 0x3C4
28 #define RAC_REG_REV2 0x1
[all...]

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