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/freebsd/sys/contrib/device-tree/Bindings/iio/adc/
H A Dqcom,spmi-iadc.txt6 (channel 0). When using an external resistor it is to be described by
36 reg = <0x3600 0x100>;
37 interrupts = <0x0 0x36 0x0 IRQ_TYPE_EDGE_RISING>;
44 io-channels = <&pmic_iadc 0>;
H A Dqcom,spmi-iadc.yaml16 (channel 0). When using an external resistor it is to be described by
56 #size-cells = <0>;
60 reg = <0x3600>;
61 interrupts = <0x0 0x36 0x0 IRQ_TYPE_EDGE_RISING>;
/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dphy-mtk-xsphy.txt59 u2 port0 0x0000 MISC
60 0x0100 FMREG
61 0x0300 U2PHY_COM
62 u2 port1 0x1000 MISC
63 0x1100 FMREG
64 0x1300 U2PHY_COM
65 u2 port2 0x2000 MISC
67 u31 common 0x3000 DIG_GLB
68 0x3100 PHYA_GLB
69 u31 port0 0x3400 DIG_LN_TOP
[all …]
H A Dmediatek,xsphy.yaml20 u2 port0 0x0000 MISC
21 0x0100 FMREG
22 0x0300 U2PHY_COM
23 u2 port1 0x1000 MISC
24 0x1100 FMREG
25 0x1300 U2PHY_COM
26 u2 port2 0x2000 MISC
28 u31 common 0x3000 DIG_GLB
29 0x3100 PHYA_GLB
30 u31 port0 0x3400 DIG_LN_TOP
[all …]
/freebsd/sys/contrib/device-tree/src/arm/qcom/
H A Dqcom-pm8226.dtsi11 polling-delay = <0>;
38 pm8226_0: pm8226@0 {
40 reg = <0x0 SPMI_USID>;
42 #size-cells = <0>;
46 reg = <0x800>;
50 interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
58 interrupts = <0x0 0x
[all...]
H A Dqcom-pm8941.dtsi11 polling-delay = <0>;
39 pm8941_0: pm8941@0 {
41 reg = <0x0 SPMI_USID>;
43 #size-cells = <0>;
47 reg = <0x6000>,
48 <0x6100>;
50 interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>;
55 reg = <0x80
[all...]
/freebsd/sys/libkern/
H A Dcrc16.c32 /* CRC table for the CRC-16. The poly is 0x8005 (x16 + x15 + x2 + 1). */
34 0x0000, 0xC0C1, 0xC181, 0x0140, 0xC301, 0x03C0, 0x0280, 0xC241,
35 0xC601, 0x06C0, 0x0780, 0xC741, 0x0500, 0xC5C1, 0xC481, 0x0440,
36 0xCC01, 0x0CC0, 0x0D80, 0xCD41, 0x0F00, 0xCFC1, 0xCE81, 0x0E40,
37 0x0A00, 0xCAC1, 0xCB81, 0x0B40, 0xC901, 0x09C0, 0x0880, 0xC841,
38 0xD801, 0x18C0, 0x1980, 0xD941, 0x1B00, 0xDBC1, 0xDA81, 0x1A40,
39 0x1E00, 0xDEC1, 0xDF81, 0x1F40, 0xDD01, 0x1DC0, 0x1C80, 0xDC41,
40 0x1400, 0xD4C1, 0xD581, 0x1540, 0xD701, 0x17C0, 0x1680, 0xD641,
41 0xD201, 0x12C0, 0x1380, 0xD341, 0x1100, 0xD1C1, 0xD081, 0x1040,
42 0xF001, 0x30C0, 0x3180, 0xF141, 0x3300, 0xF3C1, 0xF281, 0x3240,
[all …]
/freebsd/sys/contrib/device-tree/src/powerpc/fsl/
H A Dmpc8569si-post.dtsi39 interrupts = <19 2 0 0>;
40 sleep = <&pmc 0x08000000>;
43 /* controller at 0xa000 */
49 bus-range = <0 255>;
51 interrupts = <26 2 0 0>;
52 sleep = <&pmc 0x20000000>;
54 pcie@0 {
55 reg = <0 0 0 0 0>;
60 interrupts = <26 2 0 0>;
61 interrupt-map-mask = <0xf800 0 0 7>;
[all …]
/freebsd/sys/contrib/device-tree/src/powerpc/
H A Dkmeter1.dts29 #size-cells = <0>;
31 PowerPC,8360@0 {
33 reg = <0x0>;
38 timebase-frequency = <0>; /* Filled in by U-Boot */
39 bus-frequency = <0>; /* Filled in by U-Boot */
40 clock-frequency = <0>; /* Filled in by U-Boot */
46 reg = <0 0>; /* Filled in by U-Boot */
54 ranges = <0x0 0xe0000000 0x00200000>;
55 reg = <0xe0000000 0x00000200>;
56 bus-frequency = <0>; /* Filled in by U-Boot */
[all …]
/freebsd/sys/dev/bnxt/bnxt_re/
H A Dib_verbs.h41 #define BNXT_RE_ROCE_V2_UDP_SPORT 0x8CD1
42 #define BNXT_RE_QP_RANDOM_QKEY 0x81818181
97 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_256MB 0x1cUL
488 return 0; in bnxt_re_init_pow2_flag()
508 return 0; in bnxt_re_init_rsvd_wqe_flag()
516 return _is_chip_gen_p5_p7(cctx) ? 0 : BNXT_QPLIB_RESERVED_QP_WRS; in bnxt_re_get_diff()
518 return 0; in bnxt_re_get_diff()
559 return (*(u16 *)a ^ *(u16 *)b) | (a32[0] ^ b32[0]) | in compare_ether_header()
572 /* CRC table for the CRC-16. The poly is 0x8005 (x16 + x15 + x2 + 1). */ in crc16()
574 0x0000, 0xC0C1, 0xC181, 0x0140, 0xC301, 0x03C0, 0x0280, 0xC241, in crc16()
[all …]
/freebsd/sys/dev/igc/
H A Digc_regs.h11 #define IGC_CTRL 0x00000 /* Device Control - RW */
12 #define IGC_STATUS 0x00008 /* Device Status - RO */
13 #define IGC_EECD 0x00010 /* EEPROM/Flash Control - RW */
15 #define IGC_EERD 0x12014 /* EEprom mode read - RW */
16 #define IGC_EEWR 0x12018 /* EEprom mode write - RW */
17 #define IGC_CTRL_EXT 0x00018 /* Extended Device Control - RW */
18 #define IGC_MDIC 0x00020 /* MDI Control - RW */
19 #define IGC_MDICNFG 0x00E04 /* MDI Config - RW */
20 #define IGC_FCAL 0x00028 /* Flow Control Address Low - RW */
21 #define IGC_FCAH 0x0002C /* Flow Control Address High -RW */
[all …]
/freebsd/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dscorpion_reg_map.h77 volatile char pad__0[0x8]; /* 0x0 - 0x8 */
78 volatile u_int32_t MAC_DMA_CR; /* 0x8 - 0xc */
79 volatile char pad__1[0x8]; /* 0xc - 0x14 */
80 volatile u_int32_t MAC_DMA_CFG; /* 0x14 - 0x18 */
81 volatile u_int32_t MAC_DMA_RXBUFPTR_THRESH; /* 0x18 - 0x1c */
82 volatile u_int32_t MAC_DMA_TXDPPTR_THRESH; /* 0x1c - 0x20 */
83 volatile u_int32_t MAC_DMA_MIRT; /* 0x20 - 0x24 */
84 volatile u_int32_t MAC_DMA_GLOBAL_IER; /* 0x24 - 0x28 */
85 volatile u_int32_t MAC_DMA_TIMT; /* 0x28 - 0x2c */
86 volatile u_int32_t MAC_DMA_RIMT; /* 0x2c - 0x30 */
[all …]
/freebsd/share/i18n/csmapper/BIG5/
H A DHKSCS%UCS@SIP.src5 SRC_ZONE 0x87-0xFE / 0x40-0xFE / 8
7 DST_INVALID 0xFFFE
13 # Unicode version: 5.1.0
21 0x8745 = 0x7267
22 0x8748 = 0x7CB1
23 0x874A = 0x7CC5
24 0x8750 = 0x42BF
25 0x8751 = 0x3617
26 0x8752 = 0x7352
27 0x8753 = 0x6E8B
[all …]
H A DUCS@SIP%HKSCS.src5 SRC_ZONE 0x0021 - 0xF9D4
7 DST_INVALID 0xFFFF
13 # Unicode version: 5.1.0
21 0x0021 = 0x9C71
22 0x003E = 0x9375
23 0x0046 = 0x9376
24 0x004E = 0x9548
25 0x0068 = 0x8EC6
26 0x0086 = 0x8BC5
27 0x0087 = 0x8BFA
[all …]
/freebsd/sys/dev/neta/
H A Dif_mvnetareg.h39 #define MVNETA_SIZE 0x4000
53 #if MVNETA_TX_QNUM_MAX & (MVNETA_TX_QNUM_MAX - 1) != 0
56 #if MVNETA_RX_QNUM_MAX & (MVNETA_RX_QNUM_MAX - 1) != 0
61 #define MVNETA_QUEUE_ALL 0xff
67 * GbE0 BASE 0x00007.0000 SIZE 0x4000
68 * GbE1 BASE 0x00007.4000 SIZE 0x4000
73 #define MVNETA_BASEADDR(n) (0x2200 + ((n) << 3)) /* Base Address */
74 #define MVNETA_S(n) (0x2204 + ((n) << 3)) /* Size */
75 #define MVNETA_HA(n) (0x2280 + ((n) << 2)) /* High Address Remap */
76 #define MVNETA_BARE 0x2290 /* Base Address Enable */
[all …]
/freebsd/sys/dev/qlnx/qlnxe/
H A Dcommon_hsi.h50 #define ISCSI_CDU_TASK_SEG_TYPE 0
51 #define FCOE_CDU_TASK_SEG_TYPE 0
65 #define YSTORM_QZONE_SIZE 0
66 #define PSTORM_QZONE_SIZE 0
104 #define FW_ENGINEERING_VERSION 0
182 #define CDU_SEG_TYPE_OFFSET_REG_OFFSET_MASK (0x1ffff)
185 #define CDU_VF_FL_SEG_TYPE_OFFSET_REG_OFFSET_MASK (0xfff)
187 #define CDU_CONTEXT_VALIDATION_CFG_ENABLE_SHIFT (0)
199 #define DQ_DEMS_LEGACY 0
205 #define DQ_XCM_AGG_VAL_SEL_WORD2 0
[all …]
/freebsd/sys/contrib/ncsw/Peripherals/QM/
H A Dqman_low.h54 #define REG_EQCR_PI_CINH 0x0000
55 #define REG_EQCR_CI_CINH 0x0004
56 #define REG_EQCR_ITR 0x0008
57 #define REG_DQRR_PI_CINH 0x0040
58 #define REG_DQRR_CI_CINH 0x0044
59 #define REG_DQRR_ITR 0x0048
60 #define REG_DQRR_DCAP 0x0050
61 #define REG_DQRR_SDQCR 0x0054
62 #define REG_DQRR_VDQCR 0x0058
63 #define REG_DQRR_PDQCR 0x005c
[all …]
/freebsd/sys/dev/e1000/
H A De1000_regs.h38 #define E1000_CTRL 0x00000 /* Device Control - RW */
39 #define E1000_CTRL_DUP 0x00004 /* Device Control Duplicate (Shadow) - RW */
40 #define E1000_STATUS 0x00008 /* Device Status - RO */
41 #define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */
42 #define E1000_EERD 0x00014 /* EEPROM Read - RW */
43 #define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */
44 #define E1000_FLA 0x0001C /* Flash Access - RW */
45 #define E1000_MDIC 0x00020 /* MDI Control - RW */
46 #define E1000_MDICNFG 0x00E04 /* MDI Config - RW */
47 #define E1000_REGISTER_SET_SIZE 0x20000 /* CSR Size */
[all …]
/freebsd/sys/dev/bge/
H A Dif_bgereg.h54 * device register space at offset 0x8000 to read any 32K chunk
60 * accessed directly. NIC memory addresses are offset by 0x01000000.
64 #define BGE_PAGE_ZERO 0x00000000
65 #define BGE_PAGE_ZERO_END 0x000000FF
66 #define BGE_SEND_RING_RCB 0x00000100
67 #define BGE_SEND_RING_RCB_END 0x000001FF
68 #define BGE_RX_RETURN_RING_RCB 0x00000200
69 #define BGE_RX_RETURN_RING_RCB_END 0x000002FF
70 #define BGE_STATS_BLOCK 0x00000300
71 #define BGE_STATS_BLOCK_END 0x00000AFF
[all …]
/freebsd/share/i18n/csmapper/CNS/
H A DUCS@BMP%CNS11643-4.src5 SRC_ZONE 0x3401 - 0x9F9E
7 DST_INVALID 0xFFFF
13 # Unicode version: 5.0.0
47 0x3401 = 0x2224
48 0x340C = 0x2157
49 0x3416 = 0x2336
50 0x341C = 0x2835
51 0x342C = 0x2337
52 0x342D = 0x2534
53 0x3430 = 0x2159
[all …]
H A DCNS11643-4%UCS@BMP.src5 SRC_ZONE 0x21-0x7E / 0x21-0x7E / 8
7 DST_INVALID 0xFFFE
13 # Unicode version: 5.0.0
47 0x2122 = 0x4E40
48 0x2123 = 0x4E41
49 0x2124 = 0x4E5A
50 0x2126 = 0x4E02
51 0x2127 = 0x4E29
52 0x212A = 0x5202
53 0x212B = 0x353E
[all …]
/freebsd/sys/dev/cxgbe/common/
H A Dt4_hw.c46 } while (0)
60 * at the time it indicated completion is stored there. Returns 0 if the
72 return 0; in t4_wait_op_done_val()
74 if (--attempts == 0) in t4_wait_op_done_val()
179 * Reset F_ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a in t4_hw_pci_read_cfg4()
181 * F_ENABLE is 0 so a simple register write is easier than a in t4_hw_pci_read_cfg4()
184 t4_write_reg(adap, A_PCIE_CFG_SPACE_REQ, 0); in t4_hw_pci_read_cfg4()
213 CH_ERR(adap, "firmware reports adapter error: %s (0x%08x)\n", in t4_report_fw_error()
291 t4_set_reg_field(sc, port_ctl_reg, F_PORTTXEN, 0); in check_tx_state()
298 #define X_CIM_PF_NOACCESS 0xeeeeeeee
[all …]
/freebsd/tools/test/iconv/ref/
H A DEUC-TW-rev1 0x0000 = 0x0000
2 0x0001 = 0x0001
3 0x0002 = 0x0002
4 0x0003 = 0x0003
5 0x0004 = 0x0004
6 0x0005 = 0x0005
7 0x0006 = 0x0006
8 0x0007 = 0x0007
9 0x0008 = 0x0008
10 0x0009 = 0x0009
[all …]
H A DUTF-16BE-rev1 0x00 = 0x0000
2 0x01 = 0x0100
3 0x02 = 0x0200
4 0x03 = 0x0300
5 0x04 = 0x0400
6 0x05 = 0x0500
7 0x06 = 0x0600
8 0x07 = 0x0700
9 0x08 = 0x0800
10 0x09 = 0x0900
[all …]
H A DUTF-16LE-rev1 0x00 = 0x0000
2 0x01 = 0x0001
3 0x02 = 0x0002
4 0x03 = 0x0003
5 0x04 = 0x0004
6 0x05 = 0x0005
7 0x06 = 0x0006
8 0x07 = 0x0007
9 0x08 = 0x0008
10 0x09 = 0x0009
[all …]

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