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/linux/Documentation/admin-guide/perf/
H A Dhns3-pmu.rst44 config=0x00204
46 config=0x10204
51 The bits 0~15 of config (here 0x0204) are the true hardware event code. If
52 two events have same value of bits 0~15 of config, that means they are
53 event pair. And the bit 16 of config indicates getting counter 0 or
59 counter 0 / counter 1
75 …$# perf stat -g -e hns3_pmu_sicl_0/config=0x00002,global=1/ -e hns3_pmu_sicl_0/config=0x10002,glob…
86 $# perf stat -a -e hns3_pmu_sicl_0/config=0x1020F,global=1/ -I 1000
90 is same as mac id. The "tc" filter option must be set to 0xF in this mode,
95 $# perf stat -a -e hns3_pmu_sicl_0/config=0x1020F,port=0,tc=0xF/ -I 1000
[all …]
/linux/drivers/gpu/drm/radeon/
H A Dsi.c159 #define DC_HPDx_CONTROL(x) (DC_HPD1_CONTROL + (x * 0xc))
160 #define DC_HPDx_INT_CONTROL(x) (DC_HPD1_INT_CONTROL + (x * 0xc))
161 #define DC_HPDx_INT_STATUS_REG(x) (DC_HPD1_INT_STATUS + (x * 0xc))
164 (0x8000 << 16) | (0x98f4 >> 2),
165 0x00000000,
166 (0x8040 << 16) | (0x98f4 >> 2),
167 0x00000000,
168 (0x8000 << 16) | (0xe80 >> 2),
169 0x00000000,
170 (0x8040 << 16) | (0xe80 >> 2),
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dsc8180x-pmics.dtsi22 hysteresis = <0>;
28 hysteresis = <0>;
34 hysteresis = <0>;
48 hysteresis = <0>;
54 hysteresis = <0>;
60 hysteresis = <0>;
69 pmc8180_0: pmic@0 {
71 reg = <0x0 SPMI_USID>;
73 #size-cells = <0>;
77 reg = <0x0800>;
[all …]
H A Dpmm8155au_1.dtsi21 hysteresis = <0>;
27 hysteresis = <0>;
33 hysteresis = <0>;
42 pmic@0 {
44 reg = <0x0 SPMI_USID>;
46 #size-cells = <0>;
50 reg = <0x0800>;
53 interrupts = <0x0 0x8 0x0 IRQ_TYPE_EDGE_BOTH>;
64 reg = <0x2400>;
65 interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_BOTH>;
[all …]
H A Dpm6150l.dtsi18 hysteresis = <0>;
24 hysteresis = <0>;
30 hysteresis = <0>;
41 reg = <0x4 SPMI_USID>;
43 #size-cells = <0>;
47 reg = <0x2400>;
48 interrupts = <0x4 0x24 0x0 IRQ_TYPE_EDGE_BOTH>;
49 #thermal-sensor-cells = <0>;
54 reg = <0x3100>;
55 interrupts = <0x4 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
[all …]
H A Dpm8150l.dtsi21 hysteresis = <0>;
27 hysteresis = <0>;
33 hysteresis = <0>;
44 reg = <0x4 SPMI_USID>;
46 #size-cells = <0>;
50 reg = <0x0800>;
57 reg = <0x2400>;
58 interrupts = <0x4 0x24 0x0 IRQ_TYPE_EDGE_BOTH>;
61 #thermal-sensor-cells = <0>;
66 reg = <0x3100>;
[all …]
H A Dpm6125.dtsi19 hysteresis = <0>;
25 hysteresis = <0>;
31 hysteresis = <0>;
40 pmic@0 {
42 reg = <0x0 SPMI_USID>;
44 #size-cells = <0>;
48 reg = <0x800>;
49 mode-bootloader = <0x2>;
50 mode-recovery = <0x1>;
54 interrupts = <0x0 0x8 0x0 IRQ_TYPE_EDGE_BOTH>;
[all …]
H A Dpm6150.dtsi22 hysteresis = <0>;
28 hysteresis = <0>;
37 pm6150_lsid0: pmic@0 {
39 reg = <0x0 SPMI_USID>;
41 #size-cells = <0>;
45 reg = <0x800>;
46 mode-bootloader = <0x2>;
47 mode-recovery = <0x1>;
51 interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
59 interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>;
[all …]
H A Dpm8150b.dtsi21 hysteresis = <0>;
27 hysteresis = <0>;
33 hysteresis = <0>;
44 reg = <0x2 SPMI_USID>;
46 #size-cells = <0>;
50 reg = <0x0800>;
58 reg = <0x1100>;
64 reg = <0x1500>,
65 <0x1700>;
66 interrupts = <0x2 0x15 0x00 IRQ_TYPE_EDGE_RISING>,
[all …]
H A Dpmi632.dtsi20 hysteresis = <0>;
26 hysteresis = <0>;
32 hysteresis = <0>;
43 reg = <0x2 SPMI_USID>;
45 #size-cells = <0>;
49 reg = <0x1100>;
55 reg = <0x1500>;
56 interrupts = <0x2 0x15 0x00 IRQ_TYPE_EDGE_RISING>,
57 <0x2 0x15 0x01 IRQ_TYPE_EDGE_BOTH>,
58 <0x2 0x15 0x02 IRQ_TYPE_EDGE_RISING>,
[all …]
H A Dpm7250b.dtsi20 hysteresis = <0>;
26 hysteresis = <0>;
32 hysteresis = <0>;
45 #size-cells = <0>;
49 reg = <0x1100>;
55 reg = <0x1500>,
56 <0x1700>;
57 interrupts = <PM7250B_SID 0x15 0x00 IRQ_TYPE_EDGE_RISING>,
58 <PM7250B_SID 0x15 0x01 IRQ_TYPE_EDGE_BOTH>,
59 <PM7250B_SID 0x15 0x02 IRQ_TYPE_EDGE_RISING>,
[all …]
/linux/Documentation/devicetree/bindings/gpio/
H A Drealtek,otto-gpio.yaml24 pattern: "^gpio@[0-9a-f]+$"
86 reg = <0x3500 0x1c>;
98 reg = <0x3300 0x1c>, <0x3338 0x8>;
/linux/sound/soc/codecs/
H A Drt700.h30 #define RT700_AUDIO_FUNCTION_GROUP 0x01
31 #define RT700_DAC_OUT1 0x02
32 #define RT700_DAC_OUT2 0x03
33 #define RT700_ADC_IN1 0x09
34 #define RT700_ADC_IN2 0x08
35 #define RT700_DMIC1 0x12
36 #define RT700_DMIC2 0x13
37 #define RT700_SPK_OUT 0x14
38 #define RT700_MIC2 0x19
39 #define RT700_LINE1 0x1a
[all …]
H A Drt715.h30 #define RT715_AUDIO_FUNCTION_GROUP 0x01
31 #define RT715_MIC_ADC 0x07
32 #define RT715_LINE_ADC 0x08
33 #define RT715_MIX_ADC 0x09
34 #define RT715_DMIC1 0x12
35 #define RT715_DMIC2 0x13
36 #define RT715_MIC1 0x18
37 #define RT715_MIC2 0x19
38 #define RT715_LINE1 0x1a
39 #define RT715_LINE2 0x1
[all...]
H A Drt711.h32 #define RT711_AUDIO_FUNCTION_GROUP 0x01
33 #define RT711_DAC_OUT2 0x03
34 #define RT711_ADC_IN1 0x09
35 #define RT711_ADC_IN2 0x08
36 #define RT711_DMIC1 0x12
37 #define RT711_DMIC2 0x13
38 #define RT711_MIC2 0x19
39 #define RT711_LINE1 0x1a
40 #define RT711_LINE2 0x1b
41 #define RT711_BEEP 0x1d
[all …]
/linux/Documentation/devicetree/bindings/phy/
H A Dmediatek,xsphy.yaml20 u2 port0 0x0000 MISC
21 0x0100 FMREG
22 0x0300 U2PHY_COM
23 u2 port1 0x1000 MISC
24 0x1100 FMREG
25 0x1300 U2PHY_COM
26 u2 port2 0x2000 MISC
28 u31 common 0x3000 DIG_GLB
29 0x3100 PHYA_GLB
30 u31 port0 0x3400 DIG_LN_TOP
[all …]
/linux/drivers/mfd/
H A Dsi476x-prop.c25 for (i = 0; i < size; i++) in si476x_core_element_is_in_array()
38 for (i = 0; i < size; i++) in si476x_core_element_is_in_range()
49 0x0000, in si476x_core_is_valid_property_a10()
50 0x0500, 0x0501, in si476x_core_is_valid_property_a10()
51 0x0600, in si476x_core_is_valid_property_a10()
52 0x0709, 0x070C, 0x070D, 0x70E, 0x710, in si476x_core_is_valid_property_a10()
53 0x0718, in si476x_core_is_valid_property_a10()
54 0x1207, 0x1208, in si476x_core_is_valid_property_a10()
55 0x2007, in si476x_core_is_valid_property_a10()
56 0x2300, in si476x_core_is_valid_property_a10()
[all …]
/linux/drivers/scsi/qla4xxx/
H A Dql4_83xx.h11 #define QLA83XX_FLASH_SPI_STATUS 0x2808E010
12 #define QLA83XX_FLASH_SPI_CONTROL 0x2808E014
13 #define QLA83XX_FLASH_STATUS 0x42100004
14 #define QLA83XX_FLASH_CONTROL 0x42110004
15 #define QLA83XX_FLASH_ADDR 0x42110008
16 #define QLA83XX_FLASH_WRDATA 0x4211000C
17 #define QLA83XX_FLASH_RDDATA 0x42110018
18 #define QLA83XX_FLASH_DIRECT_WINDOW 0x42110030
19 #define QLA83XX_FLASH_DIRECT_DATA(DATA) (0x42150000 | (0x0000FFFF&DATA))
24 #define QLA83XX_FLASH_LOCK 0x3850
[all …]
/linux/Documentation/devicetree/bindings/thermal/
H A Dqcom-spmi-adc-tm5.yaml33 const: 0
59 "^([-a-z0-9]*)@[0-7]$":
67 minimum: 0
80 channel will be calibrated with 0V and 1.25V reference channels,
139 "^([-a-z0-9]*)@[0-7]$":
171 #size-cells = <0>;
175 reg = <0x3100>;
177 #size-cells = <0>;
191 reg = <0x3500>;
192 interrupts = <0x2 0x35 0x0 IRQ_TYPE_EDGE_RISING>;
[all …]
/linux/drivers/media/i2c/
H A Dov5675.c28 #define OV5675_REG_CHIP_ID 0x300a
29 #define OV5675_CHIP_ID 0x5675
31 #define OV5675_REG_MODE_SELECT 0x0100
32 #define OV5675_MODE_STANDBY 0x00
33 #define OV5675_MODE_STREAMING 0x01
36 #define OV5675_REG_VTS 0x380e
37 #define OV5675_VTS_30FPS 0x07e4
38 #define OV5675_VTS_30FPS_MIN 0x07e4
39 #define OV5675_VTS_MAX 0x7fff
42 #define OV5675_REG_HTS 0x380c
[all …]
H A Dov5695.c30 #define CHIP_ID 0x005695
31 #define OV5695_REG_CHIP_ID 0x300a
33 #define OV5695_REG_CTRL_MODE 0x0100
34 #define OV5695_MODE_SW_STANDBY 0x0
35 #define OV5695_MODE_STREAMING BIT(0)
37 #define OV5695_REG_EXPOSURE 0x3500
40 #define OV5695_VTS_MAX 0x7fff
42 #define OV5695_REG_ANALOG_GAIN 0x3509
43 #define ANALOG_GAIN_MIN 0x10
44 #define ANALOG_GAIN_MAX 0xf8
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/oss/
H A Doss_2_4_d.h27 #define mmIH_VMID_0_LUT 0xe00
28 #define mmIH_VMID_1_LUT 0xe01
29 #define mmIH_VMID_2_LUT 0xe02
30 #define mmIH_VMID_3_LUT 0xe03
31 #define mmIH_VMID_4_LUT 0xe04
32 #define mmIH_VMID_5_LUT 0xe05
33 #define mmIH_VMID_6_LUT 0xe06
34 #define mmIH_VMID_7_LUT 0xe07
35 #define mmIH_VMID_8_LUT 0xe08
36 #define mmIH_VMID_9_LUT 0xe09
[all …]
H A Doss_3_0_1_d.h27 #define mmIH_VMID_0_LUT 0xe00
28 #define mmIH_VMID_1_LUT 0xe01
29 #define mmIH_VMID_2_LUT 0xe02
30 #define mmIH_VMID_3_LUT 0xe03
31 #define mmIH_VMID_4_LUT 0xe04
32 #define mmIH_VMID_5_LUT 0xe05
33 #define mmIH_VMID_6_LUT 0xe06
34 #define mmIH_VMID_7_LUT 0xe07
35 #define mmIH_VMID_8_LUT 0xe08
36 #define mmIH_VMID_9_LUT 0xe09
[all …]
/linux/drivers/scsi/qla2xxx/
H A Dqla_nx2.h11 #define INTENT_TO_RECOVER 0x01
12 #define PROCEED_TO_RECOVER 0x02
13 #define IDC_LOCK_RECOVERY_OWNER_MASK 0x3C
14 #define IDC_LOCK_RECOVERY_STATE_MASK 0x3
18 #define QLA8044_ADDR_DDR_NET (0x0000000000000000ULL)
19 #define QLA8044_ADDR_DDR_NET_MAX (0x000000000fffffffULL)
21 #define MD_MIU_TEST_AGT_WRDATA_LO 0x410000A0
22 #define MD_MIU_TEST_AGT_WRDATA_HI 0x410000A4
23 #define MD_MIU_TEST_AGT_WRDATA_ULO 0x410000B0
24 #define MD_MIU_TEST_AGT_WRDATA_UHI 0x410000B4
[all …]
/linux/Documentation/devicetree/bindings/mfd/
H A Dqcom,spmi-pmic.yaml30 - pattern: '^pm(a|s)?[0-9]*@.*$'
112 const: 0
127 "^adc@[0-9a-f]+$":
134 "^adc-tm@[0-9a-f]+$":
138 "^audio-codec@[0-9a-f]+$":
142 "^battery@[0-9a-f]+$":
147 "^charger@[0-9a-f]+$":
155 "gpio@[0-9a-f]+$":
159 "^led-controller@[0-9a-f]+$":
163 "^nvram@[0-9a-f]+$":
[all …]

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