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/freebsd/sys/contrib/device-tree/src/arm/aspeed/
H A Dibm-power9-dual.dtsi5 cfam@0,0 {
6 reg = <0 0>;
9 chip-id = <0>;
13 reg = <0x1000 0x400>;
18 reg = <0x1800 0x400>;
20 #size-cells = <0>;
22 cfam0_i2c0: i2c-bus@0 {
23 reg = <0>;
85 reg = <0x2400 0x400>;
87 #size-cells = <0>;
[all …]
H A Daspeed-bmc-ibm-everest.dts175 reg = <0x80000000 0x40000000>;
185 reg = <0xb3d00000 0x100000>;
190 reg = <0xb3e00000 0x200000>; /* 16 * (4 * 0x8000) */
191 record-size = <0x8000>;
192 console-size = <0x8000>;
193 ftrace-size = <0x800
[all...]
H A Daspeed-bmc-opp-tacoma.dts21 reg = <0x80000000 0x40000000>;
31 reg = <0xb8000000 0x4000000>; /* 64M */
36 reg = <0xbc000000 0x180000>; /* 16 * (3 * 0x8000) */
37 record-size = <0x8000>;
38 console-size = <0x8000>;
39 pmsg-size = <0x800
[all...]
H A Daspeed-bmc-opp-palmetto.dts17 reg = <0x40000000 0x20000000>;
27 reg = <0x5f000000 0x01000000>; /* 16M */
31 reg = <0x5ee00000 0x00200000>;
37 reg = <0x5C000000 0x02000000>; /* 32MB */
60 #size-cells = <0>;
69 enable-gpios = <&gpio ASPEED_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
86 flash@0 {
98 pinctrl-0 = <&pinctrl_spi1debug_default>;
100 flash@0 {
110 pinctrl-0 = <&pinctrl_flbusy_default &pinctrl_flwp_default
[all …]
H A Daspeed-bmc-ibm-bonnell.dts29 reg = <0x80000000 0x40000000>;
39 reg = <0xb3d00000 0x100000>;
44 reg = <0xb3e00000 0x200000>; /* 16 * (4 * 0x8000) */
45 record-size = <0x8000>;
46 console-size = <0x8000>;
47 ftrace-size = <0x800
[all...]
H A Daspeed-bmc-ibm-rainier.dts40 reg = <0x80000000 0x40000000>;
50 reg = <0xb3e00000 0x200000>; /* 16 * (4 * 0x8000) */
51 record-size = <0x8000>;
52 console-size = <0x8000>;
53 ftrace-size = <0x8000>;
54 pmsg-size = <0x8000>;
61 reg = <0xb400000
[all...]
/freebsd/share/i18n/csmapper/CNS/
H A DUCS@BMP%CNS11643-6.src5 SRC_ZONE 0x3400 - 0x9775
7 DST_INVALID 0xFFFF
13 # Unicode version: 5.0.0
47 0x3400 = 0x222C
48 0x3404 = 0x2130
49 0x3405 = 0x2123
50 0x3438 = 0x234E
51 0x3445 = 0x2571
52 0x3458 = 0x2E5A
53 0x3467 = 0x3538
[all …]
H A DCNS11643-6%UCS@BMP.src5 SRC_ZONE 0x21-0x7E / 0x21-0x7E / 8
7 DST_INVALID 0xFFFE
13 # Unicode version: 5.0.0
47 0x2123 = 0x3405
48 0x2130 = 0x3404
49 0x213B = 0x353F
50 0x216E = 0x382A
51 0x2179 = 0x38A7
52 0x217E = 0x38FA
53 0x222C = 0x3400
[all …]
/freebsd/sys/contrib/device-tree/include/dt-bindings/pinctrl/
H A Ddra.h13 #define MUX_MODE0 0x0
14 #define MUX_MODE1 0x1
15 #define MUX_MODE2 0x2
16 #define MUX_MODE3 0x3
17 #define MUX_MODE4 0x4
18 #define MUX_MODE5 0x5
19 #define MUX_MODE6 0x6
20 #define MUX_MODE7 0x7
21 #define MUX_MODE8 0x8
22 #define MUX_MODE9 0x9
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dpmk8350.dtsi13 #define PMK8350_SID 0
21 mode-recovery = <0x01>;
22 mode-bootloader = <0x02>;
31 #size-cells = <0>;
35 reg = <0x1300>, <0x800>;
40 interrupts = <PMK8350_SID 0x13 0x7 IRQ_TYPE_EDGE_BOTH>;
47 interrupts = <PMK8350_SID 0x13 0x
[all...]
H A Dpm8998.dtsi35 pm8998_lsid0: pmic@0 {
37 reg = <0x0 SPMI_USID>;
39 #size-cells = <0>;
44 reg = <0x800>;
45 mode-bootloader = <0x2>;
46 mode-recovery = <0x1>;
50 interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
58 interrupts = <0x
[all...]
H A Dsc8280xp-pmics.dtsi14 polling-delay = <0>;
20 hysteresis = <0>;
26 hysteresis = <0>;
34 polling-delay = <0>;
40 hysteresis = <0>;
46 hysteresis = <0>;
55 pmk8280: pmic@0 {
57 reg = <0x0 SPMI_USID>;
59 #size-cells = <0>;
63 reg = <0x130
[all...]
/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dqcom,msm8996-qmp-pcie-phy.yaml57 "^phy@[0-9a-f]+$":
92 const: 0
98 const: 0
130 reg = <0x34000 0x488>;
133 ranges = <0x0 0x34000 0x4000>;
149 reg = <0x1000 0x130>,
150 <0x1200 0x200>,
151 <0x1400 0x1dc>;
156 #clock-cells = <0>;
159 #phy-cells = <0>;
[all …]
H A Dphy-mtk-xsphy.txt59 u2 port0 0x0000 MISC
60 0x0100 FMREG
61 0x0300 U2PHY_COM
62 u2 port1 0x1000 MISC
63 0x1100 FMREG
64 0x1300 U2PHY_COM
65 u2 port2 0x2000 MISC
67 u31 common 0x3000 DIG_GLB
68 0x3100 PHYA_GLB
69 u31 port0 0x3400 DIG_LN_TOP
[all …]
H A Dmediatek,xsphy.yaml20 u2 port0 0x0000 MISC
21 0x0100 FMREG
22 0x0300 U2PHY_COM
23 u2 port1 0x1000 MISC
24 0x1100 FMREG
25 0x1300 U2PHY_COM
26 u2 port2 0x2000 MISC
28 u31 common 0x3000 DIG_GLB
29 0x3100 PHYA_GLB
30 u31 port0 0x3400 DIG_LN_TOP
[all …]
/freebsd/sys/contrib/device-tree/Bindings/thermal/
H A Dqcom-spmi-adc-tm-hc.yaml31 const: 0
55 "^([-a-z0-9]*)@[0-7]$":
63 minimum: 0
76 channel will be calibrated with 0V and 1.25V reference channels,
81 enum: [0, 100, 200, 300, 400, 500, 600, 700, 1000, 2000, 4000, 6000, 8000, 10000]
120 #size-cells = <0>;
124 reg = <0x3100>;
126 #size-cells = <0>;
137 reg = <0x3400>;
[all...]
H A Dqcom-spmi-adc-tm5.yaml34 const: 0
60 "^([-a-z0-9]*)@[0-7]$":
68 minimum: 0
81 channel will be calibrated with 0V and 1.25V reference channels,
140 "^([-a-z0-9]*)@[0-7]$":
173 #size-cells = <0>;
177 reg = <0x3100>;
179 #size-cells = <0>;
193 reg = <0x3500>;
194 interrupts = <0x
[all...]
/freebsd/sys/dev/etherswitch/e6000sw/
H A De6000swreg.h44 #define MV88E6141 0x3400
45 #define MV88E6341 0x3410
46 #define MV88E6352 0x3520
47 #define MV88E6172 0x1720
48 #define MV88E6176 0x1760
49 #define MV88E6190 0x1900
52 #define MVSWITCH_MULTICHIP(_sc) ((_sc)->sw_addr != 0)
57 #define REG_GLOBAL 0x1b
58 #define REG_GLOBAL2 0x1c
59 #define REG_PORT(_sc, p) ((MVSWITCH((_sc), MV88E6190) ? 0 : 0x10) + (p))
[all …]
/freebsd/sys/contrib/device-tree/src/powerpc/fsl/
H A Dmpc8569si-post.dtsi39 interrupts = <19 2 0 0>;
40 sleep = <&pmc 0x08000000>;
43 /* controller at 0xa000 */
49 bus-range = <0 255>;
51 interrupts = <26 2 0 0>;
52 sleep = <&pmc 0x20000000>;
54 pcie@0 {
55 reg = <0 0 0 0 0>;
60 interrupts = <26 2 0 0>;
61 interrupt-map-mask = <0xf800 0 0 7>;
[all …]
/freebsd/sys/contrib/device-tree/src/powerpc/
H A Dmpc836x_rdk.dts32 #size-cells = <0>;
34 PowerPC,8360@0 {
36 reg = <0>;
42 timebase-frequency = <0>;
43 bus-frequency = <0>;
44 clock-frequency = <0>;
51 reg = <0 0>;
60 ranges = <0 0xe0000000 0x200000>;
61 reg = <0xe0000000 0x200>;
63 bus-frequency = <0>;
[all …]
H A Dkmeter1.dts29 #size-cells = <0>;
31 PowerPC,8360@0 {
33 reg = <0x0>;
38 timebase-frequency = <0>; /* Filled in by U-Boot */
39 bus-frequency = <0>; /* Filled in by U-Boot */
40 clock-frequency = <0>; /* Filled in by U-Boot */
46 reg = <0 0>; /* Filled in by U-Boot */
54 ranges = <0x0 0xe0000000 0x00200000>;
55 reg = <0xe0000000 0x00000200>;
56 bus-frequency = <0>; /* Filled in by U-Boot */
[all …]
/freebsd/crypto/heimdal/lib/wind/
H A Dbidi_table.c9 {0x5be, 1},
10 {0x5c0, 1},
11 {0x5c3, 1},
12 {0x5d0, 0x1b},
13 {0x5f0, 0x5},
14 {0x61b, 1},
15 {0x61f, 1},
16 {0x621, 0x1a},
17 {0x640, 0xb},
18 {0x66d, 0x3},
[all …]
/freebsd/sys/dev/hdmi/
H A Ddwc_hdmireg.h29 #define HDMI_DESIGN_ID 0x0000
30 #define HDMI_REVISION_ID 0x0001
31 #define HDMI_PRODUCT_ID0 0x0002
32 #define HDMI_PRODUCT_ID1 0x0003
35 #define HDMI_IH_FC_STAT0 0x0100
36 #define HDMI_IH_FC_STAT1 0x0101
37 #define HDMI_IH_FC_STAT2 0x0102
38 #define HDMI_IH_AS_STAT0 0x0103
39 #define HDMI_IH_PHY_STAT0 0x0104
40 #define HDMI_IH_PHY_STAT0_HPD (1 << 0)
[all …]
/freebsd/sys/dev/ral/
H A Drt2661reg.h35 #define RT2661_HOST_CMD_CSR 0x0008
36 #define RT2661_MCU_CNTL_CSR 0x000c
37 #define RT2661_SOFT_RESET_CSR 0x0010
38 #define RT2661_MCU_INT_SOURCE_CSR 0x0014
39 #define RT2661_MCU_INT_MASK_CSR 0x0018
40 #define RT2661_PCI_USEC_CSR 0x001c
41 #define RT2661_H2M_MAILBOX_CSR 0x2100
42 #define RT2661_M2H_CMD_DONE_CSR 0x2104
43 #define RT2661_HW_BEACON_BASE0 0x2c00
44 #define RT2661_MAC_CSR0 0x3000
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Support/
H A DUnicodeNameToCodepoint.cpp4 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
33 char32_t Value = 0xFFFFFFFF;
34 uint32_t ChildrenOffset = 0;
36 uint32_t Size = 0;
41 return !Name.empty() || Value == 0xFFFFFFFF; in isValid()
43 constexpr bool hasChildren() const { return ChildrenOffset != 0 || IsRoot; } in hasChildren()
70 if (Offset == 0) in readNode()
80 bool LongName = NameInfo & 0x40; in readNode()
81 bool HasValue = NameInfo & 0x80; in readNode()
82 std::size_t Size = NameInfo & ~0xC in readNode()
[all...]

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