Lines Matching +full:0 +full:x3400

44 #define	MV88E6141	0x3400
45 #define	MV88E6341	0x3410
46 #define	MV88E6352	0x3520
47 #define	MV88E6172	0x1720
48 #define	MV88E6176	0x1760
49 #define	MV88E6190	0x1900
50 #define	MV88E6190X	0x0a00
53 #define	MVSWITCH_MULTICHIP(_sc)	((_sc)->sw_addr != 0)
58 #define	REG_GLOBAL			0x1b
59 #define	REG_GLOBAL2			0x1c
60 #define	REG_PORT(_sc, p)		(((MVSWITCH((_sc), MV88E6190) || MVSWITCH((_sc), MV88E6190X)) ? 0 : 0x10) + (p))
67 #define	PORT_STATUS			0x0
68 #define	PORT_STATUS_SPEED_MASK		0x300
69 #define	PORT_STATUS_SPEED_10		0
76 #define	PSC_CONTROL			0x1
87 #define	PSC_CONTROL_SPD10G		0x3
89 #define	PSC_CONTROL_SPD1000		0x2
90 #define	SWITCH_ID			0x3
91 #define	PORT_CONTROL			0x4
92 #define	PORT_CONTROL1			0x5
94 #define	 PORT_CONTROL1_LAG_ID_MASK	0xf
96 #define	 PORT_CONTROL1_FID_MASK		0xf
97 #define	PORT_VLAN_MAP			0x6
98 #define	PORT_VID			0x7
99 #define	PORT_CONTROL2			0x8
100 #define	PORT_ASSOCIATION_VECTOR		0xb
101 #define	PORT_ATU_CTRL			0xc
102 #define	RX_COUNTER			0x12
103 #define	TX_COUNTER			0x13
105 #define	PORT_MASK(_sc)			0x7f
106 #define	PORT_VID_DEF_VID		0
107 #define	PORT_VID_DEF_VID_MASK		0xfff
108 #define	PORT_VID_PRIORITY_MASK		0xc00
110 #define	PORT_CONTROL_DISABLED		0
115 #define	PORT_CONTROL_FRAME		0x0300
116 #define	PORT_CONTROL_EGRESS		0x3000
117 #define	PORT_CONTROL2_DOT1Q		0x0c00
123 #define	PORT_VLAN_MAP_FID_MASK		0xf000
128 #define	SWITCH_GLOBAL_STATUS		0
142 #define	VTU_FID_MASK(_sc)		((MVSWITCH((_sc), MV88E6190) || MVSWITCH((_sc), MV88E6190X)) ? 0xfff : 0xff)
144 #define	VTU_PORT_UNMODIFIED		0
153 #define	VTU_VID_MASK			0xfff
157 #define	VTU_NOP				(0 << 12)
178 #define	ATU_PORT_MASK(_sc)		((MVSWITCH((_sc), MV88E6190) || MVSWITCH((_sc), MV88E6190X)) ? 0xfff0 : 0xff0)
180 #define	ATU_LAG_MASK                    0xf0
182 #define	ATU_STATE_MASK                  0xf
184 #define	ENTRY_STATE			0xf
188 #define	ATU_CONTROL_AGETIME_MASK	0xff0
193 #define	NO_OPERATION                    (0 << 12)
205 #define	COUNT_ALL			(0 << 0)
217 #define	MGMT_EN_ALL			0xffff
224 #define	SWITCH_MGMT_PRI			0
237 #define	SMI_CMD				0
245 #define	EEPROM_CMD			0x14
250 #define	 EEPROM_DATA_MASK		0xff
251 #define	EEPROM_ADDR			0x15
254 #define	SMI_PHY_CMD_REG			0x18
263 #define	 SMI_CMD_C45			(0 << 12)
264 #define	 SMI_CMD_C45_ADDR		(0 << 10)
274 #define	 SMI_CMD_DEV_ADDR_MASK		0x3e0
275 #define	 SMI_CMD_REG_ADDR_MASK		0x1f
276 #define	SMI_PHY_DATA_REG		0x19
277 #define	 PHY_DATA_MASK			0xffff
285 #define	SCR_AND_MISC_REG		0x1a
287 #define	SCR_AND_MISC_PTR_CFG		0x7000
288 #define	SCR_AND_MISC_DATA_CFG_MASK	0xf0
292 #define	E6000SW_SERDES_PCS_CTL1		0x1000
293 #define	E6000SW_SERDES_SGMII_CTL	0x2000