Searched +full:0 +full:x33900000 (Results 1 – 3 of 3) sorted by relevance
134 reg = <0x33800000 0x100000>,135 <0x18000000 0x8000000>,136 <0x33900000 0x100000>,137 <0x33b00000 0x100000>;
7 #define REG_PHYS_BASE 0xf00000008 #define REG_PHYS_BASE_V7 0x080000009 #define REG_VIRT_BASE 0xfc00000014 #define SUN_TOP_CTRL_BASE REG_PHYS_ADDR(0x404000)15 #define SUN_TOP_CTRL_BASE_V7 REG_PHYS_ADDR_V7(0x404000)17 #define UARTA_3390 REG_PHYS_ADDR(0x40a900)19 #define UARTA_7250 REG_PHYS_ADDR(0x40b400)20 #define UARTA_7255 REG_PHYS_ADDR(0x40c000)24 #define UARTA_7278 REG_PHYS_ADDR_V7(0x40c000)28 #define UARTA_7364 REG_PHYS_ADDR(0x40b000)[all …]
48 #size-cells = <0>;55 arm,psci-suspend-param = <0x0010033>;64 A53_0: cpu@0 {67 reg = <0x0>;71 i-cache-size = <0x8000>;74 d-cache-size = <0x8000>;88 reg = <0x1>;92 i-cache-size = <0x8000>;95 d-cache-size = <0x8000>;107 reg = <0x2>;[all …]