Lines Matching +full:0 +full:x33900000
7 #define REG_PHYS_BASE 0xf0000000
8 #define REG_PHYS_BASE_V7 0x08000000
9 #define REG_VIRT_BASE 0xfc000000
14 #define SUN_TOP_CTRL_BASE REG_PHYS_ADDR(0x404000)
15 #define SUN_TOP_CTRL_BASE_V7 REG_PHYS_ADDR_V7(0x404000)
17 #define UARTA_3390 REG_PHYS_ADDR(0x40a900)
19 #define UARTA_7250 REG_PHYS_ADDR(0x40b400)
20 #define UARTA_7255 REG_PHYS_ADDR(0x40c000)
24 #define UARTA_7278 REG_PHYS_ADDR_V7(0x40c000)
28 #define UARTA_7364 REG_PHYS_ADDR(0x40b000)
31 #define UARTA_74371 REG_PHYS_ADDR(0x406b00)
32 #define UARTA_7439 REG_PHYS_ADDR(0x40a900)
33 #define UARTA_7445 REG_PHYS_ADDR(0x40ab00)
56 mov \rv, #0 @ yes; record init is done
60 mrc p15, 0, \rv, c0, c0, 0 @ get Main ID register
68 mrc p15, 1, \rv, c15, c3, 0 @ get PERIPHBASE from CBAR
74 ldr \rv, [\rp, #0] @ get register contents
76 and \rv, \rv, #0xffffff00 @ strip revision bits [7:0]
79 20: checkuart(\rp, \rv, 0x33900000, 3390)
80 21: checkuart(\rp, \rv, 0x07211600, 72116)
81 22: checkuart(\rp, \rv, 0x72160000, 7216)
82 23: checkuart(\rp, \rv, 0x07216400, 72164)
83 24: checkuart(\rp, \rv, 0x07216500, 72165)
84 25: checkuart(\rp, \rv, 0x72500000, 7250)
85 26: checkuart(\rp, \rv, 0x72550000, 7255)
86 27: checkuart(\rp, \rv, 0x72600000, 7260)
87 28: checkuart(\rp, \rv, 0x72680000, 7268)
88 29: checkuart(\rp, \rv, 0x72710000, 7271)
89 30: checkuart(\rp, \rv, 0x72780000, 7278)
90 31: checkuart(\rp, \rv, 0x73640000, 7364)
91 32: checkuart(\rp, \rv, 0x73660000, 7366)
92 33: checkuart(\rp, \rv, 0x07416500, 74165)
93 34: checkuart(\rp, \rv, 0x07437100, 74371)
94 35: checkuart(\rp, \rv, 0x74390000, 7439)
95 36: checkuart(\rp, \rv, 0x74450000, 7445)
98 90: mov \rp, #0
103 cmp \rp, #0 @ Valid UART address?
105 str \rp, [\tmp, #8] @ Store 0 in brcmstb_uart_virt
107 92: and \rv, \rp, #0xffffff @ offset within 16MB section
171 .word 0
173 .word 0