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/linux/Documentation/devicetree/bindings/timer/
H A Drealtek,otto-timer.yaml18 pattern: "^timer@[0-9a-f]+$"
57 reg = <0x3200 0x10>, <0x3210 0x10>, <0x3220 0x10>,
58 <0x3230 0x10>, <0x3240 0x10>;
/linux/drivers/gpu/drm/radeon/reg_srcs/
H A Dr2001 r200 0x3294
2 0x1434 SRC_Y_X
3 0x1438 DST_Y_X
4 0x143C DST_HEIGHT_WIDTH
5 0x146C DP_GUI_MASTER_CNTL
6 0x1474 BRUSH_Y_X
7 0x1478 DP_BRUSH_BKGD_CLR
8 0x147C DP_BRUSH_FRGD_CLR
9 0x1480 BRUSH_DATA0
10 0x1484 BRUSH_DATA1
[all …]
/linux/drivers/media/rc/keymaps/
H A Drc-dreambox.c22 { 0x3200, KEY_POWER },
25 { 0x3290, KEY_HELP },
28 { 0x3201, KEY_1 },
29 { 0x3202, KEY_2 },
30 { 0x3203, KEY_3 },
31 { 0x3204, KEY_4 },
32 { 0x3205, KEY_5 },
33 { 0x3206, KEY_6 },
34 { 0x3207, KEY_7 },
35 { 0x3208, KEY_8 },
[all …]
/linux/arch/mips/boot/dts/realtek/
H A Drtl930x.dtsi16 #address-cells = <0>;
23 #size-cells = <0>;
25 cpu@0 {
28 reg = <0>;
35 #clock-cells = <0>;
41 #clock-cells = <0>;
47 reg = <0x1b000000 0x10000>;
57 reg = <0x0c 0x4>;
58 value = <0x01>;
63 reg = <0x36c 0x14>;
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/iccsense/
H A Dbase.c39 return nv_rd16i2cr(i2c, addr, 0x0) >= 0; in nvkm_iccsense_validate_device()
41 return nv_rd16i2cr(i2c, addr, 0xff) == 0x3220 && in nvkm_iccsense_validate_device()
42 nv_rd16i2cr(i2c, addr, 0xfe) == 0x5449; in nvkm_iccsense_validate_device()
56 if (vshunt < 0 || vbus < 0) in nvkm_iccsense_poll_lane()
71 shunt_reg, 0, bus_reg, 3, rail->mohm, in nvkm_iccsense_ina2x9_read()
104 nvkm_trace(subdev, "write config of extdev %i: 0x%04x\n", sensor->id, sensor->config); in nvkm_iccsense_sensor_config()
105 nv_wr16i2cr(sensor->i2c, sensor->addr, 0x00, sensor->config); in nvkm_iccsense_sensor_config()
111 int result = 0; in nvkm_iccsense_read_all()
123 if (res < 0) in nvkm_iccsense_read_all()
163 if (extdev.type == 0xff) in nvkm_iccsense_create_sensor()
[all …]
/linux/arch/powerpc/include/asm/
H A Dspu.h23 #define MFC_PUT_CMD 0x20
24 #define MFC_PUTS_CMD 0x28
25 #define MFC_PUTR_CMD 0x30
26 #define MFC_PUTF_CMD 0x22
27 #define MFC_PUTB_CMD 0x21
28 #define MFC_PUTFS_CMD 0x2A
29 #define MFC_PUTBS_CMD 0x29
30 #define MFC_PUTRF_CMD 0x32
31 #define MFC_PUTRB_CMD 0x31
32 #define MFC_PUTL_CMD 0x24
[all …]
/linux/drivers/net/ethernet/atheros/alx/
H A Dreg.h38 #define ALX_DEV_ID_AR8161 0x1091
39 #define ALX_DEV_ID_E2200 0xe091
40 #define ALX_DEV_ID_E2400 0xe0a1
41 #define ALX_DEV_ID_E2500 0xe0b1
42 #define ALX_DEV_ID_AR8162 0x1090
43 #define ALX_DEV_ID_AR8171 0x10A1
44 #define ALX_DEV_ID_AR8172 0x10A0
47 * bit(0): with xD support
52 #define ALX_REV_A0 0
57 #define ALX_DEV_CTRL 0x0060
[all …]
/linux/drivers/net/ethernet/atheros/atl1c/
H A Datl1c_hw.h57 #define PCI_DEVICE_ID_ATTANSIC_L2C 0x1062
58 #define PCI_DEVICE_ID_ATTANSIC_L1C 0x1063
59 #define PCI_DEVICE_ID_ATHEROS_L2C_B 0x2060 /* AR8152 v1.1 Fast 10/100 */
60 #define PCI_DEVICE_ID_ATHEROS_L2C_B2 0x2062 /* AR8152 v2.0 Fast 10/100 */
61 #define PCI_DEVICE_ID_ATHEROS_L1D 0x1073 /* AR8151 v1.0 Gigabit 1000 */
62 #define PCI_DEVICE_ID_ATHEROS_L1D_2_0 0x1083 /* AR8151 v2.0 Gigabit 1000 */
63 #define L2CB_V10 0xc0
64 #define L2CB_V11 0xc1
65 #define L2CB_V20 0xc0
66 #define L2CB_V21 0xc1
[all …]
/linux/drivers/phy/cadence/
H A Dphy-cadence-sierra.c30 #define SIERRA_COMMON_CDB_OFFSET 0x0
31 #define SIERRA_MACRO_ID_REG 0x0
32 #define SIERRA_CMN_PLLLC_GEN_PREG 0x42
33 #define SIERRA_CMN_PLLLC_FBDIV_INT_MODE0_PREG 0x43
34 #define SIERRA_CMN_PLLLC_DCOCAL_CTRL_PREG 0x45
35 #define SIERRA_CMN_PLLLC_INIT_PREG 0x46
36 #define SIERRA_CMN_PLLLC_ITERTMR_PREG 0x47
37 #define SIERRA_CMN_PLLLC_MODE_PREG 0x48
38 #define SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG 0x49
39 #define SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG 0x4A
[all …]
/linux/drivers/tty/vt/
H A Ducs_width_table.h_shipped7 * Unicode Version: 16.0.0
12 { 0x00AD, 0x00AD }, /* SOFT HYPHEN */
13 { 0x0300, 0x036F }, /* COMBINING GRAVE ACCENT - COMBINING LATIN SMALL LETTER X */
14 { 0x0483, 0x0489 }, /* COMBINING CYRILLIC TITLO - COMBINING CYRILLIC MILLIONS SIGN */
15 { 0x0591, 0x05BD }, /* HEBREW ACCENT ETNAHTA - HEBREW POINT METEG */
16 { 0x05BF, 0x05BF }, /* HEBREW POINT RAFE */
17 { 0x05C1, 0x05C2 }, /* HEBREW POINT SHIN DOT - HEBREW POINT SIN DOT */
18 { 0x05C4, 0x05C5 }, /* HEBREW MARK UPPER DOT - HEBREW MARK LOWER DOT */
19 { 0x05C7, 0x05C7 }, /* HEBREW POINT QAMATS QATAN */
20 { 0x0600, 0x0605 }, /* ARABIC NUMBER SIGN - ARABIC NUMBER MARK ABOVE */
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/dpcs/
H A Ddpcs_3_1_4_offset.h31 // base address: 0x0
32 …DPCSSYS_CR0_SUP_DIG_IDCODE_LO 0x0000
33 …DPCSSYS_CR0_SUP_DIG_IDCODE_HI 0x0001
34 …DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN 0x0002
35 …DPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN 0x0003
36 …DPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN 0x0004
37 …DPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN 0x0005
38 …DPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN 0x0006
39 …DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0 0x0007
40 …DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_1 0x0008
[all …]
H A Ddpcs_4_2_0_offset.h27 // base address: 0x0
28 …DPCSSYS_CR0_DPCSSYS_CR_ADDR 0x2934
30 …DPCSSYS_CR0_DPCSSYS_CR_DATA 0x2935
35 // base address: 0x360
36 …DPCSSYS_CR1_DPCSSYS_CR_ADDR 0x2a0c
38 …DPCSSYS_CR1_DPCSSYS_CR_DATA 0x2a0d
43 // base address: 0x6c0
44 …DPCSSYS_CR2_DPCSSYS_CR_ADDR 0x2ae4
46 …DPCSSYS_CR2_DPCSSYS_CR_DATA 0x2ae5
51 // base address: 0xa20
[all …]
H A Ddpcs_4_2_2_offset.h14 // base address: 0x0
15 …DPCSSYS_CR0_DPCSSYS_CR_ADDR 0x2934
17 …DPCSSYS_CR0_DPCSSYS_CR_DATA 0x2935
22 // base address: 0x360
23 …DPCSSYS_CR1_DPCSSYS_CR_ADDR 0x2a0c
25 …DPCSSYS_CR1_DPCSSYS_CR_DATA 0x2a0d
30 // base address: 0x6c0
31 …DPCSSYS_CR2_DPCSSYS_CR_ADDR 0x2ae4
33 …DPCSSYS_CR2_DPCSSYS_CR_DATA 0x2ae5
38 // base address: 0xa20
[all …]
H A Ddpcs_4_2_3_offset.h31 // base address: 0x0
32 …DPCSSYS_CR0_DPCSSYS_CR_ADDR 0x2934
34 …DPCSSYS_CR0_DPCSSYS_CR_DATA 0x2935
39 // base address: 0x360
40 …DPCSSYS_CR1_DPCSSYS_CR_ADDR 0x2a0c
42 …DPCSSYS_CR1_DPCSSYS_CR_DATA 0x2a0d
47 // base address: 0x6c0
48 …DPCSSYS_CR2_DPCSSYS_CR_ADDR 0x2ae4
50 …DPCSSYS_CR2_DPCSSYS_CR_DATA 0x2ae5
55 // base address: 0xa20
[all …]
/linux/drivers/pinctrl/tegra/
H A Dpinctrl-tegra114.c24 #define TEGRA_PIN_CLK_32K_OUT_PA0 _GPIO(0)
199 #define TEGRA_PIN_CORE_PWR_REQ _PIN(0)
1538 #define DRV_PINGROUP_REG_A 0x868 /* bank 0 */
1539 #define PINGROUP_REG_A 0x3000 /* bank 1 */
1560 .mux_bit = 0, \
1573 .parked_bitmask = 0, \
1592 .drv_bank = 0, \
1605 .parked_bitmask = 0, \
1610 …PINGROUP(ulpi_data0_po1, SPI3, HSI, UARTA, ULPI, 0x3000, N, N…
1611 …PINGROUP(ulpi_data1_po2, SPI3, HSI, UARTA, ULPI, 0x3004, N, N…
[all …]
H A Dpinctrl-tegra124.c24 #define TEGRA_PIN_CLK_32K_OUT_PA0 _GPIO(0)
213 #define TEGRA_PIN_CORE_PWR_REQ _PIN(0)
1705 #define DRV_PINGROUP_REG_A 0x868 /* bank 0 */
1706 #define PINGROUP_REG_A 0x3000 /* bank 1 */
1707 #define MIPI_PAD_CTRL_PINGROUP_REG_A 0x820 /* bank 2 */
1729 .mux_bit = 0, \
1742 .parked_bitmask = 0, \
1761 .drv_bank = 0, \
1774 .parked_bitmask = 0, \
1803 …PINGROUP(ulpi_data0_po1, SPI3, HSI, UARTA, ULPI, 0x3000, N, N…
[all …]
H A Dpinctrl-tegra210.c22 #define TEGRA_PIN_PEX_L0_RST_N_PA0 _GPIO(0)
182 #define TEGRA_PIN_CORE_PWR_REQ _PIN(0)
1266 #define DRV_PINGROUP_REG_A 0x8d4 /* bank 0 */
1267 #define PINGROUP_REG_A 0x3000 /* bank 1 */
1290 .mux_bit = 0, \
1306 .drv_bank = 0, \
1335 .drv_bank = 0, \
1354 …PINGROUP(sdmmc1_clk_pm0, SDMMC1, RSVD1, RSVD2, RSVD3, 0x3000, Y, Y, N, N,…
1355 …PINGROUP(sdmmc1_cmd_pm1, SDMMC1, SPI3, RSVD2, RSVD3, 0x3004, Y, Y, N, N,…
1356 …PINGROUP(sdmmc1_dat3_pm2, SDMMC1, SPI3, RSVD2, RSVD3, 0x3008, Y, Y, N, N,…
[all …]
H A Dpinctrl-tegra30.c24 #define TEGRA_PIN_CLK_32K_OUT_PA0 _GPIO(0)
278 #define TEGRA_PIN_CLK_32K_IN _PIN(0)
2099 #define DRV_PINGROUP_REG_A 0x868 /* bank 0 */
2100 #define PINGROUP_REG_A 0x3000 /* bank 1 */
2121 .mux_bit = 0, \
2134 .parked_bitmask = 0, \
2153 .drv_bank = 0, \
2166 .parked_bitmask = 0, \
2171 …PINGROUP(clk_32k_out_pa0, BLINK, RSVD2, RSVD3, RSVD4, 0x331c, N, …
2172 …PINGROUP(uart3_cts_n_pa1, UARTC, RSVD2, GMI, RSVD4, 0x317c, N, …
[all …]
/linux/drivers/scsi/
H A Dhptiop.c48 u32 req = 0; in iop_wait_ready_itl()
51 for (i = 0; i < millisec; i++) { in iop_wait_ready_itl()
61 return 0; in iop_wait_ready_itl()
118 int ret = 0; in iop_intr_itl()
120 if (plx && readl(plx + 0x11C5C) & 0xf) in iop_intr_itl()
121 writel(1, plx + 0x11C60); in iop_intr_itl()
154 outbound_tail = 0; in mv_outbound_read()
158 return 0; in mv_outbound_read()
167 head = 0; in mv_inbound_write()
177 u32 req_type = (tag >> 5) & 0x7; in hptiop_request_callback_mv()
[all …]
/linux/include/linux/
H A Dpci_ids.h15 #define PCI_CLASS_NOT_DEFINED 0x0000
16 #define PCI_CLASS_NOT_DEFINED_VGA 0x0001
18 #define PCI_BASE_CLASS_STORAGE 0x01
19 #define PCI_CLASS_STORAGE_SCSI 0x0100
20 #define PCI_CLASS_STORAGE_IDE 0x0101
21 #define PCI_CLASS_STORAGE_FLOPPY 0x0102
22 #define PCI_CLASS_STORAGE_IPI 0x0103
23 #define PCI_CLASS_STORAGE_RAID 0x0104
24 #define PCI_CLASS_STORAGE_SATA 0x0106
25 #define PCI_CLASS_STORAGE_SATA_AHCI 0x010601
[all …]
/linux/drivers/net/wireless/atmel/
H A Dat76c50x-usb.c51 #define DBG_PROGRESS 0x00000001 /* authentication/accociation */
52 #define DBG_BSS_TABLE 0x00000002 /* show BSS table after scans */
53 #define DBG_IOCTL 0x00000004 /* ioctl calls / settings */
54 #define DBG_MAC_STATE 0x00000008 /* MAC state transitions */
55 #define DBG_TX_DATA 0x00000010 /* tx header */
56 #define DBG_TX_DATA_CONTENT 0x00000020 /* tx content */
57 #define DBG_TX_MGMT 0x00000040 /* tx management */
58 #define DBG_RX_DATA 0x00000080 /* rx data header */
59 #define DBG_RX_DATA_CONTENT 0x00000100 /* rx data content */
60 #define DBG_RX_MGMT 0x00000200 /* rx mgmt frame headers */
[all …]
/linux/sound/soc/mediatek/mt8195/
H A Dmt8195-reg.h13 #define AFE_SRAM_BASE (0x10880000)
14 #define AFE_SRAM_SIZE (0x10000)
16 #define AUDIO_TOP_CON0 (0x0000)
17 #define AUDIO_TOP_CON1 (0x0004)
18 #define AUDIO_TOP_CON2 (0x0008)
19 #define AUDIO_TOP_CON3 (0x000c)
20 #define AUDIO_TOP_CON4 (0x0010)
21 #define AUDIO_TOP_CON5 (0x0014)
22 #define AUDIO_TOP_CON6 (0x0018)
23 #define AFE_MAS_HADDR_MSB (0x0020)
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_1_0_offset.h27 // base address: 0x48
28 …VGA_MEM_WRITE_PAGE_ADDR 0x0000
29 …ne mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0
30 …VGA_MEM_READ_PAGE_ADDR 0x0001
31 …ne mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX 0
35 // base address: 0x3b4
36 …CRTC8_IDX 0x002d
38 …CRTC8_DATA 0x002d
40 …GENFC_WT 0x002e
42 …GENS1 0x002e
[all …]
H A Ddcn_3_0_0_offset.h8 // base address: 0x0
9 …VGA_MEM_WRITE_PAGE_ADDR 0x0000
10 …VGA_MEM_WRITE_PAGE_ADDR 0x0000
11 …ne mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0
12 …VGA_MEM_READ_PAGE_ADDR 0x0001
13 …ne mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX 0
14 …VGA_RENDER_CONTROL 0x0000
16 …VGA_SEQUENCER_RESET_CONTROL 0x0001
18 …VGA_MODE_CONTROL 0x0002
20 …VGA_SURFACE_PITCH_SELECT 0x0003
[all …]
H A Ddcn_2_0_0_offset.h27 // base address: 0x0
28 …VGA_MEM_WRITE_PAGE_ADDR 0x0000
29 …ne mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0
30 …VGA_MEM_READ_PAGE_ADDR 0x0001
31 …ne mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX 0
32 …VGA_RENDER_CONTROL 0x0000
34 …VGA_SEQUENCER_RESET_CONTROL 0x0001
36 …VGA_MODE_CONTROL 0x0002
38 …VGA_SURFACE_PITCH_SELECT 0x0003
40 …VGA_MEMORY_BASE_ADDRESS 0x0004
[all …]

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