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/linux/Documentation/devicetree/bindings/timer/
H A Drealtek,otto-timer.yaml18 pattern: "^timer@[0-9a-f]+$"
57 reg = <0x3200 0x10>, <0x3210 0x10>, <0x3220 0x10>,
58 <0x3230 0x10>, <0x3240 0x10>;
/linux/drivers/net/ethernet/mellanox/mlxbf_gige/
H A Dmlxbf_gige_regs.h13 #define MLXBF_GIGE_VERSION 0x0000
14 #define MLXBF_GIGE_VERSION_BF2 0x0
15 #define MLXBF_GIGE_VERSION_BF3 0x1
16 #define MLXBF_GIGE_STATUS 0x0010
17 #define MLXBF_GIGE_STATUS_READY BIT(0)
18 #define MLXBF_GIGE_INT_STATUS 0x0028
19 #define MLXBF_GIGE_INT_STATUS_RX_RECEIVE_PACKET BIT(0)
28 #define MLXBF_GIGE_INT_EN 0x0030
29 #define MLXBF_GIGE_INT_EN_RX_RECEIVE_PACKET BIT(0)
38 #define MLXBF_GIGE_INT_MASK 0x0038
[all …]
/linux/drivers/media/rc/keymaps/
H A Drc-dreambox.c22 { 0x3200, KEY_POWER },
25 { 0x3290, KEY_HELP },
28 { 0x3201, KEY_1 },
29 { 0x3202, KEY_2 },
30 { 0x3203, KEY_3 },
31 { 0x3204, KEY_4 },
32 { 0x3205, KEY_5 },
33 { 0x3206, KEY_6 },
34 { 0x3207, KEY_7 },
35 { 0x3208, KEY_8 },
[all …]
/linux/drivers/gpu/drm/omapdrm/dss/
H A Dhdmi_phy.c36 for (i = 0; i < 8; i += 2) { in hdmi_phy_parse_lanes()
43 if (dx < 0 || dx >= 8) in hdmi_phy_parse_lanes()
46 if (dy < 0 || dy >= 8) in hdmi_phy_parse_lanes()
56 pol = 0; in hdmi_phy_parse_lanes()
65 return 0; in hdmi_phy_parse_lanes()
71 0x0123, in hdmi_phy_configure_lanes()
72 0x0132, in hdmi_phy_configure_lanes()
73 0x0312, in hdmi_phy_configure_lanes()
74 0x0321, in hdmi_phy_configure_lanes()
75 0x0231, in hdmi_phy_configure_lanes()
[all …]
/linux/drivers/video/fbdev/omap2/omapfb/dss/
H A Dhdmi_phy.c45 for (i = 0; i < 8; i += 2) { in hdmi_phy_parse_lanes()
52 if (dx < 0 || dx >= 8) in hdmi_phy_parse_lanes()
55 if (dy < 0 || dy >= 8) in hdmi_phy_parse_lanes()
65 pol = 0; in hdmi_phy_parse_lanes()
74 return 0; in hdmi_phy_parse_lanes()
80 0x0123, in hdmi_phy_configure_lanes()
81 0x0132, in hdmi_phy_configure_lanes()
82 0x0312, in hdmi_phy_configure_lanes()
83 0x0321, in hdmi_phy_configure_lanes()
84 0x0231, in hdmi_phy_configure_lanes()
[all …]
/linux/arch/mips/boot/dts/realtek/
H A Drtl930x.dtsi16 #address-cells = <0>;
23 #size-cells = <0>;
25 cpu@0 {
28 reg = <0>;
35 #clock-cells = <0>;
41 #clock-cells = <0>;
47 reg = <0x1b000000 0x10000>;
57 reg = <0x0c 0x4>;
58 value = <0x01>;
63 reg = <0x36c 0x14>;
[all …]
/linux/drivers/net/fddi/skfp/h/
H A Dsmt_p.h19 #define SMT_P0012 0x0012
21 #define SMT_P0015 0x0015
22 #define SMT_P0016 0x0016
23 #define SMT_P0017 0x0017
24 #define SMT_P0018 0x0018
25 #define SMT_P0019 0x0019
27 #define SMT_P001A 0x001a
28 #define SMT_P001B 0x001b
29 #define SMT_P001C 0x001c
30 #define SMT_P001D 0x001d
[all …]
/linux/drivers/net/ethernet/chelsio/cxgb/
H A Dpm3393.c45 #define RXXG_CONF1_VAL (SUNI1x10GEXP_BITMSK_RXXG_PUREP | 0x14 | \
88 return 0; in pmread()
94 return 0; in pmwrite()
100 return 0; in pm3393_reset()
117 pmwrite(cmac, SUNI1x10GEXP_REG_SERDES_3125_INTERRUPT_ENABLE, 0xffff); in pm3393_interrupt_enable()
118 pmwrite(cmac, SUNI1x10GEXP_REG_XRF_INTERRUPT_ENABLE, 0xffff); in pm3393_interrupt_enable()
119 pmwrite(cmac, SUNI1x10GEXP_REG_XRF_DIAG_INTERRUPT_ENABLE, 0xffff); in pm3393_interrupt_enable()
120 pmwrite(cmac, SUNI1x10GEXP_REG_RXOAM_INTERRUPT_ENABLE, 0xffff); in pm3393_interrupt_enable()
123 pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_0, 0); in pm3393_interrupt_enable()
124 pmwrite(cmac, SUNI1x10GEXP_REG_MSTAT_INTERRUPT_MASK_1, 0); in pm3393_interrupt_enable()
[all …]
H A Dsuni1x10gexp_regs.h29 #define SUNI1x10GEXP_REG_SIZEOF_MAC_FILTER 0x0003
37 #define SUNI1x10GEXP_REG_SIZEOF_MAC_VID_FILTER 0x0001
44 #define SUNI1x10GEXP_REG_SIZEOF_MSTAT_COUNT 0x0004
57 #define SUNI1x10GEXP_REG_IDENTIFICATION 0x0000
58 #define SUNI1x10GEXP_REG_PRODUCT_REVISION 0x0001
59 #define SUNI1x10GEXP_REG_CONFIG_AND_RESET_CONTROL 0x0002
60 #define SUNI1x10GEXP_REG_LOOPBACK_MISC_CTRL 0x0003
61 #define SUNI1x10GEXP_REG_DEVICE_STATUS 0x0004
62 #define SUNI1x10GEXP_REG_GLOBAL_PERFORMANCE_MONITOR_UPDATE 0x0005
64 #define SUNI1x10GEXP_REG_MDIO_COMMAND 0x0006
[all …]
/linux/drivers/net/ethernet/atheros/alx/
H A Dreg.h38 #define ALX_DEV_ID_AR8161 0x1091
39 #define ALX_DEV_ID_E2200 0xe091
40 #define ALX_DEV_ID_E2400 0xe0a1
41 #define ALX_DEV_ID_E2500 0xe0b1
42 #define ALX_DEV_ID_AR8162 0x1090
43 #define ALX_DEV_ID_AR8171 0x10A1
44 #define ALX_DEV_ID_AR8172 0x10A0
47 * bit(0): with xD support
52 #define ALX_REV_A0 0
57 #define ALX_DEV_CTRL 0x0060
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/dpcs/
H A Ddpcs_3_1_4_offset.h31 // base address: 0x0
32 …DPCSSYS_CR0_SUP_DIG_IDCODE_LO 0x0000
33 …DPCSSYS_CR0_SUP_DIG_IDCODE_HI 0x0001
34 …DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN 0x0002
35 …DPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN 0x0003
36 …DPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN 0x0004
37 …DPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN 0x0005
38 …DPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN 0x0006
39 …DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0 0x0007
40 …DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_1 0x0008
[all …]
H A Ddpcs_4_2_0_offset.h27 // base address: 0x0
28 …DPCSSYS_CR0_DPCSSYS_CR_ADDR 0x2934
30 …DPCSSYS_CR0_DPCSSYS_CR_DATA 0x2935
35 // base address: 0x360
36 …DPCSSYS_CR1_DPCSSYS_CR_ADDR 0x2a0c
38 …DPCSSYS_CR1_DPCSSYS_CR_DATA 0x2a0d
43 // base address: 0x6c0
44 …DPCSSYS_CR2_DPCSSYS_CR_ADDR 0x2ae4
46 …DPCSSYS_CR2_DPCSSYS_CR_DATA 0x2ae5
51 // base address: 0xa20
[all …]
H A Ddpcs_4_2_2_offset.h14 // base address: 0x0
15 …DPCSSYS_CR0_DPCSSYS_CR_ADDR 0x2934
17 …DPCSSYS_CR0_DPCSSYS_CR_DATA 0x2935
22 // base address: 0x360
23 …DPCSSYS_CR1_DPCSSYS_CR_ADDR 0x2a0c
25 …DPCSSYS_CR1_DPCSSYS_CR_DATA 0x2a0d
30 // base address: 0x6c0
31 …DPCSSYS_CR2_DPCSSYS_CR_ADDR 0x2ae4
33 …DPCSSYS_CR2_DPCSSYS_CR_DATA 0x2ae5
38 // base address: 0xa20
[all …]
H A Ddpcs_4_2_3_offset.h31 // base address: 0x0
32 …DPCSSYS_CR0_DPCSSYS_CR_ADDR 0x2934
34 …DPCSSYS_CR0_DPCSSYS_CR_DATA 0x2935
39 // base address: 0x360
40 …DPCSSYS_CR1_DPCSSYS_CR_ADDR 0x2a0c
42 …DPCSSYS_CR1_DPCSSYS_CR_DATA 0x2a0d
47 // base address: 0x6c0
48 …DPCSSYS_CR2_DPCSSYS_CR_ADDR 0x2ae4
50 …DPCSSYS_CR2_DPCSSYS_CR_DATA 0x2ae5
55 // base address: 0xa20
[all …]
/linux/drivers/pinctrl/tegra/
H A Dpinctrl-tegra114.c24 #define TEGRA_PIN_CLK_32K_OUT_PA0 _GPIO(0)
199 #define TEGRA_PIN_CORE_PWR_REQ _PIN(0)
1538 #define DRV_PINGROUP_REG_A 0x868 /* bank 0 */
1539 #define PINGROUP_REG_A 0x3000 /* bank 1 */
1560 .mux_bit = 0, \
1573 .parked_bitmask = 0, \
1592 .drv_bank = 0, \
1605 .parked_bitmask = 0, \
1610 …PINGROUP(ulpi_data0_po1, SPI3, HSI, UARTA, ULPI, 0x3000, N, N…
1611 …PINGROUP(ulpi_data1_po2, SPI3, HSI, UARTA, ULPI, 0x3004, N, N…
[all …]
H A Dpinctrl-tegra124.c24 #define TEGRA_PIN_CLK_32K_OUT_PA0 _GPIO(0)
213 #define TEGRA_PIN_CORE_PWR_REQ _PIN(0)
1705 #define DRV_PINGROUP_REG_A 0x868 /* bank 0 */
1706 #define PINGROUP_REG_A 0x3000 /* bank 1 */
1707 #define MIPI_PAD_CTRL_PINGROUP_REG_A 0x820 /* bank 2 */
1729 .mux_bit = 0, \
1742 .parked_bitmask = 0, \
1761 .drv_bank = 0, \
1774 .parked_bitmask = 0, \
1803 …PINGROUP(ulpi_data0_po1, SPI3, HSI, UARTA, ULPI, 0x3000, N, N…
[all …]
H A Dpinctrl-tegra210.c22 #define TEGRA_PIN_PEX_L0_RST_N_PA0 _GPIO(0)
182 #define TEGRA_PIN_CORE_PWR_REQ _PIN(0)
1266 #define DRV_PINGROUP_REG_A 0x8d4 /* bank 0 */
1267 #define PINGROUP_REG_A 0x3000 /* bank 1 */
1290 .mux_bit = 0, \
1306 .drv_bank = 0, \
1335 .drv_bank = 0, \
1354 …PINGROUP(sdmmc1_clk_pm0, SDMMC1, RSVD1, RSVD2, RSVD3, 0x3000, Y, Y, N, N,…
1355 …PINGROUP(sdmmc1_cmd_pm1, SDMMC1, SPI3, RSVD2, RSVD3, 0x3004, Y, Y, N, N,…
1356 …PINGROUP(sdmmc1_dat3_pm2, SDMMC1, SPI3, RSVD2, RSVD3, 0x3008, Y, Y, N, N,…
[all …]
H A Dpinctrl-tegra30.c24 #define TEGRA_PIN_CLK_32K_OUT_PA0 _GPIO(0)
278 #define TEGRA_PIN_CLK_32K_IN _PIN(0)
2099 #define DRV_PINGROUP_REG_A 0x868 /* bank 0 */
2100 #define PINGROUP_REG_A 0x3000 /* bank 1 */
2121 .mux_bit = 0, \
2134 .parked_bitmask = 0, \
2153 .drv_bank = 0, \
2166 .parked_bitmask = 0, \
2171 …PINGROUP(clk_32k_out_pa0, BLINK, RSVD2, RSVD3, RSVD4, 0x331c, N, …
2172 …PINGROUP(uart3_cts_n_pa1, UARTC, RSVD2, GMI, RSVD4, 0x317c, N, …
[all …]
/linux/sound/soc/mediatek/mt8195/
H A Dmt8195-reg.h13 #define AFE_SRAM_BASE (0x10880000)
14 #define AFE_SRAM_SIZE (0x10000)
16 #define AUDIO_TOP_CON0 (0x0000)
17 #define AUDIO_TOP_CON1 (0x0004)
18 #define AUDIO_TOP_CON2 (0x0008)
19 #define AUDIO_TOP_CON3 (0x000c)
20 #define AUDIO_TOP_CON4 (0x0010)
21 #define AUDIO_TOP_CON5 (0x0014)
22 #define AUDIO_TOP_CON6 (0x0018)
23 #define AFE_MAS_HADDR_MSB (0x0020)
[all …]
/linux/drivers/clk/qcom/
H A Dgcc-ipq806x.c33 .l_reg = 0x30c4,
34 .m_reg = 0x30c8,
35 .n_reg = 0x30cc,
36 .config_reg = 0x30d4,
37 .mode_reg = 0x30c0,
38 .status_reg = 0x30d8,
49 .enable_reg = 0x34c0,
50 .enable_mask = BIT(0),
62 .l_reg = 0x3164,
63 .m_reg = 0x3168,
[all …]
/linux/drivers/net/wireless/ath/ath9k/
H A Dhw.c83 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) { in ath9k_hw_wait()
91 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n", in ath9k_hw_wait()
117 for (r = 0; r < array->ia_rows; r++) { in ath9k_hw_write_array()
118 REG_WRITE(ah, INI_RA(array, r, 0), in ath9k_hw_write_array()
142 for (i = 0; i < size; i++) in ath9k_hw_read_array()
143 tmp_reg_list[i] = array[i][0]; in ath9k_hw_read_array()
147 for (i = 0; i < size; i++) in ath9k_hw_read_array()
160 for (i = 0, retval = 0; i < n; i++) { in ath9k_hw_reverse_bits()
174 if (kbps == 0) in ath9k_hw_computetxtime()
175 return 0; in ath9k_hw_computetxtime()
[all …]
/linux/lib/
H A Dtest_bpf.c26 #define MAX_K 0xffffFFFF
30 #define SKB_MARK 0x1234aaaa
31 #define SKB_HASH 0x1234aaab
33 #define SKB_VLAN_TCI 0xffff
52 #define FLAG_NO_DATA BIT(0)
85 int nr_testruns; /* Custom run count, defaults to MAX_TESTRUNS if 0 */
94 __u32 k = ~0; in bpf_fill_maxinsns1()
101 for (i = 0; i < len; i++, k--) in bpf_fill_maxinsns1()
107 return 0; in bpf_fill_maxinsns1()
120 for (i = 0; i < len; i++) in bpf_fill_maxinsns2()
[all …]
/linux/fs/nls/
H A Dnls_cp949.c17 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x00-0x07 */
18 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x08-0x0F */
19 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x10-0x17 */
20 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x18-0x1F */
21 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x20-0x27 */
22 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x28-0x2F */
23 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x30-0x37 */
24 0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,/* 0x38-0x3F */
25 0x0000,0xAC02,0xAC03,0xAC05,0xAC06,0xAC0B,0xAC0C,0xAC0D,/* 0x40-0x47 */
26 0xAC0E,0xAC0F,0xAC18,0xAC1E,0xAC1F,0xAC21,0xAC22,0xAC23,/* 0x48-0x4F */
[all …]
/linux/drivers/net/wireless/realtek/rtw89/
H A Drtw8852c_table.c10 {0xF0FF0000, 0x00000000},
11 {0xF03300FF, 0x00000001},
12 {0xF03400FF, 0x00000002},
13 {0xF03500FF, 0x00000003},
14 {0xF03600FF, 0x00000004},
15 {0x70C, 0x00000020},
16 {0x704, 0x601E0100},
17 {0x4000, 0x00000000},
18 {0x4004, 0xCA014000},
19 {0x4008, 0xC751D4F0},
[all …]