Lines Matching +full:0 +full:x3210
83 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) { in ath9k_hw_wait()
91 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n", in ath9k_hw_wait()
117 for (r = 0; r < array->ia_rows; r++) { in ath9k_hw_write_array()
118 REG_WRITE(ah, INI_RA(array, r, 0), in ath9k_hw_write_array()
142 for (i = 0; i < size; i++) in ath9k_hw_read_array()
143 tmp_reg_list[i] = array[i][0]; in ath9k_hw_read_array()
147 for (i = 0; i < size; i++) in ath9k_hw_read_array()
160 for (i = 0, retval = 0; i < n; i++) { in ath9k_hw_reverse_bits()
174 if (kbps == 0) in ath9k_hw_computetxtime()
175 return 0; in ath9k_hw_computetxtime()
214 txTime = 0; in ath9k_hw_computetxtime()
298 if (val == 0xFF) { in ath9k_hw_read_revisions()
308 AR_SREV_TYPE2_HOST_MODE) ? 0 : 1; in ath9k_hw_read_revisions()
331 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); in ath9k_hw_disablepcie()
332 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); in ath9k_hw_disablepcie()
333 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029); in ath9k_hw_disablepcie()
334 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824); in ath9k_hw_disablepcie()
335 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579); in ath9k_hw_disablepcie()
336 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000); in ath9k_hw_disablepcie()
337 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); in ath9k_hw_disablepcie()
338 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); in ath9k_hw_disablepcie()
339 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007); in ath9k_hw_disablepcie()
341 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); in ath9k_hw_disablepcie()
351 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999 in ath9k_hw_chip_test()
361 for (i = 0; i < loop_max; i++) { in ath9k_hw_chip_test()
366 for (j = 0; j < 0x100; j++) { in ath9k_hw_chip_test()
372 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", in ath9k_hw_chip_test()
377 for (j = 0; j < 4; j++) { in ath9k_hw_chip_test()
383 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", in ath9k_hw_chip_test()
463 ah->hw_version.subvendorid = 0; in ath9k_hw_init_defaults()
498 for (i = 0; i < 3; i++) { in ath9k_hw_init_macaddr()
501 common->macaddr[2 * i + 1] = eeval & 0xff; in ath9k_hw_init_macaddr()
529 if (ecode != 0) in ath9k_hw_post_init()
534 if (ecode != 0) in ath9k_hw_post_init()
549 if ((regdmn & 0xF0) == CTL_FCC) { in ath9k_hw_post_init()
555 return 0; in ath9k_hw_post_init()
564 return 0; in ath9k_hw_attach_ops()
571 int r = 0; in __ath9k_hw_init()
599 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n", in __ath9k_hw_init()
661 return 0; in __ath9k_hw_init()
696 ath_err(common, "Hardware device ID 0x%04x not supported\n", in ath9k_hw_init()
711 return 0; in ath9k_hw_init()
719 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa); in ath9k_hw_init_qos()
720 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210); in ath9k_hw_init_qos()
725 SM(0, AR_QOS_NO_ACK_BYTE_OFF)); in ath9k_hw_init_qos()
728 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF); in ath9k_hw_init_qos()
729 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF); in ath9k_hw_init_qos()
730 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF); in ath9k_hw_init_qos()
731 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF); in ath9k_hw_init_qos()
739 int i = 0; in ar9003_get_pll_sqsum_dvc()
745 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) { in ar9003_get_pll_sqsum_dvc()
769 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */ in ath9k_hw_init_pll()
771 AR_CH0_BB_DPLL2_PLL_PWD, 0x1); in ath9k_hw_init_pll()
773 AR_CH0_DPLL2_KD, 0x40); in ath9k_hw_init_pll()
775 AR_CH0_DPLL2_KI, 0x4); in ath9k_hw_init_pll()
778 AR_CH0_BB_DPLL1_REFDIV, 0x5); in ath9k_hw_init_pll()
780 AR_CH0_BB_DPLL1_NINI, 0x58); in ath9k_hw_init_pll()
782 AR_CH0_BB_DPLL1_NFRAC, 0x0); in ath9k_hw_init_pll()
785 AR_CH0_BB_DPLL2_OUTDIV, 0x1); in ath9k_hw_init_pll()
787 AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1); in ath9k_hw_init_pll()
789 AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1); in ath9k_hw_init_pll()
791 /* program BB PLL phase_shift to 0x6 */ in ath9k_hw_init_pll()
793 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6); in ath9k_hw_init_pll()
796 AR_CH0_BB_DPLL2_PLL_PWD, 0x0); in ath9k_hw_init_pll()
802 ddr_dpll2 = 0x18e82f01; in ath9k_hw_init_pll()
803 pll_control2 = 0xe04a3d; in ath9k_hw_init_pll()
804 kd = 0x1d; in ath9k_hw_init_pll()
806 ddr_dpll2 = 0x19e82f01; in ath9k_hw_init_pll()
807 pll_control2 = 0x886666; in ath9k_hw_init_pll()
808 kd = 0x3d; in ath9k_hw_init_pll()
816 AR_CH0_DPLL3_PHASE_SHIFT, 0x1); in ath9k_hw_init_pll()
827 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06); in ath9k_hw_init_pll()
831 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1); in ath9k_hw_init_pll()
840 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16); in ath9k_hw_init_pll()
845 pll2_divint = 0x1c; in ath9k_hw_init_pll()
846 pll2_divfrac = 0xa3d2; in ath9k_hw_init_pll()
849 pll2_divint = 0x54; in ath9k_hw_init_pll()
850 pll2_divfrac = 0x1eb85; in ath9k_hw_init_pll()
856 pll2_divfrac = 0; in ath9k_hw_init_pll()
859 pll2_divint = 0x11; in ath9k_hw_init_pll()
862 0x26665 : 0x26666; in ath9k_hw_init_pll()
869 regval |= (0x1 << 22); in ath9k_hw_init_pll()
871 regval |= (0x1 << 16); in ath9k_hw_init_pll()
881 regval = (regval & 0x80071fff) | in ath9k_hw_init_pll()
882 (0x1 << 30) | in ath9k_hw_init_pll()
883 (0x1 << 13) | in ath9k_hw_init_pll()
884 (0x4 << 26) | in ath9k_hw_init_pll()
885 (0x18 << 19); in ath9k_hw_init_pll()
887 regval = (regval & 0x01c00fff) | in ath9k_hw_init_pll()
888 (0x1 << 31) | in ath9k_hw_init_pll()
889 (0x2 << 29) | in ath9k_hw_init_pll()
890 (0xa << 25) | in ath9k_hw_init_pll()
891 (0x1 << 19); in ath9k_hw_init_pll()
894 regval |= (0x6 << 12); in ath9k_hw_init_pll()
896 regval = (regval & 0x80071fff) | in ath9k_hw_init_pll()
897 (0x3 << 30) | in ath9k_hw_init_pll()
898 (0x1 << 13) | in ath9k_hw_init_pll()
899 (0x4 << 26) | in ath9k_hw_init_pll()
900 (0x60 << 19); in ath9k_hw_init_pll()
905 REG_READ(ah, AR_PHY_PLL_MODE) & 0xffbfffff); in ath9k_hw_init_pll()
908 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff); in ath9k_hw_init_pll()
914 pll |= 0x40000; in ath9k_hw_init_pll()
924 REG_WRITE(ah, 0x50040, 0x304); in ath9k_hw_init_pll()
941 u32 msi_cfg = 0; in ath9k_hw_init_interrupt_masks()
986 "value of AR_INTCFG=0x%X, msi_cfg=0x%X\n", in ath9k_hw_init_interrupt_masks()
991 REG_WRITE(ah, AR_INTR_SYNC_CAUSE(ah), 0xFFFFFFFF); in ath9k_hw_init_interrupt_masks()
993 REG_WRITE(ah, AR_INTR_SYNC_MASK(ah), 0); in ath9k_hw_init_interrupt_masks()
999 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE(ah), 0); in ath9k_hw_init_interrupt_masks()
1000 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK(ah), 0); in ath9k_hw_init_interrupt_masks()
1001 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE(ah), 0); in ath9k_hw_init_interrupt_masks()
1002 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK(ah), 0); in ath9k_hw_init_interrupt_masks()
1009 val = min(val, (u32) 0xFFFF); in ath9k_hw_set_sifs_time()
1016 val = min(val, (u32) 0xFFFF); in ath9k_hw_setslottime()
1023 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK)); in ath9k_hw_set_ack_timeout()
1030 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS)); in ath9k_hw_set_cts_timeout()
1036 if (tu > 0xFFFF) { in ath9k_hw_set_global_txtimeout()
1052 int acktimeout, ctstimeout, ack_offset = 0; in ath9k_hw_init_global_settings()
1055 int rx_lat = 0, tx_lat = 0, eifs = 0, ack_shift = 0; in ath9k_hw_init_global_settings()
1058 ath_dbg(ath9k_hw_common(ah), RESET, "ah->misc_mode 0x%x\n", in ath9k_hw_init_global_settings()
1064 if (ah->misc_mode != 0) in ath9k_hw_init_global_settings()
1231 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200); in ath9k_hw_set_dma()
1234 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1); in ath9k_hw_set_dma()
1235 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1); in ath9k_hw_set_dma()
1291 set = 0; in ath9k_hw_set_operating_mode()
1303 for (coef_exp = 31; coef_exp > 0; coef_exp--) in ath9k_hw_get_delta_slope_vals()
1304 if ((coef_scaled >> coef_exp) & 0x1) in ath9k_hw_get_delta_slope_vals()
1322 int i, npend = 0; in ath9k_hw_ar9330_reset_war()
1324 for (i = 0; i < AR_NUM_QCU; i++) { in ath9k_hw_ar9330_reset_war()
1332 int reset_err = 0; in ath9k_hw_ar9330_reset_war()
1385 REG_WRITE(ah, AR_INTR_SYNC_ENABLE(ah), 0); in ath9k_hw_set_reset()
1429 REG_WRITE(ah, AR_RTC_RC(ah), 0); in ath9k_hw_set_reset()
1430 if (!ath9k_hw_wait(ah, AR_RTC_RC(ah), AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) { in ath9k_hw_set_reset()
1436 REG_WRITE(ah, AR_RC, 0); in ath9k_hw_set_reset()
1459 REG_WRITE(ah, AR_RTC_RESET(ah), 0); in ath9k_hw_set_reset_power_on()
1466 REG_WRITE(ah, AR_RC, 0); in ath9k_hw_set_reset_power_on()
1549 u8 ini_reloaded = 0; in ath9k_hw_channel_change()
1559 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) { in ath9k_hw_channel_change()
1618 for (i = 0; gpio_mask; i++, gpio_mask >>= 1) { in ath9k_hw_apply_gpio_override()
1634 if (val != 0xdeadbeef && val > 0x7fff) { in ath9k_hw_check_nav()
1635 ath_dbg(common, BSTUCK, "Abnormal NAV: 0x%x\n", val); in ath9k_hw_check_nav()
1636 REG_WRITE(ah, AR_NAV, 0); in ath9k_hw_check_nav()
1647 if (REG_READ(ah, AR_CFG) == 0xdeadbeef) in ath9k_hw_check_alive()
1664 if ((reg & 0x7E7FFFEF) == 0x00702400) in ath9k_hw_check_alive()
1667 switch (reg & 0x7E000B00) { in ath9k_hw_check_alive()
1668 case 0x1E000000: in ath9k_hw_check_alive()
1669 case 0x52000B00: in ath9k_hw_check_alive()
1670 case 0x18000B00: in ath9k_hw_check_alive()
1675 } while (count-- > 0); in ath9k_hw_check_alive()
1685 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt in ath9k_hw_init_mfp()
1688 0xc7ff); in ath9k_hw_init_mfp()
1722 REG_WRITE(ah, AR_ISR, ~0); in ath9k_hw_reset_opmode()
1736 for (i = 0; i < AR_NUM_DCU; i++) in ath9k_hw_init_queues()
1741 ah->intr_txqs = 0; in ath9k_hw_init_queues()
1742 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) in ath9k_hw_init_queues()
1757 ath_dbg(common, RESET, "CFG Byte Swap Set 0x%x\n", in ath9k_hw_init_desc()
1762 ath_dbg(common, RESET, "Setting CFG 0x%x\n", in ath9k_hw_init_desc()
1777 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0); in ath9k_hw_init_desc()
1846 return 0; in ath9k_hw_do_fastcc()
1853 if (cur == 0) in ath9k_hw_get_tsf_offset()
1868 u64 tsf = 0; in ath9k_hw_reset()
1876 return 0; in ath9k_hw_reset()
1889 memset(caldata, 0, sizeof(*caldata)); in ath9k_hw_reset()
1906 if (saveDefAntenna == 0) in ath9k_hw_reset()
1946 tsf_offset = ath9k_hw_get_tsf_offset(tsf_ts, 0); in ath9k_hw_reset()
1970 tsf_offset = ath9k_hw_get_tsf_offset(tsf_ts, 0); in ath9k_hw_reset()
2077 return 0; in ath9k_hw_reset()
2094 REG_CLR_BIT(ah, AR_TIMER_MODE, 0xff); in ath9k_set_power_sleep()
2095 REG_CLR_BIT(ah, AR_NDP2_TIMER_MODE, 0xff); in ath9k_set_power_sleep()
2096 REG_CLR_BIT(ah, AR_SLP32_INC, 0xfffff); in ath9k_set_power_sleep()
2098 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0); in ath9k_set_power_sleep()
2199 for (i = POWER_UP_TIME / 50; i > 0; i--) { in ath9k_hw_set_power_awake()
2207 if (i == 0) { in ath9k_hw_set_power_awake()
2278 int flags = 0; in ath9k_hw_beaconinit()
2490 if (regulatory->current_rd == 0x64 || in ath9k_hw_fill_cap_info()
2491 regulatory->current_rd == 0x65) in ath9k_hw_fill_cap_info()
2493 else if (regulatory->current_rd == 0x41) in ath9k_hw_fill_cap_info()
2494 regulatory->current_rd = 0x43; in ath9k_hw_fill_cap_info()
2495 ath_dbg(common, REGULATORY, "regdomain mapped to 0x%x\n", in ath9k_hw_fill_cap_info()
2515 if ((pCap->hw_caps & (ATH9K_HW_CAP_2GHZ | ATH9K_HW_CAP_5GHZ)) == 0) { in ath9k_hw_fill_cap_info()
2545 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */ in ath9k_hw_fill_cap_info()
2546 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7; in ath9k_hw_fill_cap_info()
2548 pCap->rx_chainmask = 0x7; in ath9k_hw_fill_cap_info()
2618 ah->ent_mode = 0x3BDA000; in ath9k_hw_fill_cap_info()
2629 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1)) { in ath9k_hw_fill_cap_info()
2643 if ((ant_div_ctl1 >> 0x6) == 0x3) { in ath9k_hw_fill_cap_info()
2655 if (tx_chainmask & BIT(0)) in ath9k_hw_fill_cap_info()
2657 if (rx_chainmask & BIT(0)) in ath9k_hw_fill_cap_info()
2683 return 0; in ath9k_hw_fill_cap_info()
2707 (0x1f << gpio_shift)); in ath9k_hw_gpio_cfg_output_mux()
2710 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0); in ath9k_hw_gpio_cfg_output_mux()
2711 tmp &= ~(0x1f << gpio_shift); in ath9k_hw_gpio_cfg_output_mux()
2748 gpio_set = out ? 1 : 0; in ath9k_hw_gpio_cfg_wmac()
2778 ath9k_hw_gpio_request(ah, gpio, false, label, 0); in ath9k_hw_gpio_request_in()
2803 u32 val = 0xffffffff; in ath9k_hw_gpio_get()
2859 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7)); in ath9k_hw_setantenna()
2889 phybits = 0; in ath9k_hw_setrxfilter()
3002 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S)); in ath9k_hw_write_associd()
3014 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) { in ath9k_hw_gettsf64()
3030 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff); in ath9k_hw_settsf64()
3031 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff); in ath9k_hw_settsf64()
3037 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0, in ath9k_hw_reset_tsf()
3062 macmode = 0; in ath9k_hw_set11nmac2040()
3071 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3072 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3073 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3074 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3075 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3076 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3077 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3078 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3079 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
3081 AR_NDP2_TIMER_MODE, 0x0002},
3083 AR_NDP2_TIMER_MODE, 0x0004},
3085 AR_NDP2_TIMER_MODE, 0x0008},
3087 AR_NDP2_TIMER_MODE, 0x0010},
3089 AR_NDP2_TIMER_MODE, 0x0020},
3091 AR_NDP2_TIMER_MODE, 0x0040},
3093 AR_NDP2_TIMER_MODE, 0x0080}
3157 u32 mask = 0; in ath9k_hw_gen_timer_start()
3174 * to use. But we still follow the old rule, 0 - 7 use tsf and in ath9k_hw_gen_timer_start()
3194 if ((ah->imask & ATH9K_INT_GENTIMER) == 0) { in ath9k_hw_gen_timer_start()
3226 if (timer_table->timer_mask == 0) { in ath9k_hw_gen_timer_stop()
3315 { 0, "5133" },
3329 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) { in ath9k_hw_mac_bb_name()
3346 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) { in ath9k_hw_rf_name()
3376 hw_name[used] = '\0'; in ath9k_hw_name()