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/linux/arch/arm64/boot/dts/arm/
H A Dmorello.dtsi16 #clock-cells = <0>;
23 #clock-cells = <0>;
30 #size-cells = <0>;
32 cpu0: cpu@0 {
34 reg = <0x0 0x0>;
38 i-cache-size = <0x10000>;
41 d-cache-size = <0x10000>;
45 clocks = <&scmi_dvfs 0>;
51 cache-size = <0x100000>;
61 reg = <0x0 0x100>;
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mn.dtsi46 #size-cells = <0>;
53 arm,psci-suspend-param = <0x0010033>;
61 A53_0: cpu@0 {
64 reg = <0x0>;
67 i-cache-size = <0x8000>;
70 d-cache-size = <0x8000>;
84 reg = <0x1>;
87 i-cache-size = <0x8000>;
90 d-cache-size = <0x8000>;
102 reg = <0x2>;
[all …]
/linux/arch/arm/boot/dts/rockchip/
H A Drk322x.dtsi30 #size-cells = <0>;
35 reg = <0xf00>;
46 reg = <0xf01>;
56 reg = <0xf02>;
66 reg = <0xf03>;
74 cpu0_opp_table: opp-table-0 {
130 #clock-cells = <0>;
140 reg = <0x100b0000 0x4000>;
147 pinctrl-0 = <&i2s1_bus>;
153 reg = <0x100c0000 0x4000>;
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/engine/gr/
H A Dctxnv50.c23 #define CP_FLAG_CLEAR 0
25 #define CP_FLAG_SWAP_DIRECTION ((0 * 32) + 0)
26 #define CP_FLAG_SWAP_DIRECTION_LOAD 0
28 #define CP_FLAG_UNK01 ((0 * 32) + 1)
29 #define CP_FLAG_UNK01_CLEAR 0
31 #define CP_FLAG_UNK03 ((0 * 32) + 3)
32 #define CP_FLAG_UNK03_CLEAR 0
34 #define CP_FLAG_USER_SAVE ((0 * 32) + 5)
35 #define CP_FLAG_USER_SAVE_NOT_PENDING 0
37 #define CP_FLAG_USER_LOAD ((0 * 32) + 6)
[all …]