23 #define CP_FLAG_CLEAR                 0
25 #define CP_FLAG_SWAP_DIRECTION        ((0 * 32) + 0)
26 #define CP_FLAG_SWAP_DIRECTION_LOAD   0
28 #define CP_FLAG_UNK01                 ((0 * 32) + 1)
29 #define CP_FLAG_UNK01_CLEAR           0
31 #define CP_FLAG_UNK03                 ((0 * 32) + 3)
32 #define CP_FLAG_UNK03_CLEAR           0
34 #define CP_FLAG_USER_SAVE             ((0 * 32) + 5)
35 #define CP_FLAG_USER_SAVE_NOT_PENDING 0
37 #define CP_FLAG_USER_LOAD             ((0 * 32) + 6)
38 #define CP_FLAG_USER_LOAD_NOT_PENDING 0
40 #define CP_FLAG_UNK0B                 ((0 * 32) + 0xb)
41 #define CP_FLAG_UNK0B_CLEAR           0
43 #define CP_FLAG_XFER_SWITCH           ((0 * 32) + 0xe)
44 #define CP_FLAG_XFER_SWITCH_DISABLE   0
46 #define CP_FLAG_STATE                 ((0 * 32) + 0x1c)
47 #define CP_FLAG_STATE_STOPPED         0
49 #define CP_FLAG_UNK1D                 ((0 * 32) + 0x1d)
50 #define CP_FLAG_UNK1D_CLEAR           0
52 #define CP_FLAG_UNK20                 ((1 * 32) + 0)
53 #define CP_FLAG_UNK20_CLEAR           0
55 #define CP_FLAG_STATUS                ((2 * 32) + 0)
56 #define CP_FLAG_STATUS_BUSY           0
59 #define CP_FLAG_AUTO_SAVE_NOT_PENDING 0
62 #define CP_FLAG_AUTO_LOAD_NOT_PENDING 0
65 #define CP_FLAG_NEWCTX_BUSY           0
68 #define CP_FLAG_XFER_IDLE             0
71 #define CP_FLAG_ALWAYS_FALSE          0
74 #define CP_FLAG_INTR_NOT_PENDING      0
77 #define CP_CTX                   0x00100000
78 #define CP_CTX_COUNT             0x000f0000
80 #define CP_CTX_REG               0x00003fff
81 #define CP_LOAD_SR               0x00200000
82 #define CP_LOAD_SR_VALUE         0x000fffff
83 #define CP_BRA                   0x00400000
84 #define CP_BRA_IP                0x0001ff00
86 #define CP_BRA_IF_CLEAR          0x00000080
87 #define CP_BRA_FLAG              0x0000007f
88 #define CP_WAIT                  0x00500000
89 #define CP_WAIT_SET              0x00000080
90 #define CP_WAIT_FLAG             0x0000007f
91 #define CP_SET                   0x00700000
92 #define CP_SET_1                 0x00000080
93 #define CP_SET_FLAG              0x0000007f
94 #define CP_NEWCTX                0x00600004
95 #define CP_NEXT_TO_SWAP          0x00600005
96 #define CP_SET_CONTEXT_POINTER   0x00600006
97 #define CP_SET_XFER_POINTER      0x00600007
98 #define CP_ENABLE                0x00600009
99 #define CP_END                   0x0060000c
100 #define CP_NEXT_TO_CURRENT       0x0060000d
101 #define CP_DISABLE1              0x0090ffff
102 #define CP_DISABLE2              0x0091ffff
103 #define CP_XFER_1      0x008000ff
104 #define CP_XFER_2      0x008800ff
105 #define CP_SEEK_1      0x00c000ff
106 #define CP_SEEK_2      0x00c800ff
113 #define IS_NVA3F(x) (((x) > 0xa0 && (x) < 0xaa) || (x) == 0xaf)
114 #define IS_NVAAF(x) ((x) >= 0xaa && (x) <= 0xac)
157  *  - use 0x4008fc instead of 0x1540?
217 	cp_pos (ctx, 0x00004/4);  in nv50_grctx_generate()
218 	cp_ctx (ctx, 0x400828, 1); /* needed. otherwise, flickering happens. */  in nv50_grctx_generate()
219 	cp_pos (ctx, 0x00100/4);  in nv50_grctx_generate()
250 	ctx->ctxvals_pos += 0x400; /* padding... no idea why you need it */  in nv50_grctx_generate()
252 	return 0;  in nv50_grctx_generate()
280 	nvkm_wr32(device, 0x400324, 0);  in nv50_grctx_init()
281 	for (i = 0; i < ctx.ctxprog_len; i++)  in nv50_grctx_init()
282 		nvkm_wr32(device, 0x400328, ctxprog[i]);  in nv50_grctx_init()
285 	return 0;  in nv50_grctx_init()
302 	u32 units = nvkm_rd32(device, 0x1540);  in nv50_gr_construct_mmio()
305 	cp_ctx(ctx, 0x400808, 7);  in nv50_gr_construct_mmio()
306 	gr_def(ctx, 0x400814, 0x00000030);  in nv50_gr_construct_mmio()
307 	cp_ctx(ctx, 0x400834, 0x32);  in nv50_gr_construct_mmio()
308 	if (device->chipset == 0x50) {  in nv50_gr_construct_mmio()
309 		gr_def(ctx, 0x400834, 0xff400040);  in nv50_gr_construct_mmio()
310 		gr_def(ctx, 0x400838, 0xfff00080);  in nv50_gr_construct_mmio()
311 		gr_def(ctx, 0x40083c, 0xfff70090);  in nv50_gr_construct_mmio()
312 		gr_def(ctx, 0x400840, 0xffe806a8);  in nv50_gr_construct_mmio()
314 	gr_def(ctx, 0x400844, 0x00000002);  in nv50_gr_construct_mmio()
316 		gr_def(ctx, 0x400894, 0x00001000);  in nv50_gr_construct_mmio()
317 	gr_def(ctx, 0x4008e8, 0x00000003);  in nv50_gr_construct_mmio()
318 	gr_def(ctx, 0x4008ec, 0x00001000);  in nv50_gr_construct_mmio()
319 	if (device->chipset == 0x50)  in nv50_gr_construct_mmio()
320 		cp_ctx(ctx, 0x400908, 0xb);  in nv50_gr_construct_mmio()
321 	else if (device->chipset < 0xa0)  in nv50_gr_construct_mmio()
322 		cp_ctx(ctx, 0x400908, 0xc);  in nv50_gr_construct_mmio()
324 		cp_ctx(ctx, 0x400908, 0xe);  in nv50_gr_construct_mmio()
326 	if (device->chipset >= 0xa0)  in nv50_gr_construct_mmio()
327 		cp_ctx(ctx, 0x400b00, 0x1);  in nv50_gr_construct_mmio()
329 		cp_ctx(ctx, 0x400b10, 0x1);  in nv50_gr_construct_mmio()
330 		gr_def(ctx, 0x400b10, 0x0001629d);  in nv50_gr_construct_mmio()
331 		cp_ctx(ctx, 0x400b20, 0x1);  in nv50_gr_construct_mmio()
332 		gr_def(ctx, 0x400b20, 0x0001629d);  in nv50_gr_construct_mmio()
337 	/* 0C00: VFETCH */  in nv50_gr_construct_mmio()
338 	cp_ctx(ctx, 0x400c08, 0x2);  in nv50_gr_construct_mmio()
339 	gr_def(ctx, 0x400c08, 0x0000fe0c);  in nv50_gr_construct_mmio()
342 	if (device->chipset < 0xa0) {  in nv50_gr_construct_mmio()
343 		cp_ctx(ctx, 0x401008, 0x4);  in nv50_gr_construct_mmio()
344 		gr_def(ctx, 0x401014, 0x00001000);  in nv50_gr_construct_mmio()
346 		cp_ctx(ctx, 0x401008, 0x5);  in nv50_gr_construct_mmio()
347 		gr_def(ctx, 0x401018, 0x00001000);  in nv50_gr_construct_mmio()
349 		cp_ctx(ctx, 0x401008, 0x5);  in nv50_gr_construct_mmio()
350 		gr_def(ctx, 0x401018, 0x00004000);  in nv50_gr_construct_mmio()
354 	cp_ctx(ctx, 0x401400, 0x8);  in nv50_gr_construct_mmio()
355 	cp_ctx(ctx, 0x401424, 0x3);  in nv50_gr_construct_mmio()
356 	if (device->chipset == 0x50)  in nv50_gr_construct_mmio()
357 		gr_def(ctx, 0x40142c, 0x0001fd87);  in nv50_gr_construct_mmio()
359 		gr_def(ctx, 0x40142c, 0x00000187);  in nv50_gr_construct_mmio()
360 	cp_ctx(ctx, 0x401540, 0x5);  in nv50_gr_construct_mmio()
361 	gr_def(ctx, 0x401550, 0x00001018);  in nv50_gr_construct_mmio()
364 	cp_ctx(ctx, 0x401814, 0x1);  in nv50_gr_construct_mmio()
365 	gr_def(ctx, 0x401814, 0x000000ff);  in nv50_gr_construct_mmio()
366 	if (device->chipset == 0x50) {  in nv50_gr_construct_mmio()
367 		cp_ctx(ctx, 0x40181c, 0xe);  in nv50_gr_construct_mmio()
368 		gr_def(ctx, 0x401850, 0x00000004);  in nv50_gr_construct_mmio()
369 	} else if (device->chipset < 0xa0) {  in nv50_gr_construct_mmio()
370 		cp_ctx(ctx, 0x40181c, 0xf);  in nv50_gr_construct_mmio()
371 		gr_def(ctx, 0x401854, 0x00000004);  in nv50_gr_construct_mmio()
373 		cp_ctx(ctx, 0x40181c, 0x13);  in nv50_gr_construct_mmio()
374 		gr_def(ctx, 0x401864, 0x00000004);  in nv50_gr_construct_mmio()
378 	cp_ctx(ctx, 0x401c00, 0x1);  in nv50_gr_construct_mmio()
380 	case 0x50:  in nv50_gr_construct_mmio()
381 		gr_def(ctx, 0x401c00, 0x0001005f);  in nv50_gr_construct_mmio()
383 	case 0x84:  in nv50_gr_construct_mmio()
384 	case 0x86:  in nv50_gr_construct_mmio()
385 	case 0x94:  in nv50_gr_construct_mmio()
386 		gr_def(ctx, 0x401c00, 0x044d00df);  in nv50_gr_construct_mmio()
388 	case 0x92:  in nv50_gr_construct_mmio()
389 	case 0x96:  in nv50_gr_construct_mmio()
390 	case 0x98:  in nv50_gr_construct_mmio()
391 	case 0xa0:  in nv50_gr_construct_mmio()
392 	case 0xaa:  in nv50_gr_construct_mmio()
393 	case 0xac:  in nv50_gr_construct_mmio()
394 		gr_def(ctx, 0x401c00, 0x042500df);  in nv50_gr_construct_mmio()
396 	case 0xa3:  in nv50_gr_construct_mmio()
397 	case 0xa5:  in nv50_gr_construct_mmio()
398 	case 0xa8:  in nv50_gr_construct_mmio()
399 	case 0xaf:  in nv50_gr_construct_mmio()
400 		gr_def(ctx, 0x401c00, 0x142500df);  in nv50_gr_construct_mmio()
407 	cp_ctx(ctx, 0x402400, 0x1);  in nv50_gr_construct_mmio()
408 	if (device->chipset == 0x50)  in nv50_gr_construct_mmio()
409 		cp_ctx(ctx, 0x402408, 0x1);  in nv50_gr_construct_mmio()
411 		cp_ctx(ctx, 0x402408, 0x2);  in nv50_gr_construct_mmio()
412 	gr_def(ctx, 0x402408, 0x00000600);  in nv50_gr_construct_mmio()
415 	cp_ctx(ctx, 0x402800, 0x1);  in nv50_gr_construct_mmio()
416 	if (device->chipset == 0x50)  in nv50_gr_construct_mmio()
417 		gr_def(ctx, 0x402800, 0x00000006);  in nv50_gr_construct_mmio()
420 	cp_ctx(ctx, 0x402c08, 0x6);  in nv50_gr_construct_mmio()
421 	if (device->chipset != 0x50)  in nv50_gr_construct_mmio()
422 		gr_def(ctx, 0x402c14, 0x01000000);  in nv50_gr_construct_mmio()
423 	gr_def(ctx, 0x402c18, 0x000000ff);  in nv50_gr_construct_mmio()
424 	if (device->chipset == 0x50)  in nv50_gr_construct_mmio()
425 		cp_ctx(ctx, 0x402ca0, 0x1);  in nv50_gr_construct_mmio()
427 		cp_ctx(ctx, 0x402ca0, 0x2);  in nv50_gr_construct_mmio()
428 	if (device->chipset < 0xa0)  in nv50_gr_construct_mmio()
429 		gr_def(ctx, 0x402ca0, 0x00000400);  in nv50_gr_construct_mmio()
431 		gr_def(ctx, 0x402ca0, 0x00000800);  in nv50_gr_construct_mmio()
433 		gr_def(ctx, 0x402ca0, 0x00000400);  in nv50_gr_construct_mmio()
434 	cp_ctx(ctx, 0x402cac, 0x4);  in nv50_gr_construct_mmio()
437 	cp_ctx(ctx, 0x403004, 0x1);  in nv50_gr_construct_mmio()
438 	gr_def(ctx, 0x403004, 0x00000001);  in nv50_gr_construct_mmio()
441 	if (device->chipset >= 0xa0) {  in nv50_gr_construct_mmio()
442 		cp_ctx(ctx, 0x403404, 0x1);  in nv50_gr_construct_mmio()
443 		gr_def(ctx, 0x403404, 0x00000001);  in nv50_gr_construct_mmio()
447 	cp_ctx(ctx, 0x405000, 0x1);  in nv50_gr_construct_mmio()
449 	case 0x50:  in nv50_gr_construct_mmio()
450 		gr_def(ctx, 0x405000, 0x00300080);  in nv50_gr_construct_mmio()
452 	case 0x84:  in nv50_gr_construct_mmio()
453 	case 0xa0:  in nv50_gr_construct_mmio()
454 	case 0xa3:  in nv50_gr_construct_mmio()
455 	case 0xa5:  in nv50_gr_construct_mmio()
456 	case 0xa8:  in nv50_gr_construct_mmio()
457 	case 0xaa:  in nv50_gr_construct_mmio()
458 	case 0xac:  in nv50_gr_construct_mmio()
459 	case 0xaf:  in nv50_gr_construct_mmio()
460 		gr_def(ctx, 0x405000, 0x000e0080);  in nv50_gr_construct_mmio()
462 	case 0x86:  in nv50_gr_construct_mmio()
463 	case 0x92:  in nv50_gr_construct_mmio()
464 	case 0x94:  in nv50_gr_construct_mmio()
465 	case 0x96:  in nv50_gr_construct_mmio()
466 	case 0x98:  in nv50_gr_construct_mmio()
467 		gr_def(ctx, 0x405000, 0x00000080);  in nv50_gr_construct_mmio()
470 	cp_ctx(ctx, 0x405014, 0x1);  in nv50_gr_construct_mmio()
471 	gr_def(ctx, 0x405014, 0x00000004);  in nv50_gr_construct_mmio()
472 	cp_ctx(ctx, 0x40501c, 0x1);  in nv50_gr_construct_mmio()
473 	cp_ctx(ctx, 0x405024, 0x1);  in nv50_gr_construct_mmio()
474 	cp_ctx(ctx, 0x40502c, 0x1);  in nv50_gr_construct_mmio()
477 	if (device->chipset == 0x50)  in nv50_gr_construct_mmio()
478 		cp_ctx(ctx, 0x4063e0, 0x1);  in nv50_gr_construct_mmio()
481 	if (device->chipset < 0x90) {  in nv50_gr_construct_mmio()
482 		cp_ctx(ctx, 0x406814, 0x2b);  in nv50_gr_construct_mmio()
483 		gr_def(ctx, 0x406818, 0x00000f80);  in nv50_gr_construct_mmio()
484 		gr_def(ctx, 0x406860, 0x007f0080);  in nv50_gr_construct_mmio()
485 		gr_def(ctx, 0x40689c, 0x007f0080);  in nv50_gr_construct_mmio()
487 		cp_ctx(ctx, 0x406814, 0x4);  in nv50_gr_construct_mmio()
488 		if (device->chipset == 0x98)  in nv50_gr_construct_mmio()
489 			gr_def(ctx, 0x406818, 0x00000f80);  in nv50_gr_construct_mmio()
491 			gr_def(ctx, 0x406818, 0x00001f80);  in nv50_gr_construct_mmio()
493 			gr_def(ctx, 0x40681c, 0x00000030);  in nv50_gr_construct_mmio()
494 		cp_ctx(ctx, 0x406830, 0x3);  in nv50_gr_construct_mmio()
498 	for (i = 0; i < 8; i++) {  in nv50_gr_construct_mmio()
500 			cp_ctx(ctx, 0x407000 + (i<<8), 3);  in nv50_gr_construct_mmio()
501 			if (device->chipset == 0x50)  in nv50_gr_construct_mmio()
502 				gr_def(ctx, 0x407000 + (i<<8), 0x1b74f820);  in nv50_gr_construct_mmio()
503 			else if (device->chipset != 0xa5)  in nv50_gr_construct_mmio()
504 				gr_def(ctx, 0x407000 + (i<<8), 0x3b74f821);  in nv50_gr_construct_mmio()
506 				gr_def(ctx, 0x407000 + (i<<8), 0x7b74f821);  in nv50_gr_construct_mmio()
507 			gr_def(ctx, 0x407004 + (i<<8), 0x89058001);  in nv50_gr_construct_mmio()
509 			if (device->chipset == 0x50) {  in nv50_gr_construct_mmio()
510 				cp_ctx(ctx, 0x407010 + (i<<8), 1);  in nv50_gr_construct_mmio()
511 			} else if (device->chipset < 0xa0) {  in nv50_gr_construct_mmio()
512 				cp_ctx(ctx, 0x407010 + (i<<8), 2);  in nv50_gr_construct_mmio()
513 				gr_def(ctx, 0x407010 + (i<<8), 0x00001000);  in nv50_gr_construct_mmio()
514 				gr_def(ctx, 0x407014 + (i<<8), 0x0000001f);  in nv50_gr_construct_mmio()
516 				cp_ctx(ctx, 0x407010 + (i<<8), 3);  in nv50_gr_construct_mmio()
517 				gr_def(ctx, 0x407010 + (i<<8), 0x00001000);  in nv50_gr_construct_mmio()
518 				if (device->chipset != 0xa5)  in nv50_gr_construct_mmio()
519 					gr_def(ctx, 0x407014 + (i<<8), 0x000000ff);  in nv50_gr_construct_mmio()
521 					gr_def(ctx, 0x407014 + (i<<8), 0x000001ff);  in nv50_gr_construct_mmio()
524 			cp_ctx(ctx, 0x407080 + (i<<8), 4);  in nv50_gr_construct_mmio()
525 			if (device->chipset != 0xa5)  in nv50_gr_construct_mmio()
526 				gr_def(ctx, 0x407080 + (i<<8), 0x027c10fa);  in nv50_gr_construct_mmio()
528 				gr_def(ctx, 0x407080 + (i<<8), 0x827c10fa);  in nv50_gr_construct_mmio()
529 			if (device->chipset == 0x50)  in nv50_gr_construct_mmio()
530 				gr_def(ctx, 0x407084 + (i<<8), 0x000000c0);  in nv50_gr_construct_mmio()
532 				gr_def(ctx, 0x407084 + (i<<8), 0x400000c0);  in nv50_gr_construct_mmio()
533 			gr_def(ctx, 0x407088 + (i<<8), 0xb7892080);  in nv50_gr_construct_mmio()
535 			if (device->chipset < 0xa0)  in nv50_gr_construct_mmio()
536 				cp_ctx(ctx, 0x407094 + (i<<8), 1);  in nv50_gr_construct_mmio()
538 				cp_ctx(ctx, 0x407094 + (i<<8), 3);  in nv50_gr_construct_mmio()
540 				cp_ctx(ctx, 0x407094 + (i<<8), 4);  in nv50_gr_construct_mmio()
541 				gr_def(ctx, 0x4070a0 + (i<<8), 1);  in nv50_gr_construct_mmio()
546 	cp_ctx(ctx, 0x407c00, 0x3);  in nv50_gr_construct_mmio()
547 	if (device->chipset < 0x90)  in nv50_gr_construct_mmio()
548 		gr_def(ctx, 0x407c00, 0x00010040);  in nv50_gr_construct_mmio()
549 	else if (device->chipset < 0xa0)  in nv50_gr_construct_mmio()
550 		gr_def(ctx, 0x407c00, 0x00390040);  in nv50_gr_construct_mmio()
552 		gr_def(ctx, 0x407c00, 0x003d0040);  in nv50_gr_construct_mmio()
553 	gr_def(ctx, 0x407c08, 0x00000022);  in nv50_gr_construct_mmio()
554 	if (device->chipset >= 0xa0) {  in nv50_gr_construct_mmio()
555 		cp_ctx(ctx, 0x407c10, 0x3);  in nv50_gr_construct_mmio()
556 		cp_ctx(ctx, 0x407c20, 0x1);  in nv50_gr_construct_mmio()
557 		cp_ctx(ctx, 0x407c2c, 0x1);  in nv50_gr_construct_mmio()
560 	if (device->chipset < 0xa0) {  in nv50_gr_construct_mmio()
561 		cp_ctx(ctx, 0x407d00, 0x9);  in nv50_gr_construct_mmio()
563 		cp_ctx(ctx, 0x407d00, 0x15);  in nv50_gr_construct_mmio()
565 	if (device->chipset == 0x98)  in nv50_gr_construct_mmio()
566 		gr_def(ctx, 0x407d08, 0x00380040);  in nv50_gr_construct_mmio()
568 		if (device->chipset < 0x90)  in nv50_gr_construct_mmio()
569 			gr_def(ctx, 0x407d08, 0x00010040);  in nv50_gr_construct_mmio()
570 		else if (device->chipset < 0xa0)  in nv50_gr_construct_mmio()
571 			gr_def(ctx, 0x407d08, 0x00390040);  in nv50_gr_construct_mmio()
574 				gr_def(ctx, 0x407d08, 0x003d0040);  in nv50_gr_construct_mmio()
576 				gr_def(ctx, 0x407d08, 0x003c0040);  in nv50_gr_construct_mmio()
578 		gr_def(ctx, 0x407d0c, 0x00000022);  in nv50_gr_construct_mmio()
582 	for (i = 0; i < 10; i++) {  in nv50_gr_construct_mmio()
584 			if (device->chipset < 0xa0)  in nv50_gr_construct_mmio()
585 				base = 0x408000 + (i<<12);  in nv50_gr_construct_mmio()
587 				base = 0x408000 + (i<<11);  in nv50_gr_construct_mmio()
588 			if (device->chipset < 0xa0)  in nv50_gr_construct_mmio()
589 				offset = base + 0xc00;  in nv50_gr_construct_mmio()
591 				offset = base + 0x80;  in nv50_gr_construct_mmio()
592 			cp_ctx(ctx, offset + 0x00, 1);  in nv50_gr_construct_mmio()
593 			gr_def(ctx, offset + 0x00, 0x0000ff0a);  in nv50_gr_construct_mmio()
594 			cp_ctx(ctx, offset + 0x08, 1);  in nv50_gr_construct_mmio()
597 			for (j = 0; j < (device->chipset < 0xa0 ? 2 : 4); j++) {  in nv50_gr_construct_mmio()
599 				if (device->chipset < 0xa0)  in nv50_gr_construct_mmio()
600 					offset = base + 0x200 + (j<<7);  in nv50_gr_construct_mmio()
602 					offset = base + 0x100 + (j<<7);  in nv50_gr_construct_mmio()
603 				cp_ctx(ctx, offset, 0x20);  in nv50_gr_construct_mmio()
604 				gr_def(ctx, offset + 0x00, 0x01800000);  in nv50_gr_construct_mmio()
605 				gr_def(ctx, offset + 0x04, 0x00160000);  in nv50_gr_construct_mmio()
606 				gr_def(ctx, offset + 0x08, 0x01800000);  in nv50_gr_construct_mmio()
607 				gr_def(ctx, offset + 0x18, 0x0003ffff);  in nv50_gr_construct_mmio()
609 				case 0x50:  in nv50_gr_construct_mmio()
610 					gr_def(ctx, offset + 0x1c, 0x00080000);  in nv50_gr_construct_mmio()
612 				case 0x84:  in nv50_gr_construct_mmio()
613 					gr_def(ctx, offset + 0x1c, 0x00880000);  in nv50_gr_construct_mmio()
615 				case 0x86:  in nv50_gr_construct_mmio()
616 					gr_def(ctx, offset + 0x1c, 0x018c0000);  in nv50_gr_construct_mmio()
618 				case 0x92:  in nv50_gr_construct_mmio()
619 				case 0x96:  in nv50_gr_construct_mmio()
620 				case 0x98:  in nv50_gr_construct_mmio()
621 					gr_def(ctx, offset + 0x1c, 0x118c0000);  in nv50_gr_construct_mmio()
623 				case 0x94:  in nv50_gr_construct_mmio()
624 					gr_def(ctx, offset + 0x1c, 0x10880000);  in nv50_gr_construct_mmio()
626 				case 0xa0:  in nv50_gr_construct_mmio()
627 				case 0xa5:  in nv50_gr_construct_mmio()
628 					gr_def(ctx, offset + 0x1c, 0x310c0000);  in nv50_gr_construct_mmio()
630 				case 0xa3:  in nv50_gr_construct_mmio()
631 				case 0xa8:  in nv50_gr_construct_mmio()
632 				case 0xaa:  in nv50_gr_construct_mmio()
633 				case 0xac:  in nv50_gr_construct_mmio()
634 				case 0xaf:  in nv50_gr_construct_mmio()
635 					gr_def(ctx, offset + 0x1c, 0x300c0000);  in nv50_gr_construct_mmio()
638 				gr_def(ctx, offset + 0x40, 0x00010401);  in nv50_gr_construct_mmio()
639 				if (device->chipset == 0x50)  in nv50_gr_construct_mmio()
640 					gr_def(ctx, offset + 0x48, 0x00000040);  in nv50_gr_construct_mmio()
642 					gr_def(ctx, offset + 0x48, 0x00000078);  in nv50_gr_construct_mmio()
643 				gr_def(ctx, offset + 0x50, 0x000000bf);  in nv50_gr_construct_mmio()
644 				gr_def(ctx, offset + 0x58, 0x00001210);  in nv50_gr_construct_mmio()
645 				if (device->chipset == 0x50)  in nv50_gr_construct_mmio()
646 					gr_def(ctx, offset + 0x5c, 0x00000080);  in nv50_gr_construct_mmio()
648 					gr_def(ctx, offset + 0x5c, 0x08000080);  in nv50_gr_construct_mmio()
649 				if (device->chipset >= 0xa0)  in nv50_gr_construct_mmio()
650 					gr_def(ctx, offset + 0x68, 0x0000003e);  in nv50_gr_construct_mmio()
653 			if (device->chipset < 0xa0)  in nv50_gr_construct_mmio()
654 				cp_ctx(ctx, base + 0x300, 0x4);  in nv50_gr_construct_mmio()
656 				cp_ctx(ctx, base + 0x300, 0x5);  in nv50_gr_construct_mmio()
657 			if (device->chipset == 0x50)  in nv50_gr_construct_mmio()
658 				gr_def(ctx, base + 0x304, 0x00007070);  in nv50_gr_construct_mmio()
659 			else if (device->chipset < 0xa0)  in nv50_gr_construct_mmio()
660 				gr_def(ctx, base + 0x304, 0x00027070);  in nv50_gr_construct_mmio()
662 				gr_def(ctx, base + 0x304, 0x01127070);  in nv50_gr_construct_mmio()
664 				gr_def(ctx, base + 0x304, 0x05127070);  in nv50_gr_construct_mmio()
666 			if (device->chipset < 0xa0)  in nv50_gr_construct_mmio()
667 				cp_ctx(ctx, base + 0x318, 1);  in nv50_gr_construct_mmio()
669 				cp_ctx(ctx, base + 0x320, 1);  in nv50_gr_construct_mmio()
670 			if (device->chipset == 0x50)  in nv50_gr_construct_mmio()
671 				gr_def(ctx, base + 0x318, 0x0003ffff);  in nv50_gr_construct_mmio()
672 			else if (device->chipset < 0xa0)  in nv50_gr_construct_mmio()
673 				gr_def(ctx, base + 0x318, 0x03ffffff);  in nv50_gr_construct_mmio()
675 				gr_def(ctx, base + 0x320, 0x07ffffff);  in nv50_gr_construct_mmio()
677 			if (device->chipset < 0xa0)  in nv50_gr_construct_mmio()
678 				cp_ctx(ctx, base + 0x324, 5);  in nv50_gr_construct_mmio()
680 				cp_ctx(ctx, base + 0x328, 4);  in nv50_gr_construct_mmio()
682 			if (device->chipset < 0xa0) {  in nv50_gr_construct_mmio()
683 				cp_ctx(ctx, base + 0x340, 9);  in nv50_gr_construct_mmio()
684 				offset = base + 0x340;  in nv50_gr_construct_mmio()
686 				cp_ctx(ctx, base + 0x33c, 0xb);  in nv50_gr_construct_mmio()
687 				offset = base + 0x344;  in nv50_gr_construct_mmio()
689 				cp_ctx(ctx, base + 0x33c, 0xd);  in nv50_gr_construct_mmio()
690 				offset = base + 0x344;  in nv50_gr_construct_mmio()
692 			gr_def(ctx, offset + 0x0, 0x00120407);  in nv50_gr_construct_mmio()
693 			gr_def(ctx, offset + 0x4, 0x05091507);  in nv50_gr_construct_mmio()
694 			if (device->chipset == 0x84)  in nv50_gr_construct_mmio()
695 				gr_def(ctx, offset + 0x8, 0x05100202);  in nv50_gr_construct_mmio()
697 				gr_def(ctx, offset + 0x8, 0x05010202);  in nv50_gr_construct_mmio()
698 			gr_def(ctx, offset + 0xc, 0x00030201);  in nv50_gr_construct_mmio()
699 			if (device->chipset == 0xa3)  in nv50_gr_construct_mmio()
700 				cp_ctx(ctx, base + 0x36c, 1);  in nv50_gr_construct_mmio()
702 			cp_ctx(ctx, base + 0x400, 2);  in nv50_gr_construct_mmio()
703 			gr_def(ctx, base + 0x404, 0x00000040);  in nv50_gr_construct_mmio()
704 			cp_ctx(ctx, base + 0x40c, 2);  in nv50_gr_construct_mmio()
705 			gr_def(ctx, base + 0x40c, 0x0d0c0b0a);  in nv50_gr_construct_mmio()
706 			gr_def(ctx, base + 0x410, 0x00141210);  in nv50_gr_construct_mmio()
708 			if (device->chipset < 0xa0)  in nv50_gr_construct_mmio()
709 				offset = base + 0x800;  in nv50_gr_construct_mmio()
711 				offset = base + 0x500;  in nv50_gr_construct_mmio()
713 			gr_def(ctx, offset + 0x0, 0x000001f0);  in nv50_gr_construct_mmio()
714 			gr_def(ctx, offset + 0x4, 0x00000001);  in nv50_gr_construct_mmio()
715 			gr_def(ctx, offset + 0x8, 0x00000003);  in nv50_gr_construct_mmio()
716 			if (device->chipset == 0x50 || IS_NVAAF(device->chipset))  in nv50_gr_construct_mmio()
717 				gr_def(ctx, offset + 0xc, 0x00008000);  in nv50_gr_construct_mmio()
718 			gr_def(ctx, offset + 0x14, 0x00039e00);  in nv50_gr_construct_mmio()
719 			cp_ctx(ctx, offset + 0x1c, 2);  in nv50_gr_construct_mmio()
720 			if (device->chipset == 0x50)  in nv50_gr_construct_mmio()
721 				gr_def(ctx, offset + 0x1c, 0x00000040);  in nv50_gr_construct_mmio()
723 				gr_def(ctx, offset + 0x1c, 0x00000100);  in nv50_gr_construct_mmio()
724 			gr_def(ctx, offset + 0x20, 0x00003800);  in nv50_gr_construct_mmio()
726 			if (device->chipset >= 0xa0) {  in nv50_gr_construct_mmio()
727 				cp_ctx(ctx, base + 0x54c, 2);  in nv50_gr_construct_mmio()
729 					gr_def(ctx, base + 0x54c, 0x003fe006);  in nv50_gr_construct_mmio()
731 					gr_def(ctx, base + 0x54c, 0x003fe007);  in nv50_gr_construct_mmio()
732 				gr_def(ctx, base + 0x550, 0x003fe000);  in nv50_gr_construct_mmio()
735 			if (device->chipset < 0xa0)  in nv50_gr_construct_mmio()
736 				offset = base + 0xa00;  in nv50_gr_construct_mmio()
738 				offset = base + 0x680;  in nv50_gr_construct_mmio()
740 			gr_def(ctx, offset, 0x00404040);  in nv50_gr_construct_mmio()
742 			if (device->chipset < 0xa0)  in nv50_gr_construct_mmio()
743 				offset = base + 0xe00;  in nv50_gr_construct_mmio()
745 				offset = base + 0x700;  in nv50_gr_construct_mmio()
747 			if (device->chipset < 0xa0)  in nv50_gr_construct_mmio()
748 				gr_def(ctx, offset, 0x0077f005);  in nv50_gr_construct_mmio()
749 			else if (device->chipset == 0xa5)  in nv50_gr_construct_mmio()
750 				gr_def(ctx, offset, 0x6cf7f007);  in nv50_gr_construct_mmio()
751 			else if (device->chipset == 0xa8)  in nv50_gr_construct_mmio()
752 				gr_def(ctx, offset, 0x6cfff007);  in nv50_gr_construct_mmio()
753 			else if (device->chipset == 0xac)  in nv50_gr_construct_mmio()
754 				gr_def(ctx, offset, 0x0cfff007);  in nv50_gr_construct_mmio()
756 				gr_def(ctx, offset, 0x0cf7f007);  in nv50_gr_construct_mmio()
757 			if (device->chipset == 0x50)  in nv50_gr_construct_mmio()
758 				gr_def(ctx, offset + 0x4, 0x00007fff);  in nv50_gr_construct_mmio()
759 			else if (device->chipset < 0xa0)  in nv50_gr_construct_mmio()
760 				gr_def(ctx, offset + 0x4, 0x003f7fff);  in nv50_gr_construct_mmio()
762 				gr_def(ctx, offset + 0x4, 0x02bf7fff);  in nv50_gr_construct_mmio()
763 			cp_ctx(ctx, offset + 0x2c, 1);  in nv50_gr_construct_mmio()
764 			if (device->chipset == 0x50) {  in nv50_gr_construct_mmio()
765 				cp_ctx(ctx, offset + 0x50, 9);  in nv50_gr_construct_mmio()
766 				gr_def(ctx, offset + 0x54, 0x000003ff);  in nv50_gr_construct_mmio()
767 				gr_def(ctx, offset + 0x58, 0x00000003);  in nv50_gr_construct_mmio()
768 				gr_def(ctx, offset + 0x5c, 0x00000003);  in nv50_gr_construct_mmio()
769 				gr_def(ctx, offset + 0x60, 0x000001ff);  in nv50_gr_construct_mmio()
770 				gr_def(ctx, offset + 0x64, 0x0000001f);  in nv50_gr_construct_mmio()
771 				gr_def(ctx, offset + 0x68, 0x0000000f);  in nv50_gr_construct_mmio()
772 				gr_def(ctx, offset + 0x6c, 0x0000000f);  in nv50_gr_construct_mmio()
773 			} else if (device->chipset < 0xa0) {  in nv50_gr_construct_mmio()
774 				cp_ctx(ctx, offset + 0x50, 1);  in nv50_gr_construct_mmio()
775 				cp_ctx(ctx, offset + 0x70, 1);  in nv50_gr_construct_mmio()
777 				cp_ctx(ctx, offset + 0x50, 1);  in nv50_gr_construct_mmio()
778 				cp_ctx(ctx, offset + 0x60, 5);  in nv50_gr_construct_mmio()
788 		for (i = 0; i < num; i++)  in dd_emit()
802 	dd_emit(ctx, 1, 0);	/* 00000001 UNK0F90 */  in nv50_gr_construct_mmio_ddata()
803 	dd_emit(ctx, 1, 0);	/* 00000001 UNK135C */  in nv50_gr_construct_mmio_ddata()
806 	dd_emit(ctx, 1, 0);	/* 00000007 SRC_TILE_MODE_Z */  in nv50_gr_construct_mmio_ddata()
809 	dd_emit(ctx, 1, 0);	/* 000000ff SRC_ADDRESS_HIGH */  in nv50_gr_construct_mmio_ddata()
810 	dd_emit(ctx, 1, 0);	/* 00000001 SRC_SRGB */  in nv50_gr_construct_mmio_ddata()
811 	if (device->chipset >= 0x94)  in nv50_gr_construct_mmio_ddata()
812 		dd_emit(ctx, 1, 0);	/* 00000003 eng2d UNK0258 */  in nv50_gr_construct_mmio_ddata()
814 	dd_emit(ctx, 1, 0x100);	/* 0000ffff SRC_HEIGHT */  in nv50_gr_construct_mmio_ddata()
817 	dd_emit(ctx, 1, 0);		/* 0000000f TEXTURES_LOG2 */  in nv50_gr_construct_mmio_ddata()
818 	dd_emit(ctx, 1, 0);		/* 0000000f SAMPLERS_LOG2 */  in nv50_gr_construct_mmio_ddata()
819 	dd_emit(ctx, 1, 0);		/* 000000ff CB_DEF_ADDRESS_HIGH */  in nv50_gr_construct_mmio_ddata()
820 	dd_emit(ctx, 1, 0);		/* ffffffff CB_DEF_ADDRESS_LOW */  in nv50_gr_construct_mmio_ddata()
821 	dd_emit(ctx, 1, 0);		/* ffffffff SHARED_SIZE */  in nv50_gr_construct_mmio_ddata()
825 	dd_emit(ctx, 1, 0);		/* 000000ff UNK370 */  in nv50_gr_construct_mmio_ddata()
826 	dd_emit(ctx, 1, 0);		/* 000000ff USER_PARAM_UNK */  in nv50_gr_construct_mmio_ddata()
827 	dd_emit(ctx, 1, 0);		/* 000000ff USER_PARAM_COUNT */  in nv50_gr_construct_mmio_ddata()
829 	dd_emit(ctx, 1, 0x3fffff);	/* 003fffff TIC_LIMIT */  in nv50_gr_construct_mmio_ddata()
830 	dd_emit(ctx, 1, 0x1fff);	/* 000fffff TSC_LIMIT */  in nv50_gr_construct_mmio_ddata()
831 	dd_emit(ctx, 1, 0);		/* 0000ffff CB_ADDR_INDEX */  in nv50_gr_construct_mmio_ddata()
834 	dd_emit(ctx, 1, 0);		/* 00000001 BLOCKDIM_XMY_OVERFLOW */  in nv50_gr_construct_mmio_ddata()
841 		dd_emit(ctx, 1, 0);	/* 00000003 UNK03E8 */  in nv50_gr_construct_mmio_ddata()
852 	if (device->chipset == 0x50) {  in nv50_gr_construct_mmio_ddata()
853 		dd_emit(ctx, 4, 0);		/* 0000ffff clip X, Y, W, H */  in nv50_gr_construct_mmio_ddata()
858 		dd_emit(ctx, 1, 0);		/* ffffffff pattern SHAPE */  in nv50_gr_construct_mmio_ddata()
861 		dd_emit(ctx, 1, 0xa);		/* ffffffff surf2d SRC_FORMAT */  in nv50_gr_construct_mmio_ddata()
862 		dd_emit(ctx, 1, 0);		/* ffffffff surf2d DMA_SRC */  in nv50_gr_construct_mmio_ddata()
863 		dd_emit(ctx, 1, 0);		/* 000000ff surf2d SRC_ADDRESS_HIGH */  in nv50_gr_construct_mmio_ddata()
864 		dd_emit(ctx, 1, 0);		/* ffffffff surf2d SRC_ADDRESS_LOW */  in nv50_gr_construct_mmio_ddata()
865 		dd_emit(ctx, 1, 0x40);		/* 0000ffff surf2d SRC_PITCH */  in nv50_gr_construct_mmio_ddata()
866 		dd_emit(ctx, 1, 0);		/* 0000000f surf2d SRC_TILE_MODE_Z */  in nv50_gr_construct_mmio_ddata()
868 		dd_emit(ctx, 1, 0x100);		/* ffffffff surf2d SRC_HEIGHT */  in nv50_gr_construct_mmio_ddata()
870 		dd_emit(ctx, 1, 0x100);		/* ffffffff surf2d SRC_WIDTH */  in nv50_gr_construct_mmio_ddata()
872 		dd_emit(ctx, 1, 0);		/* 0000ffff gdirect CLIP_B_X */  in nv50_gr_construct_mmio_ddata()
873 		dd_emit(ctx, 1, 0);		/* 0000ffff gdirect CLIP_B_Y */  in nv50_gr_construct_mmio_ddata()
874 		dd_emit(ctx, 1, 0);		/* 0000ffff gdirect CLIP_C_X */  in nv50_gr_construct_mmio_ddata()
875 		dd_emit(ctx, 1, 0);		/* 0000ffff gdirect CLIP_C_Y */  in nv50_gr_construct_mmio_ddata()
876 		dd_emit(ctx, 1, 0);		/* 0000ffff gdirect CLIP_D_X */  in nv50_gr_construct_mmio_ddata()
877 		dd_emit(ctx, 1, 0);		/* 0000ffff gdirect CLIP_D_Y */  in nv50_gr_construct_mmio_ddata()
879 		dd_emit(ctx, 1, 0);		/* ffffffff gdirect OPERATION */  in nv50_gr_construct_mmio_ddata()
880 		dd_emit(ctx, 1, 0);		/* 0000ffff gdirect POINT_X */  in nv50_gr_construct_mmio_ddata()
881 		dd_emit(ctx, 1, 0);		/* 0000ffff gdirect POINT_Y */  in nv50_gr_construct_mmio_ddata()
883 		dd_emit(ctx, 1, 0);		/* 0000ffff blit SRC_Y */  in nv50_gr_construct_mmio_ddata()
884 		dd_emit(ctx, 1, 0);		/* ffffffff blit OPERATION */  in nv50_gr_construct_mmio_ddata()
886 		dd_emit(ctx, 1, 0);		/* ffffffff ifc OPERATION */  in nv50_gr_construct_mmio_ddata()
888 		dd_emit(ctx, 1, 0);		/* ffffffff iifc INDEX_FORMAT */  in nv50_gr_construct_mmio_ddata()
889 		dd_emit(ctx, 1, 0);		/* ffffffff iifc LUT_OFFSET */  in nv50_gr_construct_mmio_ddata()
891 		dd_emit(ctx, 1, 0);		/* ffffffff iifc OPERATION */  in nv50_gr_construct_mmio_ddata()
895 	dd_emit(ctx, 1, 0);		/* ffffffff m2mf LINE_COUNT */  in nv50_gr_construct_mmio_ddata()
896 	dd_emit(ctx, 1, 0);		/* ffffffff m2mf LINE_LENGTH_IN */  in nv50_gr_construct_mmio_ddata()
897 	dd_emit(ctx, 2, 0);		/* ffffffff m2mf OFFSET_IN, OFFSET_OUT */  in nv50_gr_construct_mmio_ddata()
899 	dd_emit(ctx, 1, 0x100);		/* ffffffff m2mf TILING_HEIGHT_OUT */  in nv50_gr_construct_mmio_ddata()
900 	dd_emit(ctx, 1, 0);		/* ffffffff m2mf TILING_POSITION_OUT_Z */  in nv50_gr_construct_mmio_ddata()
902 	dd_emit(ctx, 2, 0);		/* 0000ffff m2mf TILING_POSITION_OUT_X, Y */  in nv50_gr_construct_mmio_ddata()
903 	dd_emit(ctx, 1, 0x100);		/* ffffffff m2mf TILING_PITCH_OUT */  in nv50_gr_construct_mmio_ddata()
905 	dd_emit(ctx, 1, 0x100);		/* ffffffff m2mf TILING_HEIGHT_IN */  in nv50_gr_construct_mmio_ddata()
906 	dd_emit(ctx, 1, 0);		/* ffffffff m2mf TILING_POSITION_IN_Z */  in nv50_gr_construct_mmio_ddata()
908 	dd_emit(ctx, 2, 0);		/* 0000ffff m2mf TILING_POSITION_IN_X, Y */  in nv50_gr_construct_mmio_ddata()
909 	dd_emit(ctx, 1, 0x100);		/* ffffffff m2mf TILING_PITCH_IN */  in nv50_gr_construct_mmio_ddata()
912 	if (device->chipset == 0x50) {  in nv50_gr_construct_mmio_ddata()
914 		dd_emit(ctx, 1, 0);		/* ffffffff line OPERATION */  in nv50_gr_construct_mmio_ddata()
917 		dd_emit(ctx, 1, 0);		/* ffffffff triangle OPERATION */  in nv50_gr_construct_mmio_ddata()
919 		dd_emit(ctx, 1, 0);		/* 0000000f sifm TILE_MODE_Z */  in nv50_gr_construct_mmio_ddata()
921 		dd_emit(ctx, 1, 0);		/* 000000ff sifm FORMAT_FILTER */  in nv50_gr_construct_mmio_ddata()
923 		dd_emit(ctx, 1, 0);		/* 0000ffff sifm SRC_PITCH */  in nv50_gr_construct_mmio_ddata()
925 		dd_emit(ctx, 1, 0);		/* 000000ff sifm SRC_OFFSET_HIGH */  in nv50_gr_construct_mmio_ddata()
926 		dd_emit(ctx, 1, 0);		/* ffffffff sifm SRC_OFFSET */  in nv50_gr_construct_mmio_ddata()
927 		dd_emit(ctx, 1, 0);		/* 0000ffff sifm SRC_HEIGHT */  in nv50_gr_construct_mmio_ddata()
928 		dd_emit(ctx, 1, 0);		/* 0000ffff sifm SRC_WIDTH */  in nv50_gr_construct_mmio_ddata()
930 		dd_emit(ctx, 1, 0);		/* ffffffff sifm OPERATION */  in nv50_gr_construct_mmio_ddata()
932 		dd_emit(ctx, 1, 0);		/* ffffffff sifc OPERATION */  in nv50_gr_construct_mmio_ddata()
936 	dd_emit(ctx, 1, 0);		/* 0000000f GP_TEXTURES_LOG2 */  in nv50_gr_construct_mmio_ddata()
937 	dd_emit(ctx, 1, 0);		/* 0000000f GP_SAMPLERS_LOG2 */  in nv50_gr_construct_mmio_ddata()
938 	dd_emit(ctx, 1, 0);		/* 000000ff */  in nv50_gr_construct_mmio_ddata()
939 	dd_emit(ctx, 1, 0);		/* ffffffff */  in nv50_gr_construct_mmio_ddata()
941 	dd_emit(ctx, 1, 0x70);		/* 000000ff UNK12B0_1 */  in nv50_gr_construct_mmio_ddata()
942 	dd_emit(ctx, 1, 0x80);		/* 000000ff UNK12B0_3 */  in nv50_gr_construct_mmio_ddata()
943 	dd_emit(ctx, 1, 0);		/* 000000ff UNK12B0_2 */  in nv50_gr_construct_mmio_ddata()
944 	dd_emit(ctx, 1, 0);		/* 0000000f FP_TEXTURES_LOG2 */  in nv50_gr_construct_mmio_ddata()
945 	dd_emit(ctx, 1, 0);		/* 0000000f FP_SAMPLERS_LOG2 */  in nv50_gr_construct_mmio_ddata()
947 		dd_emit(ctx, 1, 0);	/* ffffffff */  in nv50_gr_construct_mmio_ddata()
948 		dd_emit(ctx, 1, 0);	/* 0000007f MULTISAMPLE_SAMPLES_LOG2 */  in nv50_gr_construct_mmio_ddata()
950 		dd_emit(ctx, 1, 0);	/* 0000000f MULTISAMPLE_SAMPLES_LOG2 */  in nv50_gr_construct_mmio_ddata()
952 	dd_emit(ctx, 1, 0xc);		/* 000000ff SEMANTIC_COLOR.BFC0_ID */  in nv50_gr_construct_mmio_ddata()
953 	if (device->chipset != 0x50)  in nv50_gr_construct_mmio_ddata()
954 		dd_emit(ctx, 1, 0);	/* 00000001 SEMANTIC_COLOR.CLMP_EN */  in nv50_gr_construct_mmio_ddata()
956 	dd_emit(ctx, 1, 0x14);		/* 000000ff SEMANTIC_COLOR.FFC0_ID */  in nv50_gr_construct_mmio_ddata()
957 	if (device->chipset == 0x50) {  in nv50_gr_construct_mmio_ddata()
958 		dd_emit(ctx, 1, 0);	/* 000000ff SEMANTIC_LAYER */  in nv50_gr_construct_mmio_ddata()
959 		dd_emit(ctx, 1, 0);	/* 00000001 */  in nv50_gr_construct_mmio_ddata()
961 		dd_emit(ctx, 1, 0);	/* 00000001 SEMANTIC_PTSZ.ENABLE */  in nv50_gr_construct_mmio_ddata()
962 		dd_emit(ctx, 1, 0x29);	/* 000000ff SEMANTIC_PTSZ.PTSZ_ID */  in nv50_gr_construct_mmio_ddata()
963 		dd_emit(ctx, 1, 0x27);	/* 000000ff SEMANTIC_PRIM */  in nv50_gr_construct_mmio_ddata()
964 		dd_emit(ctx, 1, 0x26);	/* 000000ff SEMANTIC_LAYER */  in nv50_gr_construct_mmio_ddata()
967 		dd_emit(ctx, 1, 0x27);	/* 000000ff UNK0FD4 */  in nv50_gr_construct_mmio_ddata()
968 		dd_emit(ctx, 1, 0);	/* 00000001 UNK1900 */  in nv50_gr_construct_mmio_ddata()
970 	dd_emit(ctx, 1, 0);		/* 00000007 RT_CONTROL_MAP0 */  in nv50_gr_construct_mmio_ddata()
979 	dd_emit(ctx, 8, 0);		/* 00000001 RT_HORIZ_UNK */  in nv50_gr_construct_mmio_ddata()
980 	dd_emit(ctx, 8, 0);		/* ffffffff RT_ADDRESS_LOW */  in nv50_gr_construct_mmio_ddata()
981 	dd_emit(ctx, 1, 0xcf);		/* 000000ff RT_FORMAT */  in nv50_gr_construct_mmio_ddata()
982 	dd_emit(ctx, 7, 0);		/* 000000ff RT_FORMAT */  in nv50_gr_construct_mmio_ddata()
983 	if (device->chipset != 0x50)  in nv50_gr_construct_mmio_ddata()
984 		dd_emit(ctx, 3, 0);	/* 1, 1, 1 */  in nv50_gr_construct_mmio_ddata()
986 		dd_emit(ctx, 2, 0);	/* 1, 1 */  in nv50_gr_construct_mmio_ddata()
987 	dd_emit(ctx, 1, 0);		/* ffffffff GP_ENABLE */  in nv50_gr_construct_mmio_ddata()
988 	dd_emit(ctx, 1, 0x80);		/* 0000ffff GP_VERTEX_OUTPUT_COUNT*/  in nv50_gr_construct_mmio_ddata()
993 		dd_emit(ctx, 1, 0);	/* 00000001 UNK1418. Alone. */  in nv50_gr_construct_mmio_ddata()
995 	if (device->chipset != 0x50)  in nv50_gr_construct_mmio_ddata()
998 	dd_emit(ctx, 1, 0);		/* 00000001 FP_CONTROL.EXPORTS_Z */  in nv50_gr_construct_mmio_ddata()
999 	if (device->chipset != 0x50)  in nv50_gr_construct_mmio_ddata()
1000 		dd_emit(ctx, 1, 0);	/* 00000001 FP_CONTROL.MULTIPLE_RESULTS */  in nv50_gr_construct_mmio_ddata()
1001 	dd_emit(ctx, 1, 0x12);		/* 000000ff FP_INTERPOLANT_CTRL.COUNT */  in nv50_gr_construct_mmio_ddata()
1002 	dd_emit(ctx, 1, 0x10);		/* 000000ff FP_INTERPOLANT_CTRL.COUNT_NONFLAT */  in nv50_gr_construct_mmio_ddata()
1003 	dd_emit(ctx, 1, 0xc);		/* 000000ff FP_INTERPOLANT_CTRL.OFFSET */  in nv50_gr_construct_mmio_ddata()
1005 	dd_emit(ctx, 1, 0);		/* 00000001 FP_INTERPOLANT_CTRL.UMASK.X */  in nv50_gr_construct_mmio_ddata()
1006 	dd_emit(ctx, 1, 0);		/* 00000001 FP_INTERPOLANT_CTRL.UMASK.Y */  in nv50_gr_construct_mmio_ddata()
1007 	dd_emit(ctx, 1, 0);		/* 00000001 FP_INTERPOLANT_CTRL.UMASK.Z */  in nv50_gr_construct_mmio_ddata()
1011 	if (device->chipset >= 0xa0)  in nv50_gr_construct_mmio_ddata()
1012 		dd_emit(ctx, 1, 0);	/* ffffffff */  in nv50_gr_construct_mmio_ddata()
1013 	dd_emit(ctx, 1, 0);		/* 00000001 GP_BUILTIN_RESULT_EN.LAYER_IDX */  in nv50_gr_construct_mmio_ddata()
1014 	dd_emit(ctx, 1, 0);		/* ffffffff STRMOUT_ENABLE */  in nv50_gr_construct_mmio_ddata()
1015 	dd_emit(ctx, 1, 0x3fffff);	/* 003fffff TIC_LIMIT */  in nv50_gr_construct_mmio_ddata()
1016 	dd_emit(ctx, 1, 0x1fff);	/* 000fffff TSC_LIMIT */  in nv50_gr_construct_mmio_ddata()
1017 	dd_emit(ctx, 1, 0);		/* 00000001 VERTEX_TWO_SIDE_ENABLE*/  in nv50_gr_construct_mmio_ddata()
1018 	if (device->chipset != 0x50)  in nv50_gr_construct_mmio_ddata()
1019 		dd_emit(ctx, 8, 0);	/* 00000001 */  in nv50_gr_construct_mmio_ddata()
1020 	if (device->chipset >= 0xa0) {  in nv50_gr_construct_mmio_ddata()
1024 		dd_emit(ctx, 1, 0);	/* 000000ff VTX_ATTR_DEFINE.ATTR */  in nv50_gr_construct_mmio_ddata()
1027 	dd_emit(ctx, 1, 0x14);		/* 0000001f ZETA_FORMAT */  in nv50_gr_construct_mmio_ddata()
1029 	dd_emit(ctx, 1, 0);		/* 0000000f VP_TEXTURES_LOG2 */  in nv50_gr_construct_mmio_ddata()
1030 	dd_emit(ctx, 1, 0);		/* 0000000f VP_SAMPLERS_LOG2 */  in nv50_gr_construct_mmio_ddata()
1032 		dd_emit(ctx, 1, 0);	/* 00000001 */  in nv50_gr_construct_mmio_ddata()
1034 	if (device->chipset >= 0xa0)  in nv50_gr_construct_mmio_ddata()
1035 		dd_emit(ctx, 1, 0);	/* 00000003 VTX_ATTR_DEFINE.SIZE - 1 */  in nv50_gr_construct_mmio_ddata()
1036 	dd_emit(ctx, 1, 0);		/* 0000ffff CB_ADDR_INDEX */  in nv50_gr_construct_mmio_ddata()
1037 	if (device->chipset >= 0xa0)  in nv50_gr_construct_mmio_ddata()
1038 		dd_emit(ctx, 1, 0);	/* 00000003 */  in nv50_gr_construct_mmio_ddata()
1039 	dd_emit(ctx, 1, 0);		/* 00000001 CULL_FACE_ENABLE */  in nv50_gr_construct_mmio_ddata()
1041 	dd_emit(ctx, 1, 0);		/* 00000001 FRONT_FACE */  in nv50_gr_construct_mmio_ddata()
1043 	dd_emit(ctx, 1, 0x1000);	/* 00007fff UNK141C */  in nv50_gr_construct_mmio_ddata()
1044 	if (device->chipset != 0x50) {  in nv50_gr_construct_mmio_ddata()
1045 		dd_emit(ctx, 1, 0xe00);		/* 7fff */  in nv50_gr_construct_mmio_ddata()
1046 		dd_emit(ctx, 1, 0x1000);	/* 7fff */  in nv50_gr_construct_mmio_ddata()
1047 		dd_emit(ctx, 1, 0x1e00);	/* 7fff */  in nv50_gr_construct_mmio_ddata()
1049 	dd_emit(ctx, 1, 0);		/* 00000001 BEGIN_END_ACTIVE */  in nv50_gr_construct_mmio_ddata()
1055 	dd_emit(ctx, 1, 0);		/* 00000001 */  in nv50_gr_construct_mmio_ddata()
1056 	dd_emit(ctx, 1, 0);		/* 00000001 VTX_ATTR_MASK_UNK0 nonempty */  in nv50_gr_construct_mmio_ddata()
1057 	dd_emit(ctx, 1, 0);		/* 00000001 VTX_ATTR_MASK_UNK1 nonempty */  in nv50_gr_construct_mmio_ddata()
1058 	dd_emit(ctx, 1, 0x200);		/* 0003ffff GP_VERTEX_OUTPUT_COUNT*GP_REG_ALLOC_RESULT */  in nv50_gr_construct_mmio_ddata()
1060 		dd_emit(ctx, 1, 0x200);  in nv50_gr_construct_mmio_ddata()
1061 	dd_emit(ctx, 1, 0);		/* 00000001 */  in nv50_gr_construct_mmio_ddata()
1062 	if (device->chipset < 0xa0) {  in nv50_gr_construct_mmio_ddata()
1064 		dd_emit(ctx, 1, 0x70);	/* 000000ff */  in nv50_gr_construct_mmio_ddata()
1065 		dd_emit(ctx, 1, 0x80);	/* 000000ff */  in nv50_gr_construct_mmio_ddata()
1066 		dd_emit(ctx, 1, 0);	/* 000000ff */  in nv50_gr_construct_mmio_ddata()
1067 		dd_emit(ctx, 1, 0);	/* 00000001 */  in nv50_gr_construct_mmio_ddata()
1069 		dd_emit(ctx, 1, 0x70);	/* 000000ff */  in nv50_gr_construct_mmio_ddata()
1070 		dd_emit(ctx, 1, 0x80);	/* 000000ff */  in nv50_gr_construct_mmio_ddata()
1071 		dd_emit(ctx, 1, 0);	/* 000000ff */  in nv50_gr_construct_mmio_ddata()
1074 		dd_emit(ctx, 1, 0xf0);	/* 000000ff */  in nv50_gr_construct_mmio_ddata()
1075 		dd_emit(ctx, 1, 0xff);	/* 000000ff */  in nv50_gr_construct_mmio_ddata()
1076 		dd_emit(ctx, 1, 0);	/* 000000ff */  in nv50_gr_construct_mmio_ddata()
1077 		dd_emit(ctx, 1, 0);	/* 00000001 */  in nv50_gr_construct_mmio_ddata()
1079 		dd_emit(ctx, 1, 0xf0);	/* 000000ff */  in nv50_gr_construct_mmio_ddata()
1080 		dd_emit(ctx, 1, 0xff);	/* 000000ff */  in nv50_gr_construct_mmio_ddata()
1081 		dd_emit(ctx, 1, 0);	/* 000000ff */  in nv50_gr_construct_mmio_ddata()
1086 	dd_emit(ctx, 1, 0);		/* 00000001 eng2d COLOR_KEY_ENABLE */  in nv50_gr_construct_mmio_ddata()
1087 	dd_emit(ctx, 1, 0);		/* 00000007 eng2d COLOR_KEY_FORMAT */  in nv50_gr_construct_mmio_ddata()
1089 	dd_emit(ctx, 1, 0xcf);		/* 000000ff eng2d DST_FORMAT */  in nv50_gr_construct_mmio_ddata()
1090 	dd_emit(ctx, 1, 0);		/* ffffffff eng2d DST_LAYER */  in nv50_gr_construct_mmio_ddata()
1092 	dd_emit(ctx, 1, 0);		/* 00000007 eng2d PATTERN_COLOR_FORMAT */  in nv50_gr_construct_mmio_ddata()
1093 	dd_emit(ctx, 1, 0);		/* 00000007 eng2d OPERATION */  in nv50_gr_construct_mmio_ddata()
1094 	dd_emit(ctx, 1, 0);		/* 00000003 eng2d PATTERN_SELECT */  in nv50_gr_construct_mmio_ddata()
1095 	dd_emit(ctx, 1, 0xcf);		/* 000000ff eng2d SIFC_FORMAT */  in nv50_gr_construct_mmio_ddata()
1096 	dd_emit(ctx, 1, 0);		/* 00000001 eng2d SIFC_BITMAP_ENABLE */  in nv50_gr_construct_mmio_ddata()
1098 	dd_emit(ctx, 1, 0);		/* ffffffff eng2d BLIT_DU_DX_FRACT */  in nv50_gr_construct_mmio_ddata()
1100 	dd_emit(ctx, 1, 0);		/* ffffffff eng2d BLIT_DV_DY_FRACT */  in nv50_gr_construct_mmio_ddata()
1102 	dd_emit(ctx, 1, 0);		/* 00000001 eng2d BLIT_CONTROL_FILTER */  in nv50_gr_construct_mmio_ddata()
1103 	dd_emit(ctx, 1, 0xcf);		/* 000000ff eng2d DRAW_COLOR_FORMAT */  in nv50_gr_construct_mmio_ddata()
1104 	dd_emit(ctx, 1, 0xcf);		/* 000000ff eng2d SRC_FORMAT */  in nv50_gr_construct_mmio_ddata()
1110 		cp_ctx(ctx, 0x404800, num);  in nv50_gr_construct_mmio_ddata()
1112 		cp_ctx(ctx, 0x405400, num);  in nv50_gr_construct_mmio_ddata()
1138  * The most common value in default context is 0, and when the genes
1139  * are separated by 0's, gene bounduaries are quite speculative...
1143  * is unknown. Except for strand 0, which is the longest strand and
1161 		for (i = 0; i < num; i++)  in xf_emit()
1194 	int size = 0;  in nv50_gr_construct_xfer1()
1195 	u32 units = nvkm_rd32(device, 0x1540);  in nv50_gr_construct_xfer1()
1197 	offset = (ctx->ctxvals_pos+0x3f)&~0x3f;  in nv50_gr_construct_xfer1()
1200 	if (device->chipset < 0xa0) {  in nv50_gr_construct_xfer1()
1201 		/* Strand 0 */  in nv50_gr_construct_xfer1()
1212 		ctx->ctxvals_pos = offset + 0x1;  in nv50_gr_construct_xfer1()
1222 		ctx->ctxvals_pos = offset + 0x2;  in nv50_gr_construct_xfer1()
1234 		for (i = 0; i < 6; i++)  in nv50_gr_construct_xfer1()
1241 		for (i = 0; i < 4; i++) {  in nv50_gr_construct_xfer1()
1251 		/* Strand 0 */  in nv50_gr_construct_xfer1()
1270 		if (device->chipset == 0xa0)  in nv50_gr_construct_xfer1()
1293 		for (i = 0; i < 8; i++)  in nv50_gr_construct_xfer1()
1304 		if (units & (1 << 0))  in nv50_gr_construct_xfer1()
1317 		if (device->chipset == 0xa0) {  in nv50_gr_construct_xfer1()
1338 	ctx->ctxvals_pos = (ctx->ctxvals_pos+0x3f)&~0x3f;  in nv50_gr_construct_xfer1()
1354 	/* start of strand 0 */  in nv50_gr_construct_gene_dispatch()
1357 	if (device->chipset == 0x50)  in nv50_gr_construct_gene_dispatch()
1358 		xf_emit(ctx, 5, 0);  in nv50_gr_construct_gene_dispatch()
1360 		xf_emit(ctx, 6, 0);  in nv50_gr_construct_gene_dispatch()
1362 		xf_emit(ctx, 4, 0);  in nv50_gr_construct_gene_dispatch()
1365 	if (device->chipset == 0x50)  in nv50_gr_construct_gene_dispatch()
1366 		xf_emit(ctx, 8*3, 0);  in nv50_gr_construct_gene_dispatch()
1368 		xf_emit(ctx, 0x100*3, 0);  in nv50_gr_construct_gene_dispatch()
1370 	xf_emit(ctx, 3, 0);  in nv50_gr_construct_gene_dispatch()
1373 		xf_emit(ctx, 3, 0);  in nv50_gr_construct_gene_dispatch()
1376 	xf_emit(ctx, 9, 0);  in nv50_gr_construct_gene_dispatch()
1378 	xf_emit(ctx, 9, 0);  in nv50_gr_construct_gene_dispatch()
1380 	xf_emit(ctx, 9, 0);  in nv50_gr_construct_gene_dispatch()
1382 	xf_emit(ctx, 9, 0);  in nv50_gr_construct_gene_dispatch()
1384 	if (device->chipset < 0x90)  in nv50_gr_construct_gene_dispatch()
1385 		xf_emit(ctx, 4, 0);  in nv50_gr_construct_gene_dispatch()
1387 	xf_emit(ctx, 2, 0);  in nv50_gr_construct_gene_dispatch()
1389 	xf_emit(ctx, 6*2, 0);  in nv50_gr_construct_gene_dispatch()
1390 	xf_emit(ctx, 2, 0);  in nv50_gr_construct_gene_dispatch()
1392 	xf_emit(ctx, 2, 0);  in nv50_gr_construct_gene_dispatch()
1394 	xf_emit(ctx, 6*2, 0);  in nv50_gr_construct_gene_dispatch()
1395 	xf_emit(ctx, 2, 0);  in nv50_gr_construct_gene_dispatch()
1397 	if (device->chipset == 0x50)  in nv50_gr_construct_gene_dispatch()
1398 		xf_emit(ctx, 0x1c, 0);  in nv50_gr_construct_gene_dispatch()
1399 	else if (device->chipset < 0xa0)  in nv50_gr_construct_gene_dispatch()
1400 		xf_emit(ctx, 0x1e, 0);  in nv50_gr_construct_gene_dispatch()
1402 		xf_emit(ctx, 0x22, 0);  in nv50_gr_construct_gene_dispatch()
1404 	xf_emit(ctx, 0x15, 0);  in nv50_gr_construct_gene_dispatch()
1410 	/* Strand 0, right after dispatch */  in nv50_gr_construct_gene_m2mf()
1412 	int smallm2mf = 0;  in nv50_gr_construct_gene_m2mf()
1413 	if (device->chipset < 0x92 || device->chipset == 0x98)  in nv50_gr_construct_gene_m2mf()
1416 	xf_emit (ctx, 1, 0);		/* DMA_NOTIFY instance >> 4 */  in nv50_gr_construct_gene_m2mf()
1417 	xf_emit (ctx, 1, 0);		/* DMA_BUFFER_IN instance >> 4 */  in nv50_gr_construct_gene_m2mf()
1418 	xf_emit (ctx, 1, 0);		/* DMA_BUFFER_OUT instance >> 4 */  in nv50_gr_construct_gene_m2mf()
1419 	xf_emit (ctx, 1, 0);		/* OFFSET_IN */  in nv50_gr_construct_gene_m2mf()
1420 	xf_emit (ctx, 1, 0);		/* OFFSET_OUT */  in nv50_gr_construct_gene_m2mf()
1421 	xf_emit (ctx, 1, 0);		/* PITCH_IN */  in nv50_gr_construct_gene_m2mf()
1422 	xf_emit (ctx, 1, 0);		/* PITCH_OUT */  in nv50_gr_construct_gene_m2mf()
1423 	xf_emit (ctx, 1, 0);		/* LINE_LENGTH */  in nv50_gr_construct_gene_m2mf()
1424 	xf_emit (ctx, 1, 0);		/* LINE_COUNT */  in nv50_gr_construct_gene_m2mf()
1425 	xf_emit (ctx, 1, 0x21);		/* FORMAT: bits 0-4 INPUT_INC, bits 5-9 OUTPUT_INC */  in nv50_gr_construct_gene_m2mf()
1427 	xf_emit (ctx, 1, 0x2);		/* TILING_MODE_IN: bits 0-2 y tiling, bits 3-5 z tiling */  in nv50_gr_construct_gene_m2mf()
1428 	xf_emit (ctx, 1, 0x100);	/* TILING_PITCH_IN */  in nv50_gr_construct_gene_m2mf()
1429 	xf_emit (ctx, 1, 0x100);	/* TILING_HEIGHT_IN */  in nv50_gr_construct_gene_m2mf()
1431 	xf_emit (ctx, 1, 0);		/* TILING_POSITION_IN_Z */  in nv50_gr_construct_gene_m2mf()
1432 	xf_emit (ctx, 1, 0);		/* TILING_POSITION_IN */  in nv50_gr_construct_gene_m2mf()
1434 	xf_emit (ctx, 1, 0x2);		/* TILING_MODE_OUT: bits 0-2 y tiling, bits 3-5 z tiling */  in nv50_gr_construct_gene_m2mf()
1435 	xf_emit (ctx, 1, 0x100);	/* TILING_PITCH_OUT */  in nv50_gr_construct_gene_m2mf()
1436 	xf_emit (ctx, 1, 0x100);	/* TILING_HEIGHT_OUT */  in nv50_gr_construct_gene_m2mf()
1438 	xf_emit (ctx, 1, 0);		/* TILING_POSITION_OUT_Z */  in nv50_gr_construct_gene_m2mf()
1439 	xf_emit (ctx, 1, 0);		/* TILING_POSITION_OUT */  in nv50_gr_construct_gene_m2mf()
1440 	xf_emit (ctx, 1, 0);		/* OFFSET_IN_HIGH */  in nv50_gr_construct_gene_m2mf()
1441 	xf_emit (ctx, 1, 0);		/* OFFSET_OUT_HIGH */  in nv50_gr_construct_gene_m2mf()
1444 		xf_emit(ctx, 0x40, 0);	/* 20 * ffffffff, 3ffff */  in nv50_gr_construct_gene_m2mf()
1446 		xf_emit(ctx, 0x100, 0);	/* 80 * ffffffff, 3ffff */  in nv50_gr_construct_gene_m2mf()
1447 	xf_emit(ctx, 4, 0);		/* 1f/7f, 0, 1f/7f, 0 [1f for smallm2mf, 7f otherwise] */  in nv50_gr_construct_gene_m2mf()
1450 		xf_emit(ctx, 0x400, 0);	/* ffffffff */  in nv50_gr_construct_gene_m2mf()
1452 		xf_emit(ctx, 0x800, 0);	/* ffffffff */  in nv50_gr_construct_gene_m2mf()
1453 	xf_emit(ctx, 4, 0);		/* ff/1ff, 0, 0, 0 [ff for smallm2mf, 1ff otherwise] */  in nv50_gr_construct_gene_m2mf()
1455 	xf_emit(ctx, 0x40, 0);		/* 20 * bits ffffffff, 3ffff */  in nv50_gr_construct_gene_m2mf()
1456 	xf_emit(ctx, 0x6, 0);		/* 1f, 0, 1f, 0, 1f, 0 */  in nv50_gr_construct_gene_m2mf()
1463 	xf_emit(ctx, 2, 0);		/* RO */  in nv50_gr_construct_gene_ccache()
1464 	xf_emit(ctx, 0x800, 0);		/* ffffffff */  in nv50_gr_construct_gene_ccache()
1466 	case 0x50:  in nv50_gr_construct_gene_ccache()
1467 	case 0x92:  in nv50_gr_construct_gene_ccache()
1468 	case 0xa0:  in nv50_gr_construct_gene_ccache()
1469 		xf_emit(ctx, 0x2b, 0);  in nv50_gr_construct_gene_ccache()
1471 	case 0x84:  in nv50_gr_construct_gene_ccache()
1472 		xf_emit(ctx, 0x29, 0);  in nv50_gr_construct_gene_ccache()
1474 	case 0x94:  in nv50_gr_construct_gene_ccache()
1475 	case 0x96:  in nv50_gr_construct_gene_ccache()
1476 	case 0xa3:  in nv50_gr_construct_gene_ccache()
1477 		xf_emit(ctx, 0x27, 0);  in nv50_gr_construct_gene_ccache()
1479 	case 0x86:  in nv50_gr_construct_gene_ccache()
1480 	case 0x98:  in nv50_gr_construct_gene_ccache()
1481 	case 0xa5:  in nv50_gr_construct_gene_ccache()
1482 	case 0xa8:  in nv50_gr_construct_gene_ccache()
1483 	case 0xaa:  in nv50_gr_construct_gene_ccache()
1484 	case 0xac:  in nv50_gr_construct_gene_ccache()
1485 	case 0xaf:  in nv50_gr_construct_gene_ccache()
1486 		xf_emit(ctx, 0x25, 0);  in nv50_gr_construct_gene_ccache()
1489 	/* CB bindings, 0x80 of them. first word is address >> 8, second is  in nv50_gr_construct_gene_ccache()
1491 	xf_emit(ctx, 0x100, 0);		/* ffffffff CB_DEF */  in nv50_gr_construct_gene_ccache()
1492 	xf_emit(ctx, 1, 0);		/* 0000007f CB_ADDR_BUFFER */  in nv50_gr_construct_gene_ccache()
1493 	xf_emit(ctx, 1, 0);		/* 0 */  in nv50_gr_construct_gene_ccache()
1494 	xf_emit(ctx, 0x30, 0);		/* ff SET_PROGRAM_CB */  in nv50_gr_construct_gene_ccache()
1495 	xf_emit(ctx, 1, 0);		/* 3f last SET_PROGRAM_CB */  in nv50_gr_construct_gene_ccache()
1496 	xf_emit(ctx, 4, 0);		/* RO */  in nv50_gr_construct_gene_ccache()
1497 	xf_emit(ctx, 0x100, 0);		/* ffffffff */  in nv50_gr_construct_gene_ccache()
1498 	xf_emit(ctx, 8, 0);		/* 1f, 0, 0, ... */  in nv50_gr_construct_gene_ccache()
1499 	xf_emit(ctx, 8, 0);		/* ffffffff */  in nv50_gr_construct_gene_ccache()
1500 	xf_emit(ctx, 4, 0);		/* ffffffff */  in nv50_gr_construct_gene_ccache()
1501 	xf_emit(ctx, 1, 0);		/* 3 */  in nv50_gr_construct_gene_ccache()
1502 	xf_emit(ctx, 1, 0);		/* ffffffff */  in nv50_gr_construct_gene_ccache()
1503 	xf_emit(ctx, 1, 0);		/* 0000ffff DMA_CODE_CB */  in nv50_gr_construct_gene_ccache()
1504 	xf_emit(ctx, 1, 0);		/* 0000ffff DMA_TIC */  in nv50_gr_construct_gene_ccache()
1505 	xf_emit(ctx, 1, 0);		/* 0000ffff DMA_TSC */  in nv50_gr_construct_gene_ccache()
1506 	xf_emit(ctx, 1, 0);		/* 00000001 LINKED_TSC */  in nv50_gr_construct_gene_ccache()
1507 	xf_emit(ctx, 1, 0);		/* 000000ff TIC_ADDRESS_HIGH */  in nv50_gr_construct_gene_ccache()
1508 	xf_emit(ctx, 1, 0);		/* ffffffff TIC_ADDRESS_LOW */  in nv50_gr_construct_gene_ccache()
1509 	xf_emit(ctx, 1, 0x3fffff);	/* 003fffff TIC_LIMIT */  in nv50_gr_construct_gene_ccache()
1510 	xf_emit(ctx, 1, 0);		/* 000000ff TSC_ADDRESS_HIGH */  in nv50_gr_construct_gene_ccache()
1511 	xf_emit(ctx, 1, 0);		/* ffffffff TSC_ADDRESS_LOW */  in nv50_gr_construct_gene_ccache()
1512 	xf_emit(ctx, 1, 0x1fff);	/* 000fffff TSC_LIMIT */  in nv50_gr_construct_gene_ccache()
1513 	xf_emit(ctx, 1, 0);		/* 000000ff VP_ADDRESS_HIGH */  in nv50_gr_construct_gene_ccache()
1514 	xf_emit(ctx, 1, 0);		/* ffffffff VP_ADDRESS_LOW */  in nv50_gr_construct_gene_ccache()
1515 	xf_emit(ctx, 1, 0);		/* 00ffffff VP_START_ID */  in nv50_gr_construct_gene_ccache()
1516 	xf_emit(ctx, 1, 0);		/* 000000ff CB_DEF_ADDRESS_HIGH */  in nv50_gr_construct_gene_ccache()
1517 	xf_emit(ctx, 1, 0);		/* ffffffff CB_DEF_ADDRESS_LOW */  in nv50_gr_construct_gene_ccache()
1518 	xf_emit(ctx, 1, 0);		/* 00000001 GP_ENABLE */  in nv50_gr_construct_gene_ccache()
1519 	xf_emit(ctx, 1, 0);		/* 000000ff GP_ADDRESS_HIGH */  in nv50_gr_construct_gene_ccache()
1520 	xf_emit(ctx, 1, 0);		/* ffffffff GP_ADDRESS_LOW */  in nv50_gr_construct_gene_ccache()
1521 	xf_emit(ctx, 1, 0);		/* 00ffffff GP_START_ID */  in nv50_gr_construct_gene_ccache()
1522 	xf_emit(ctx, 1, 0);		/* 000000ff FP_ADDRESS_HIGH */  in nv50_gr_construct_gene_ccache()
1523 	xf_emit(ctx, 1, 0);		/* ffffffff FP_ADDRESS_LOW */  in nv50_gr_construct_gene_ccache()
1524 	xf_emit(ctx, 1, 0);		/* 00ffffff FP_START_ID */  in nv50_gr_construct_gene_ccache()
1535 	xf_emit(ctx, 1, 0);		/* 00000001 GP_ENABLE */  in nv50_gr_construct_gene_unk10xx()
1536 	xf_emit(ctx, 1, 0x80);		/* 0000ffff GP_VERTEX_OUTPUT_COUNT */  in nv50_gr_construct_gene_unk10xx()
1538 	xf_emit(ctx, 1, 0x80c14);	/* 01ffffff SEMANTIC_COLOR */  in nv50_gr_construct_gene_unk10xx()
1539 	xf_emit(ctx, 1, 0);		/* 00000001 VERTEX_TWO_SIDE_ENABLE */  in nv50_gr_construct_gene_unk10xx()
1540 	if (device->chipset == 0x50)  in nv50_gr_construct_gene_unk10xx()
1541 		xf_emit(ctx, 1, 0x3ff);  in nv50_gr_construct_gene_unk10xx()
1543 		xf_emit(ctx, 1, 0x7ff);	/* 000007ff */  in nv50_gr_construct_gene_unk10xx()
1544 	xf_emit(ctx, 1, 0);		/* 111/113 */  in nv50_gr_construct_gene_unk10xx()
1545 	xf_emit(ctx, 1, 0);		/* ffffffff tesla UNK1A30 */  in nv50_gr_construct_gene_unk10xx()
1546 	for (i = 0; i < 8; i++) {  in nv50_gr_construct_gene_unk10xx()
1548 		case 0x50:  in nv50_gr_construct_gene_unk10xx()
1549 		case 0x86:  in nv50_gr_construct_gene_unk10xx()
1550 		case 0x98:  in nv50_gr_construct_gene_unk10xx()
1551 		case 0xaa:  in nv50_gr_construct_gene_unk10xx()
1552 		case 0xac:  in nv50_gr_construct_gene_unk10xx()
1553 			xf_emit(ctx, 0xa0, 0);	/* ffffffff */  in nv50_gr_construct_gene_unk10xx()
1555 		case 0x84:  in nv50_gr_construct_gene_unk10xx()
1556 		case 0x92:  in nv50_gr_construct_gene_unk10xx()
1557 		case 0x94:  in nv50_gr_construct_gene_unk10xx()
1558 		case 0x96:  in nv50_gr_construct_gene_unk10xx()
1559 			xf_emit(ctx, 0x120, 0);  in nv50_gr_construct_gene_unk10xx()
1561 		case 0xa5:  in nv50_gr_construct_gene_unk10xx()
1562 		case 0xa8:  in nv50_gr_construct_gene_unk10xx()
1563 			xf_emit(ctx, 0x100, 0);	/* ffffffff */  in nv50_gr_construct_gene_unk10xx()
1565 		case 0xa0:  in nv50_gr_construct_gene_unk10xx()
1566 		case 0xa3:  in nv50_gr_construct_gene_unk10xx()
1567 		case 0xaf:  in nv50_gr_construct_gene_unk10xx()
1568 			xf_emit(ctx, 0x400, 0);	/* ffffffff */  in nv50_gr_construct_gene_unk10xx()
1571 		xf_emit(ctx, 4, 0);	/* 3f, 0, 0, 0 */  in nv50_gr_construct_gene_unk10xx()
1572 		xf_emit(ctx, 4, 0);	/* ffffffff */  in nv50_gr_construct_gene_unk10xx()
1576 	xf_emit(ctx, 1, 0);		/* 00000001 GP_ENABLE */  in nv50_gr_construct_gene_unk10xx()
1577 	xf_emit(ctx, 1, 0x80);		/* 0000ffff GP_VERTEX_OUTPUT_COUNT */  in nv50_gr_construct_gene_unk10xx()
1580 	xf_emit(ctx, 1, 0);		/* 00000001 tesla UNK1900 */  in nv50_gr_construct_gene_unk10xx()
1581 	xf_emit(ctx, 1, 0x27);		/* 000000ff UNK0FD4 */  in nv50_gr_construct_gene_unk10xx()
1582 	xf_emit(ctx, 1, 0);		/* 0001ffff GP_BUILTIN_RESULT_EN */  in nv50_gr_construct_gene_unk10xx()
1583 	xf_emit(ctx, 1, 0x26);		/* 000000ff SEMANTIC_LAYER */  in nv50_gr_construct_gene_unk10xx()
1584 	xf_emit(ctx, 1, 0);		/* ffffffff tesla UNK1A30 */  in nv50_gr_construct_gene_unk10xx()
1592 	xf_emit(ctx, 1, 0);		/* 00000001 VIEWPORT_CLIP_RECTS_EN */  in nv50_gr_construct_gene_unk34xx()
1593 	xf_emit(ctx, 1, 0);		/* 00000003 VIEWPORT_CLIP_MODE */  in nv50_gr_construct_gene_unk34xx()
1594 	xf_emit(ctx, 0x10, 0x04000000);	/* 07ffffff VIEWPORT_CLIP_HORIZ*8, VIEWPORT_CLIP_VERT*8 */  in nv50_gr_construct_gene_unk34xx()
1595 	xf_emit(ctx, 1, 0);		/* 00000001 POLYGON_STIPPLE_ENABLE */  in nv50_gr_construct_gene_unk34xx()
1596 	xf_emit(ctx, 0x20, 0);		/* ffffffff POLYGON_STIPPLE */  in nv50_gr_construct_gene_unk34xx()
1597 	xf_emit(ctx, 2, 0);		/* 00007fff WINDOW_OFFSET_XY */  in nv50_gr_construct_gene_unk34xx()
1598 	xf_emit(ctx, 1, 0);		/* ffff0ff3 */  in nv50_gr_construct_gene_unk34xx()
1599 	xf_emit(ctx, 1, 0x04e3bfdf);	/* ffffffff UNK0D64 */  in nv50_gr_construct_gene_unk34xx()
1600 	xf_emit(ctx, 1, 0x04e3bfdf);	/* ffffffff UNK0DF4 */  in nv50_gr_construct_gene_unk34xx()
1601 	xf_emit(ctx, 1, 0);		/* 00000003 WINDOW_ORIGIN */  in nv50_gr_construct_gene_unk34xx()
1602 	xf_emit(ctx, 1, 0);		/* 00000007 */  in nv50_gr_construct_gene_unk34xx()
1603 	xf_emit(ctx, 1, 0x1fe21);	/* 0001ffff tesla UNK0FAC */  in nv50_gr_construct_gene_unk34xx()
1604 	if (device->chipset >= 0xa0)  in nv50_gr_construct_gene_unk34xx()
1605 		xf_emit(ctx, 1, 0x0fac6881);  in nv50_gr_construct_gene_unk34xx()
1608 		xf_emit(ctx, 3, 0);  in nv50_gr_construct_gene_unk34xx()
1617 	if (device->chipset != 0x50) {  in nv50_gr_construct_gene_unk14xx()
1618 		xf_emit(ctx, 5, 0);		/* ffffffff */  in nv50_gr_construct_gene_unk14xx()
1619 		xf_emit(ctx, 1, 0x80c14);	/* 01ffffff SEMANTIC_COLOR */  in nv50_gr_construct_gene_unk14xx()
1620 		xf_emit(ctx, 1, 0);		/* 00000001 */  in nv50_gr_construct_gene_unk14xx()
1621 		xf_emit(ctx, 1, 0);		/* 000003ff */  in nv50_gr_construct_gene_unk14xx()
1622 		xf_emit(ctx, 1, 0x804);		/* 00000fff SEMANTIC_CLIP */  in nv50_gr_construct_gene_unk14xx()
1623 		xf_emit(ctx, 1, 0);		/* 00000001 */  in nv50_gr_construct_gene_unk14xx()
1625 		xf_emit(ctx, 1, 0x8100c12);	/* 1fffffff FP_INTERPOLANT_CTRL */  in nv50_gr_construct_gene_unk14xx()
1627 	xf_emit(ctx, 1, 0);			/* ffffffff tesla UNK1A30 */  in nv50_gr_construct_gene_unk14xx()
1630 	xf_emit(ctx, 1, 0);			/* 00000001 GP_ENABLE */  in nv50_gr_construct_gene_unk14xx()
1631 	xf_emit(ctx, 1, 0x10);			/* 7f/ff VIEW_VOLUME_CLIP_CTRL */  in nv50_gr_construct_gene_unk14xx()
1632 	xf_emit(ctx, 1, 0);			/* 000000ff VP_CLIP_DISTANCE_ENABLE */  in nv50_gr_construct_gene_unk14xx()
1633 	if (device->chipset != 0x50)  in nv50_gr_construct_gene_unk14xx()
1634 		xf_emit(ctx, 1, 0);		/* 3ff */  in nv50_gr_construct_gene_unk14xx()
1635 	xf_emit(ctx, 1, 0);			/* 000000ff tesla UNK1940 */  in nv50_gr_construct_gene_unk14xx()
1636 	xf_emit(ctx, 1, 0);			/* 00000001 tesla UNK0D7C */  in nv50_gr_construct_gene_unk14xx()
1637 	xf_emit(ctx, 1, 0x804);			/* 00000fff SEMANTIC_CLIP */  in nv50_gr_construct_gene_unk14xx()
1639 	xf_emit(ctx, 1, 0x1a);			/* 0000001f POLYGON_MODE */  in nv50_gr_construct_gene_unk14xx()
1640 	if (device->chipset != 0x50)  in nv50_gr_construct_gene_unk14xx()
1641 		xf_emit(ctx, 1, 0x7f);		/* 000000ff tesla UNK0FFC */  in nv50_gr_construct_gene_unk14xx()
1642 	xf_emit(ctx, 1, 0);			/* ffffffff tesla UNK1A30 */  in nv50_gr_construct_gene_unk14xx()
1644 	xf_emit(ctx, 1, 0x80c14);		/* 01ffffff SEMANTIC_COLOR */  in nv50_gr_construct_gene_unk14xx()
1645 	xf_emit(ctx, 1, 0);			/* 00000001 tesla UNK1900 */  in nv50_gr_construct_gene_unk14xx()
1646 	xf_emit(ctx, 1, 0x8100c12);		/* 1fffffff FP_INTERPOLANT_CTRL */  in nv50_gr_construct_gene_unk14xx()
1649 	xf_emit(ctx, 1, 0);			/* 00000001 GP_ENABLE */  in nv50_gr_construct_gene_unk14xx()
1650 	xf_emit(ctx, 1, 0x10);			/* 7f/ff VIEW_VOLUME_CLIP_CTRL */  in nv50_gr_construct_gene_unk14xx()
1651 	xf_emit(ctx, 1, 0);			/* 00000001 tesla UNK0D7C */  in nv50_gr_construct_gene_unk14xx()
1652 	xf_emit(ctx, 1, 0);			/* 00000001 tesla UNK0F8C */  in nv50_gr_construct_gene_unk14xx()
1653 	xf_emit(ctx, 1, 0);			/* ffffffff tesla UNK1A30 */  in nv50_gr_construct_gene_unk14xx()
1655 	xf_emit(ctx, 1, 0x8100c12);		/* 1fffffff FP_INTERPOLANT_CTRL */  in nv50_gr_construct_gene_unk14xx()
1656 	xf_emit(ctx, 4, 0);			/* ffffffff NOPERSPECTIVE_BITMAP */  in nv50_gr_construct_gene_unk14xx()
1657 	xf_emit(ctx, 1, 0);			/* 00000001 tesla UNK1900 */  in nv50_gr_construct_gene_unk14xx()
1658 	xf_emit(ctx, 1, 0);			/* 0000000f */  in nv50_gr_construct_gene_unk14xx()
1659 	if (device->chipset == 0x50)  in nv50_gr_construct_gene_unk14xx()
1660 		xf_emit(ctx, 1, 0x3ff);		/* 000003ff tesla UNK0D68 */  in nv50_gr_construct_gene_unk14xx()
1662 		xf_emit(ctx, 1, 0x7ff);		/* 000007ff tesla UNK0D68 */  in nv50_gr_construct_gene_unk14xx()
1663 	xf_emit(ctx, 1, 0x80c14);		/* 01ffffff SEMANTIC_COLOR */  in nv50_gr_construct_gene_unk14xx()
1664 	xf_emit(ctx, 1, 0);			/* 00000001 VERTEX_TWO_SIDE_ENABLE */  in nv50_gr_construct_gene_unk14xx()
1665 	xf_emit(ctx, 0x30, 0);			/* ffffffff VIEWPORT_SCALE: X0, Y0, Z0, X1, Y1, ... */  in nv50_gr_construct_gene_unk14xx()
1666 	xf_emit(ctx, 3, 0);			/* f, 0, 0 */  in nv50_gr_construct_gene_unk14xx()
1667 	xf_emit(ctx, 3, 0);			/* ffffffff last VIEWPORT_SCALE? */  in nv50_gr_construct_gene_unk14xx()
1668 	xf_emit(ctx, 1, 0);			/* ffffffff tesla UNK1A30 */  in nv50_gr_construct_gene_unk14xx()
1670 	xf_emit(ctx, 1, 0);			/* 00000001 tesla UNK1900 */  in nv50_gr_construct_gene_unk14xx()
1671 	xf_emit(ctx, 1, 0);			/* 00000001 tesla UNK1924 */  in nv50_gr_construct_gene_unk14xx()
1672 	xf_emit(ctx, 1, 0x10);			/* 000000ff VIEW_VOLUME_CLIP_CTRL */  in nv50_gr_construct_gene_unk14xx()
1673 	xf_emit(ctx, 1, 0);			/* 00000001 */  in nv50_gr_construct_gene_unk14xx()
1674 	xf_emit(ctx, 0x30, 0);			/* ffffffff VIEWPORT_TRANSLATE */  in nv50_gr_construct_gene_unk14xx()
1675 	xf_emit(ctx, 3, 0);			/* f, 0, 0 */  in nv50_gr_construct_gene_unk14xx()
1676 	xf_emit(ctx, 3, 0);			/* ffffffff */  in nv50_gr_construct_gene_unk14xx()
1677 	xf_emit(ctx, 1, 0);			/* ffffffff tesla UNK1A30 */  in nv50_gr_construct_gene_unk14xx()
1678 	xf_emit(ctx, 2, 0x88);			/* 000001ff tesla UNK19D8 */  in nv50_gr_construct_gene_unk14xx()
1679 	xf_emit(ctx, 1, 0);			/* 00000001 tesla UNK1924 */  in nv50_gr_construct_gene_unk14xx()
1680 	xf_emit(ctx, 1, 0);			/* ffffffff tesla UNK1A30 */  in nv50_gr_construct_gene_unk14xx()
1682 	xf_emit(ctx, 2, 0);			/* 07ffffff SCREEN_SCISSOR */  in nv50_gr_construct_gene_unk14xx()
1683 	xf_emit(ctx, 2, 0);			/* 00007fff WINDOW_OFFSET_XY */  in nv50_gr_construct_gene_unk14xx()
1684 	xf_emit(ctx, 1, 0);			/* 00000003 WINDOW_ORIGIN */  in nv50_gr_construct_gene_unk14xx()
1685 	xf_emit(ctx, 0x10, 0);			/* 00000001 SCISSOR_ENABLE */  in nv50_gr_construct_gene_unk14xx()
1686 	xf_emit(ctx, 1, 0);			/* 0001ffff GP_BUILTIN_RESULT_EN */  in nv50_gr_construct_gene_unk14xx()
1687 	xf_emit(ctx, 1, 0x26);			/* 000000ff SEMANTIC_LAYER */  in nv50_gr_construct_gene_unk14xx()
1688 	xf_emit(ctx, 1, 0);			/* 00000001 tesla UNK1900 */  in nv50_gr_construct_gene_unk14xx()
1689 	xf_emit(ctx, 1, 0);			/* 0000000f */  in nv50_gr_construct_gene_unk14xx()
1690 	xf_emit(ctx, 1, 0x3f800000);		/* ffffffff LINE_WIDTH */  in nv50_gr_construct_gene_unk14xx()
1691 	xf_emit(ctx, 1, 0);			/* 00000001 LINE_STIPPLE_ENABLE */  in nv50_gr_construct_gene_unk14xx()
1692 	xf_emit(ctx, 1, 0);			/* 00000001 LINE_SMOOTH_ENABLE */  in nv50_gr_construct_gene_unk14xx()
1693 	xf_emit(ctx, 1, 0);			/* 00000007 MULTISAMPLE_SAMPLES_LOG2 */  in nv50_gr_construct_gene_unk14xx()
1695 		xf_emit(ctx, 1, 0);		/* 00000001 */  in nv50_gr_construct_gene_unk14xx()
1696 	xf_emit(ctx, 1, 0x1a);			/* 0000001f POLYGON_MODE */  in nv50_gr_construct_gene_unk14xx()
1697 	xf_emit(ctx, 1, 0x10);			/* 000000ff VIEW_VOLUME_CLIP_CTRL */  in nv50_gr_construct_gene_unk14xx()
1698 	if (device->chipset != 0x50) {  in nv50_gr_construct_gene_unk14xx()
1699 		xf_emit(ctx, 1, 0);		/* ffffffff */  in nv50_gr_construct_gene_unk14xx()
1700 		xf_emit(ctx, 1, 0);		/* 00000001 */  in nv50_gr_construct_gene_unk14xx()
1701 		xf_emit(ctx, 1, 0);		/* 000003ff */  in nv50_gr_construct_gene_unk14xx()
1703 	xf_emit(ctx, 0x20, 0);			/* 10xbits ffffffff, 3fffff. SCISSOR_* */  in nv50_gr_construct_gene_unk14xx()
1704 	xf_emit(ctx, 1, 0);			/* f */  in nv50_gr_construct_gene_unk14xx()
1705 	xf_emit(ctx, 1, 0);			/* 0? */  in nv50_gr_construct_gene_unk14xx()
1706 	xf_emit(ctx, 1, 0);			/* ffffffff */  in nv50_gr_construct_gene_unk14xx()
1707 	xf_emit(ctx, 1, 0);			/* 003fffff */  in nv50_gr_construct_gene_unk14xx()
1708 	xf_emit(ctx, 1, 0);			/* ffffffff tesla UNK1A30 */  in nv50_gr_construct_gene_unk14xx()
1709 	xf_emit(ctx, 1, 0x52);			/* 000001ff SEMANTIC_PTSZ */  in nv50_gr_construct_gene_unk14xx()
1710 	xf_emit(ctx, 1, 0);			/* 0001ffff GP_BUILTIN_RESULT_EN */  in nv50_gr_construct_gene_unk14xx()
1711 	xf_emit(ctx, 1, 0x26);			/* 000000ff SEMANTIC_LAYER */  in nv50_gr_construct_gene_unk14xx()
1712 	xf_emit(ctx, 1, 0);			/* 00000001 tesla UNK1900 */  in nv50_gr_construct_gene_unk14xx()
1715 	xf_emit(ctx, 1, 0);			/* 00000001 GP_ENABLE */  in nv50_gr_construct_gene_unk14xx()
1716 	xf_emit(ctx, 1, 0x1a);			/* 0000001f POLYGON_MODE */  in nv50_gr_construct_gene_unk14xx()
1717 	xf_emit(ctx, 1, 0);			/* 00000001 LINE_SMOOTH_ENABLE */  in nv50_gr_construct_gene_unk14xx()
1718 	xf_emit(ctx, 1, 0);			/* 00000001 LINE_STIPPLE_ENABLE */  in nv50_gr_construct_gene_unk14xx()
1719 	xf_emit(ctx, 1, 0x00ffff00);		/* 00ffffff LINE_STIPPLE_PATTERN */  in nv50_gr_construct_gene_unk14xx()
1720 	xf_emit(ctx, 1, 0);			/* 0000000f */  in nv50_gr_construct_gene_unk14xx()
1727 	/* end of strand 0 on pre-NVA0, beginning of strand 6 on NVAx */  in nv50_gr_construct_gene_zcull()
1729 	xf_emit(ctx, 1, 0x3f);		/* 0000003f UNK1590 */  in nv50_gr_construct_gene_zcull()
1730 	xf_emit(ctx, 1, 0);		/* 00000001 ALPHA_TEST_ENABLE */  in nv50_gr_construct_gene_zcull()
1731 	xf_emit(ctx, 1, 0);		/* 00000007 MULTISAMPLE_SAMPLES_LOG2 */  in nv50_gr_construct_gene_zcull()
1732 	xf_emit(ctx, 1, 0);		/* 00000001 tesla UNK1534 */  in nv50_gr_construct_gene_zcull()
1733 	xf_emit(ctx, 1, 0);		/* 00000007 STENCIL_BACK_FUNC_FUNC */  in nv50_gr_construct_gene_zcull()
1734 	xf_emit(ctx, 1, 0);		/* 000000ff STENCIL_BACK_FUNC_MASK */  in nv50_gr_construct_gene_zcull()
1735 	xf_emit(ctx, 1, 0);		/* 000000ff STENCIL_BACK_FUNC_REF */  in nv50_gr_construct_gene_zcull()
1736 	xf_emit(ctx, 1, 0);		/* 000000ff STENCIL_BACK_MASK */  in nv50_gr_construct_gene_zcull()
1737 	xf_emit(ctx, 3, 0);		/* 00000007 STENCIL_BACK_OP_FAIL, ZFAIL, ZPASS */  in nv50_gr_construct_gene_zcull()
1739 	xf_emit(ctx, 2, 0x04000000);	/* 07ffffff tesla UNK0D6C */  in nv50_gr_construct_gene_zcull()
1740 	xf_emit(ctx, 1, 0);		/* ffff0ff3 */  in nv50_gr_construct_gene_zcull()
1741 	xf_emit(ctx, 1, 0);		/* 00000001 CLIPID_ENABLE */  in nv50_gr_construct_gene_zcull()
1742 	xf_emit(ctx, 2, 0);		/* ffffffff DEPTH_BOUNDS */  in nv50_gr_construct_gene_zcull()
1743 	xf_emit(ctx, 1, 0);		/* 00000001 */  in nv50_gr_construct_gene_zcull()
1744 	xf_emit(ctx, 1, 0);		/* 00000007 DEPTH_TEST_FUNC */  in nv50_gr_construct_gene_zcull()
1745 	xf_emit(ctx, 1, 0);		/* 00000001 DEPTH_TEST_ENABLE */  in nv50_gr_construct_gene_zcull()
1746 	xf_emit(ctx, 1, 0);		/* 00000001 DEPTH_WRITE_ENABLE */  in nv50_gr_construct_gene_zcull()
1748 	xf_emit(ctx, 1, 0);		/* 0000ffff */  in nv50_gr_construct_gene_zcull()
1749 	xf_emit(ctx, 1, 0);		/* 00000001 UNK0FB0 */  in nv50_gr_construct_gene_zcull()
1750 	xf_emit(ctx, 1, 0);		/* 00000001 POLYGON_STIPPLE_ENABLE */  in nv50_gr_construct_gene_zcull()
1752 	xf_emit(ctx, 1, 0);		/* ffffffff */  in nv50_gr_construct_gene_zcull()
1753 	xf_emit(ctx, 1, 0);		/* 0001ffff GP_BUILTIN_RESULT_EN */  in nv50_gr_construct_gene_zcull()
1754 	xf_emit(ctx, 1, 0);		/* 000000ff CLEAR_STENCIL */  in nv50_gr_construct_gene_zcull()
1755 	xf_emit(ctx, 1, 0);		/* 00000007 STENCIL_FRONT_FUNC_FUNC */  in nv50_gr_construct_gene_zcull()
1756 	xf_emit(ctx, 1, 0);		/* 000000ff STENCIL_FRONT_FUNC_MASK */  in nv50_gr_construct_gene_zcull()
1757 	xf_emit(ctx, 1, 0);		/* 000000ff STENCIL_FRONT_FUNC_REF */  in nv50_gr_construct_gene_zcull()
1758 	xf_emit(ctx, 1, 0);		/* 000000ff STENCIL_FRONT_MASK */  in nv50_gr_construct_gene_zcull()
1759 	xf_emit(ctx, 3, 0);		/* 00000007 STENCIL_FRONT_OP_FAIL, ZFAIL, ZPASS */  in nv50_gr_construct_gene_zcull()
1760 	xf_emit(ctx, 1, 0);		/* 00000001 STENCIL_FRONT_ENABLE */  in nv50_gr_construct_gene_zcull()
1761 	xf_emit(ctx, 1, 0);		/* 00000001 STENCIL_BACK_ENABLE */  in nv50_gr_construct_gene_zcull()
1762 	xf_emit(ctx, 1, 0);		/* ffffffff CLEAR_DEPTH */  in nv50_gr_construct_gene_zcull()
1763 	xf_emit(ctx, 1, 0);		/* 00000007 */  in nv50_gr_construct_gene_zcull()
1764 	if (device->chipset != 0x50)  in nv50_gr_construct_gene_zcull()
1765 		xf_emit(ctx, 1, 0);	/* 00000003 tesla UNK1108 */  in nv50_gr_construct_gene_zcull()
1766 	xf_emit(ctx, 1, 0);		/* 00000001 SAMPLECNT_ENABLE */  in nv50_gr_construct_gene_zcull()
1767 	xf_emit(ctx, 1, 0);		/* 0000000f ZETA_FORMAT */  in nv50_gr_construct_gene_zcull()
1769 	xf_emit(ctx, 1, 0x1001);	/* 00001fff ZETA_ARRAY_MODE */  in nv50_gr_construct_gene_zcull()
1771 	xf_emit(ctx, 4, 0xffff);	/* 0000ffff MSAA_MASK */  in nv50_gr_construct_gene_zcull()
1772 	xf_emit(ctx, 0x10, 0);		/* 00000001 SCISSOR_ENABLE */  in nv50_gr_construct_gene_zcull()
1773 	xf_emit(ctx, 0x10, 0);		/* ffffffff DEPTH_RANGE_NEAR */  in nv50_gr_construct_gene_zcull()
1774 	xf_emit(ctx, 0x10, 0x3f800000);	/* ffffffff DEPTH_RANGE_FAR */  in nv50_gr_construct_gene_zcull()
1775 	xf_emit(ctx, 1, 0x10);		/* 7f/ff/3ff VIEW_VOLUME_CLIP_CTRL */  in nv50_gr_construct_gene_zcull()
1776 	xf_emit(ctx, 1, 0);		/* 00000001 VIEWPORT_CLIP_RECTS_EN */  in nv50_gr_construct_gene_zcull()
1778 	xf_emit(ctx, 1, 0);		/* 00000003 tesla UNK1968 */  in nv50_gr_construct_gene_zcull()
1779 	if (device->chipset != 0x50)  in nv50_gr_construct_gene_zcull()
1780 		xf_emit(ctx, 1, 0);	/* 0fffffff tesla UNK1104 */  in nv50_gr_construct_gene_zcull()
1781 	xf_emit(ctx, 1, 0);		/* 00000001 tesla UNK151C */  in nv50_gr_construct_gene_zcull()
1787 	/* middle of strand 0 on pre-NVA0 [after 24xx], middle of area 6 on NVAx */  in nv50_gr_construct_gene_clipid()
1789 	xf_emit(ctx, 1, 0);		/* 00000007 UNK0FB4 */  in nv50_gr_construct_gene_clipid()
1791 	xf_emit(ctx, 4, 0);		/* 07ffffff CLIPID_REGION_HORIZ */  in nv50_gr_construct_gene_clipid()
1792 	xf_emit(ctx, 4, 0);		/* 07ffffff CLIPID_REGION_VERT */  in nv50_gr_construct_gene_clipid()
1793 	xf_emit(ctx, 2, 0);		/* 07ffffff SCREEN_SCISSOR */  in nv50_gr_construct_gene_clipid()
1794 	xf_emit(ctx, 2, 0x04000000);	/* 07ffffff UNK1508 */  in nv50_gr_construct_gene_clipid()
1795 	xf_emit(ctx, 1, 0);		/* 00000001 CLIPID_ENABLE */  in nv50_gr_construct_gene_clipid()
1796 	xf_emit(ctx, 1, 0x80);		/* 00003fff CLIPID_WIDTH */  in nv50_gr_construct_gene_clipid()
1797 	xf_emit(ctx, 1, 0);		/* 000000ff CLIPID_ID */  in nv50_gr_construct_gene_clipid()
1798 	xf_emit(ctx, 1, 0);		/* 000000ff CLIPID_ADDRESS_HIGH */  in nv50_gr_construct_gene_clipid()
1799 	xf_emit(ctx, 1, 0);		/* ffffffff CLIPID_ADDRESS_LOW */  in nv50_gr_construct_gene_clipid()
1800 	xf_emit(ctx, 1, 0x80);		/* 00003fff CLIPID_HEIGHT */  in nv50_gr_construct_gene_clipid()
1801 	xf_emit(ctx, 1, 0);		/* 0000ffff DMA_CLIPID */  in nv50_gr_construct_gene_clipid()
1809 	/* middle of strand 0 on pre-NVA0 [after m2mf], end of strand 2 on NVAx */  in nv50_gr_construct_gene_unk24xx()
1811 	xf_emit(ctx, 0x33, 0);  in nv50_gr_construct_gene_unk24xx()
1813 	xf_emit(ctx, 2, 0);  in nv50_gr_construct_gene_unk24xx()
1815 	xf_emit(ctx, 1, 0);		/* 00000001 GP_ENABLE */  in nv50_gr_construct_gene_unk24xx()
1820 		xf_emit(ctx, 4, 0);	/* RO */  in nv50_gr_construct_gene_unk24xx()
1821 		xf_emit(ctx, 0xe10, 0); /* 190 * 9: 8*ffffffff, 7ff */  in nv50_gr_construct_gene_unk24xx()
1822 		xf_emit(ctx, 1, 0);	/* 1ff */  in nv50_gr_construct_gene_unk24xx()
1823 		xf_emit(ctx, 8, 0);	/* 0? */  in nv50_gr_construct_gene_unk24xx()
1824 		xf_emit(ctx, 9, 0);	/* ffffffff, 7ff */  in nv50_gr_construct_gene_unk24xx()
1826 		xf_emit(ctx, 4, 0);	/* RO */  in nv50_gr_construct_gene_unk24xx()
1827 		xf_emit(ctx, 0xe10, 0); /* 190 * 9: 8*ffffffff, 7ff */  in nv50_gr_construct_gene_unk24xx()
1828 		xf_emit(ctx, 1, 0);	/* 1ff */  in nv50_gr_construct_gene_unk24xx()
1829 		xf_emit(ctx, 8, 0);	/* 0? */  in nv50_gr_construct_gene_unk24xx()
1830 		xf_emit(ctx, 9, 0);	/* ffffffff, 7ff */  in nv50_gr_construct_gene_unk24xx()
1832 		xf_emit(ctx, 0xc, 0);	/* RO */  in nv50_gr_construct_gene_unk24xx()
1834 		xf_emit(ctx, 0xe10, 0); /* 190 * 9: 8*ffffffff, 7ff */  in nv50_gr_construct_gene_unk24xx()
1835 		xf_emit(ctx, 1, 0);	/* 1ff */  in nv50_gr_construct_gene_unk24xx()
1836 		xf_emit(ctx, 8, 0);	/* 0? */  in nv50_gr_construct_gene_unk24xx()
1839 		xf_emit(ctx, 0xc, 0);	/* RO */  in nv50_gr_construct_gene_unk24xx()
1841 		xf_emit(ctx, 0xe10, 0); /* 190 * 9: 8*ffffffff, 7ff */  in nv50_gr_construct_gene_unk24xx()
1842 		xf_emit(ctx, 1, 0);	/* 1ff */  in nv50_gr_construct_gene_unk24xx()
1843 		xf_emit(ctx, 8, 0);	/* 0? */  in nv50_gr_construct_gene_unk24xx()
1846 	xf_emit(ctx, 1, 0);		/* 00000001 GP_ENABLE */  in nv50_gr_construct_gene_unk24xx()
1849 	xf_emit(ctx, 1, 0x8100c12);	/* 1fffffff FP_INTERPOLANT_CTRL */  in nv50_gr_construct_gene_unk24xx()
1850 	if (device->chipset != 0x50)  in nv50_gr_construct_gene_unk24xx()
1853 	xf_emit(ctx, 1, 0);		/* 00000001 GP_ENABLE */  in nv50_gr_construct_gene_unk24xx()
1854 	xf_emit(ctx, 1, 0x8100c12);	/* 1fffffff FP_INTERPOLANT_CTRL */  in nv50_gr_construct_gene_unk24xx()
1855 	xf_emit(ctx, 1, 0);		/* 0000000f VP_GP_BUILTIN_ATTR_EN */  in nv50_gr_construct_gene_unk24xx()
1856 	xf_emit(ctx, 1, 0x80c14);	/* 01ffffff SEMANTIC_COLOR */  in nv50_gr_construct_gene_unk24xx()
1859 	if (device->chipset >= 0xa0)  in nv50_gr_construct_gene_unk24xx()
1861 	xf_emit(ctx, 1, 0x80c14);	/* 01ffffff SEMANTIC_COLOR */  in nv50_gr_construct_gene_unk24xx()
1862 	xf_emit(ctx, 1, 0);		/* 00000001 VERTEX_TWO_SIDE_ENABLE */  in nv50_gr_construct_gene_unk24xx()
1863 	xf_emit(ctx, 1, 0);		/* 00000001 POINT_SPRITE_ENABLE */  in nv50_gr_construct_gene_unk24xx()
1864 	xf_emit(ctx, 1, 0x8100c12);	/* 1fffffff FP_INTERPOLANT_CTRL */  in nv50_gr_construct_gene_unk24xx()
1865 	xf_emit(ctx, 1, 0x27);		/* 000000ff SEMANTIC_PRIM_ID */  in nv50_gr_construct_gene_unk24xx()
1866 	xf_emit(ctx, 1, 0);		/* 00000001 GP_ENABLE */  in nv50_gr_construct_gene_unk24xx()
1867 	xf_emit(ctx, 1, 0);		/* 0000000f */  in nv50_gr_construct_gene_unk24xx()
1869 	for (i = 0; i < 10; i++) {  in nv50_gr_construct_gene_unk24xx()
1871 		xf_emit(ctx, 0x40, 0);		/* ffffffff */  in nv50_gr_construct_gene_unk24xx()
1872 		xf_emit(ctx, 0x10, 0);		/* 3, 0, 0.... */  in nv50_gr_construct_gene_unk24xx()
1873 		xf_emit(ctx, 0x10, 0);		/* ffffffff */  in nv50_gr_construct_gene_unk24xx()
1876 	xf_emit(ctx, 1, 0);		/* 00000001 POINT_SPRITE_CTRL */  in nv50_gr_construct_gene_unk24xx()
1878 	xf_emit(ctx, 1, 0);		/* ffffffff */  in nv50_gr_construct_gene_unk24xx()
1879 	xf_emit(ctx, 4, 0);		/* ffffffff NOPERSPECTIVE_BITMAP */  in nv50_gr_construct_gene_unk24xx()
1880 	xf_emit(ctx, 0x10, 0);		/* 00ffffff POINT_COORD_REPLACE_MAP */  in nv50_gr_construct_gene_unk24xx()
1881 	xf_emit(ctx, 1, 0);		/* 00000003 WINDOW_ORIGIN */  in nv50_gr_construct_gene_unk24xx()
1882 	xf_emit(ctx, 1, 0x8100c12);	/* 1fffffff FP_INTERPOLANT_CTRL */  in nv50_gr_construct_gene_unk24xx()
1883 	if (device->chipset != 0x50)  in nv50_gr_construct_gene_unk24xx()
1884 		xf_emit(ctx, 1, 0);	/* 000003ff */  in nv50_gr_construct_gene_unk24xx()
1891 	int acnt = 0x10, rep, i;  in nv50_gr_construct_gene_vfetch()
1894 		acnt = 0x20;  in nv50_gr_construct_gene_vfetch()
1896 	if (device->chipset >= 0xa0) {  in nv50_gr_construct_gene_vfetch()
1897 		xf_emit(ctx, 1, 0);	/* ffffffff tesla UNK13A4 */  in nv50_gr_construct_gene_vfetch()
1900 	xf_emit(ctx, 1, 0);		/* ffffffff VERTEX_BUFFER_FIRST */  in nv50_gr_construct_gene_vfetch()
1901 	xf_emit(ctx, 1, 0);		/* 00000001 PRIMITIVE_RESTART_ENABLE */  in nv50_gr_construct_gene_vfetch()
1902 	xf_emit(ctx, 1, 0);		/* 00000001 UNK0DE8 */  in nv50_gr_construct_gene_vfetch()
1903 	xf_emit(ctx, 1, 0);		/* ffffffff PRIMITIVE_RESTART_INDEX */  in nv50_gr_construct_gene_vfetch()
1904 	xf_emit(ctx, 1, 0xf);		/* ffffffff VP_ATTR_EN */  in nv50_gr_construct_gene_vfetch()
1905 	xf_emit(ctx, (acnt/8)-1, 0);	/* ffffffff VP_ATTR_EN */  in nv50_gr_construct_gene_vfetch()
1906 	xf_emit(ctx, acnt/8, 0);	/* ffffffff VTX_ATR_MASK_UNK0DD0 */  in nv50_gr_construct_gene_vfetch()
1907 	xf_emit(ctx, 1, 0);		/* 0000000f VP_GP_BUILTIN_ATTR_EN */  in nv50_gr_construct_gene_vfetch()
1908 	xf_emit(ctx, 1, 0x20);		/* 0000ffff tesla UNK129C */  in nv50_gr_construct_gene_vfetch()
1909 	xf_emit(ctx, 1, 0);		/* 000000ff turing UNK370??? */  in nv50_gr_construct_gene_vfetch()
1910 	xf_emit(ctx, 1, 0);		/* 0000ffff turing USER_PARAM_COUNT */  in nv50_gr_construct_gene_vfetch()
1911 	xf_emit(ctx, 1, 0);		/* ffffffff tesla UNK1A30 */  in nv50_gr_construct_gene_vfetch()
1914 		xf_emit(ctx, 0xb, 0);	/* RO */  in nv50_gr_construct_gene_vfetch()
1915 	else if (device->chipset >= 0xa0)  in nv50_gr_construct_gene_vfetch()
1916 		xf_emit(ctx, 0x9, 0);	/* RO */  in nv50_gr_construct_gene_vfetch()
1918 		xf_emit(ctx, 0x8, 0);	/* RO */  in nv50_gr_construct_gene_vfetch()
1920 	xf_emit(ctx, 1, 0);		/* 00000001 EDGE_FLAG */  in nv50_gr_construct_gene_vfetch()
1921 	xf_emit(ctx, 1, 0);		/* 00000001 PROVOKING_VERTEX_LAST */  in nv50_gr_construct_gene_vfetch()
1922 	xf_emit(ctx, 1, 0);		/* 00000001 GP_ENABLE */  in nv50_gr_construct_gene_vfetch()
1923 	xf_emit(ctx, 1, 0x1a);		/* 0000001f POLYGON_MODE */  in nv50_gr_construct_gene_vfetch()
1925 	xf_emit(ctx, 0xc, 0);		/* RO */  in nv50_gr_construct_gene_vfetch()
1927 	xf_emit(ctx, 1, 0);		/* 7f/ff */  in nv50_gr_construct_gene_vfetch()
1930 	xf_emit(ctx, 1, 0);		/* 0000000f VP_GP_BUILTIN_ATTR_EN */  in nv50_gr_construct_gene_vfetch()
1933 	xf_emit(ctx, 1, 0);		/* 00000001 GP_ENABLE */  in nv50_gr_construct_gene_vfetch()
1934 	if (device->chipset == 0x50)  in nv50_gr_construct_gene_vfetch()
1935 		xf_emit(ctx, 1, 0x3ff);	/* 3ff tesla UNK0D68 */  in nv50_gr_construct_gene_vfetch()
1937 		xf_emit(ctx, 1, 0x7ff);	/* 7ff tesla UNK0D68 */  in nv50_gr_construct_gene_vfetch()
1938 	if (device->chipset == 0xa8)  in nv50_gr_construct_gene_vfetch()
1939 		xf_emit(ctx, 1, 0x1e00);	/* 7fff */  in nv50_gr_construct_gene_vfetch()
1941 	xf_emit(ctx, 0xc, 0);		/* RO or close */  in nv50_gr_construct_gene_vfetch()
1943 	xf_emit(ctx, 1, 0xf);		/* ffffffff VP_ATTR_EN */  in nv50_gr_construct_gene_vfetch()
1944 	xf_emit(ctx, (acnt/8)-1, 0);	/* ffffffff VP_ATTR_EN */  in nv50_gr_construct_gene_vfetch()
1945 	xf_emit(ctx, 1, 0);		/* 0000000f VP_GP_BUILTIN_ATTR_EN */  in nv50_gr_construct_gene_vfetch()
1946 	if (device->chipset > 0x50 && device->chipset < 0xa0)  in nv50_gr_construct_gene_vfetch()
1947 		xf_emit(ctx, 2, 0);	/* ffffffff */  in nv50_gr_construct_gene_vfetch()
1949 		xf_emit(ctx, 1, 0);	/* ffffffff */  in nv50_gr_construct_gene_vfetch()
1950 	xf_emit(ctx, 1, 0);		/* 00000003 tesla UNK0FD8 */  in nv50_gr_construct_gene_vfetch()
1953 		xf_emit(ctx, 0x10, 0);	/* 0? */  in nv50_gr_construct_gene_vfetch()
1954 		xf_emit(ctx, 2, 0);	/* weird... */  in nv50_gr_construct_gene_vfetch()
1955 		xf_emit(ctx, 2, 0);	/* RO */  in nv50_gr_construct_gene_vfetch()
1957 		xf_emit(ctx, 8, 0);	/* 0? */  in nv50_gr_construct_gene_vfetch()
1958 		xf_emit(ctx, 1, 0);	/* weird... */  in nv50_gr_construct_gene_vfetch()
1959 		xf_emit(ctx, 2, 0);	/* RO */  in nv50_gr_construct_gene_vfetch()
1962 	xf_emit(ctx, 1, 0);		/* ffffffff VB_ELEMENT_BASE */  in nv50_gr_construct_gene_vfetch()
1963 	xf_emit(ctx, 1, 0);		/* ffffffff UNK1438 */  in nv50_gr_construct_gene_vfetch()
1964 	xf_emit(ctx, acnt, 0);		/* 1 tesla UNK1000 */  in nv50_gr_construct_gene_vfetch()
1965 	if (device->chipset >= 0xa0)  in nv50_gr_construct_gene_vfetch()
1966 		xf_emit(ctx, 1, 0);	/* ffffffff tesla UNK1118? */  in nv50_gr_construct_gene_vfetch()
1968 	xf_emit(ctx, acnt, 0);		/* ffffffff VERTEX_ARRAY_UNK90C */  in nv50_gr_construct_gene_vfetch()
1969 	xf_emit(ctx, 1, 0);		/* f/1f */  in nv50_gr_construct_gene_vfetch()
1971 	xf_emit(ctx, acnt, 0);		/* ffffffff VERTEX_ARRAY_UNK90C */  in nv50_gr_construct_gene_vfetch()
1972 	xf_emit(ctx, 1, 0);		/* f/1f */  in nv50_gr_construct_gene_vfetch()
1974 	xf_emit(ctx, acnt, 0);		/* RO */  in nv50_gr_construct_gene_vfetch()
1975 	xf_emit(ctx, 2, 0);		/* RO */  in nv50_gr_construct_gene_vfetch()
1977 	xf_emit(ctx, 1, 0);		/* ffffffff tesla UNK111C? */  in nv50_gr_construct_gene_vfetch()
1978 	xf_emit(ctx, 1, 0);		/* RO */  in nv50_gr_construct_gene_vfetch()
1980 	xf_emit(ctx, 1, 0);		/* 000000ff UNK15F4_ADDRESS_HIGH */  in nv50_gr_construct_gene_vfetch()
1981 	xf_emit(ctx, 1, 0);		/* ffffffff UNK15F4_ADDRESS_LOW */  in nv50_gr_construct_gene_vfetch()
1982 	xf_emit(ctx, 1, 0);		/* 000000ff UNK0F84_ADDRESS_HIGH */  in nv50_gr_construct_gene_vfetch()
1983 	xf_emit(ctx, 1, 0);		/* ffffffff UNK0F84_ADDRESS_LOW */  in nv50_gr_construct_gene_vfetch()
1985 	xf_emit(ctx, acnt, 0);		/* 00003fff VERTEX_ARRAY_ATTRIB_OFFSET */  in nv50_gr_construct_gene_vfetch()
1986 	xf_emit(ctx, 3, 0);		/* f/1f */  in nv50_gr_construct_gene_vfetch()
1988 	xf_emit(ctx, acnt, 0);		/* 00000fff VERTEX_ARRAY_STRIDE */  in nv50_gr_construct_gene_vfetch()
1989 	xf_emit(ctx, 3, 0);		/* f/1f */  in nv50_gr_construct_gene_vfetch()
1991 	xf_emit(ctx, acnt, 0);		/* ffffffff VERTEX_ARRAY_LOW */  in nv50_gr_construct_gene_vfetch()
1992 	xf_emit(ctx, 3, 0);		/* f/1f */  in nv50_gr_construct_gene_vfetch()
1994 	xf_emit(ctx, acnt, 0);		/* 000000ff VERTEX_ARRAY_HIGH */  in nv50_gr_construct_gene_vfetch()
1995 	xf_emit(ctx, 3, 0);		/* f/1f */  in nv50_gr_construct_gene_vfetch()
1997 	xf_emit(ctx, acnt, 0);		/* ffffffff VERTEX_LIMIT_LOW */  in nv50_gr_construct_gene_vfetch()
1998 	xf_emit(ctx, 3, 0);		/* f/1f */  in nv50_gr_construct_gene_vfetch()
2000 	xf_emit(ctx, acnt, 0);		/* 000000ff VERTEX_LIMIT_HIGH */  in nv50_gr_construct_gene_vfetch()
2001 	xf_emit(ctx, 3, 0);		/* f/1f */  in nv50_gr_construct_gene_vfetch()
2004 		xf_emit(ctx, acnt, 0);		/* f */  in nv50_gr_construct_gene_vfetch()
2005 		xf_emit(ctx, 3, 0);		/* f/1f */  in nv50_gr_construct_gene_vfetch()
2009 		xf_emit(ctx, 2, 0);	/* RO */  in nv50_gr_construct_gene_vfetch()
2011 		xf_emit(ctx, 5, 0);	/* RO */  in nv50_gr_construct_gene_vfetch()
2013 	xf_emit(ctx, 1, 0);		/* ffff DMA_VTXBUF */  in nv50_gr_construct_gene_vfetch()
2015 	if (device->chipset < 0xa0) {  in nv50_gr_construct_gene_vfetch()
2016 		xf_emit(ctx, 0x41, 0);	/* RO */  in nv50_gr_construct_gene_vfetch()
2018 		xf_emit(ctx, 0x11, 0);	/* RO */  in nv50_gr_construct_gene_vfetch()
2020 		xf_emit(ctx, 0x50, 0);	/* RO */  in nv50_gr_construct_gene_vfetch()
2022 		xf_emit(ctx, 0x58, 0);	/* RO */  in nv50_gr_construct_gene_vfetch()
2024 	xf_emit(ctx, 1, 0xf);		/* ffffffff VP_ATTR_EN */  in nv50_gr_construct_gene_vfetch()
2025 	xf_emit(ctx, (acnt/8)-1, 0);	/* ffffffff VP_ATTR_EN */  in nv50_gr_construct_gene_vfetch()
2028 	xf_emit(ctx, acnt*4, 0);	/* ffffffff VTX_ATTR */  in nv50_gr_construct_gene_vfetch()
2029 	xf_emit(ctx, 4, 0);		/* f/1f, 0, 0, 0 */  in nv50_gr_construct_gene_vfetch()
2032 		xf_emit(ctx, 0x1d, 0);	/* RO */  in nv50_gr_construct_gene_vfetch()
2034 		xf_emit(ctx, 0x16, 0);	/* RO */  in nv50_gr_construct_gene_vfetch()
2036 	xf_emit(ctx, 1, 0xf);		/* ffffffff VP_ATTR_EN */  in nv50_gr_construct_gene_vfetch()
2037 	xf_emit(ctx, (acnt/8)-1, 0);	/* ffffffff VP_ATTR_EN */  in nv50_gr_construct_gene_vfetch()
2039 	if (device->chipset < 0xa0)  in nv50_gr_construct_gene_vfetch()
2040 		xf_emit(ctx, 8, 0);	/* RO */  in nv50_gr_construct_gene_vfetch()
2042 		xf_emit(ctx, 0xc, 0);	/* RO */  in nv50_gr_construct_gene_vfetch()
2044 		xf_emit(ctx, 7, 0);	/* RO */  in nv50_gr_construct_gene_vfetch()
2046 	xf_emit(ctx, 0xa, 0);		/* RO */  in nv50_gr_construct_gene_vfetch()
2047 	if (device->chipset == 0xa0)  in nv50_gr_construct_gene_vfetch()
2048 		rep = 0xc;  in nv50_gr_construct_gene_vfetch()
2051 	for (i = 0; i < rep; i++) {  in nv50_gr_construct_gene_vfetch()
2054 			xf_emit(ctx, 0x20, 0);	/* ffffffff */  in nv50_gr_construct_gene_vfetch()
2055 		xf_emit(ctx, 0x200, 0);	/* ffffffff */  in nv50_gr_construct_gene_vfetch()
2056 		xf_emit(ctx, 4, 0);	/* 7f/ff, 0, 0, 0 */  in nv50_gr_construct_gene_vfetch()
2057 		xf_emit(ctx, 4, 0);	/* ffffffff */  in nv50_gr_construct_gene_vfetch()
2060 	xf_emit(ctx, 1, 0);		/* 113/111 */  in nv50_gr_construct_gene_vfetch()
2061 	xf_emit(ctx, 1, 0xf);		/* ffffffff VP_ATTR_EN */  in nv50_gr_construct_gene_vfetch()
2062 	xf_emit(ctx, (acnt/8)-1, 0);	/* ffffffff VP_ATTR_EN */  in nv50_gr_construct_gene_vfetch()
2063 	xf_emit(ctx, acnt/8, 0);	/* ffffffff VTX_ATTR_MASK_UNK0DD0 */  in nv50_gr_construct_gene_vfetch()
2064 	xf_emit(ctx, 1, 0);		/* 0000000f VP_GP_BUILTIN_ATTR_EN */  in nv50_gr_construct_gene_vfetch()
2065 	xf_emit(ctx, 1, 0);		/* ffffffff tesla UNK1A30 */  in nv50_gr_construct_gene_vfetch()
2068 		xf_emit(ctx, 7, 0);	/* weird... */  in nv50_gr_construct_gene_vfetch()
2070 		xf_emit(ctx, 5, 0);	/* weird... */  in nv50_gr_construct_gene_vfetch()
2079 	xf_emit(ctx, 2, 0);		/* 0001ffff CLIP_X, CLIP_Y */  in nv50_gr_construct_gene_eng2d()
2080 	xf_emit(ctx, 2, 0);		/* 0000ffff CLIP_W, CLIP_H */  in nv50_gr_construct_gene_eng2d()
2081 	xf_emit(ctx, 1, 0);		/* 00000001 CLIP_ENABLE */  in nv50_gr_construct_gene_eng2d()
2082 	if (device->chipset < 0xa0) {  in nv50_gr_construct_gene_eng2d()
2085 		xf_emit(ctx, 2, 0);	/* 0000ffff IFC_CLIP_X, Y */  in nv50_gr_construct_gene_eng2d()
2087 		xf_emit(ctx, 1, 0);	/* 00000001 IFC_CLIP_ENABLE */  in nv50_gr_construct_gene_eng2d()
2090 	xf_emit(ctx, 1, 0x100);		/* 0001ffff DST_WIDTH */  in nv50_gr_construct_gene_eng2d()
2091 	xf_emit(ctx, 1, 0x100);		/* 0001ffff DST_HEIGHT */  in nv50_gr_construct_gene_eng2d()
2092 	xf_emit(ctx, 1, 0x11);		/* 3f[NV50]/7f[NV84+] DST_FORMAT */  in nv50_gr_construct_gene_eng2d()
2093 	xf_emit(ctx, 1, 0);		/* 0001ffff DRAW_POINT_X */  in nv50_gr_construct_gene_eng2d()
2095 	xf_emit(ctx, 1, 0);		/* 000fffff SIFC_DST_X_FRACT */  in nv50_gr_construct_gene_eng2d()
2096 	xf_emit(ctx, 1, 0);		/* 0001ffff SIFC_DST_X_INT */  in nv50_gr_construct_gene_eng2d()
2097 	xf_emit(ctx, 1, 0);		/* 000fffff SIFC_DST_Y_FRACT */  in nv50_gr_construct_gene_eng2d()
2098 	xf_emit(ctx, 1, 0);		/* 0001ffff SIFC_DST_Y_INT */  in nv50_gr_construct_gene_eng2d()
2099 	xf_emit(ctx, 1, 0);		/* 000fffff SIFC_DX_DU_FRACT */  in nv50_gr_construct_gene_eng2d()
2101 	xf_emit(ctx, 1, 0);		/* 000fffff SIFC_DY_DV_FRACT */  in nv50_gr_construct_gene_eng2d()
2105 	xf_emit(ctx, 1, 0xcf);		/* 000000ff SIFC_FORMAT */  in nv50_gr_construct_gene_eng2d()
2107 	xf_emit(ctx, 1, 0);		/* 00000003 SIFC_BITMAP_LINE_PACK_MODE */  in nv50_gr_construct_gene_eng2d()
2108 	xf_emit(ctx, 1, 0);		/* 00000001 SIFC_BITMAP_LSB_FIRST */  in nv50_gr_construct_gene_eng2d()
2109 	xf_emit(ctx, 1, 0);		/* 00000001 SIFC_BITMAP_ENABLE */  in nv50_gr_construct_gene_eng2d()
2110 	xf_emit(ctx, 1, 0);		/* 0000ffff BLIT_DST_X */  in nv50_gr_construct_gene_eng2d()
2111 	xf_emit(ctx, 1, 0);		/* 0000ffff BLIT_DST_Y */  in nv50_gr_construct_gene_eng2d()
2112 	xf_emit(ctx, 1, 0);		/* 000fffff BLIT_DU_DX_FRACT */  in nv50_gr_construct_gene_eng2d()
2114 	xf_emit(ctx, 1, 0);		/* 000fffff BLIT_DV_DY_FRACT */  in nv50_gr_construct_gene_eng2d()
2118 	xf_emit(ctx, 1, 0);		/* 000fffff BLIT_SRC_X_FRACT */  in nv50_gr_construct_gene_eng2d()
2119 	xf_emit(ctx, 1, 0);		/* 0001ffff BLIT_SRC_X_INT */  in nv50_gr_construct_gene_eng2d()
2120 	xf_emit(ctx, 1, 0);		/* 000fffff BLIT_SRC_Y_FRACT */  in nv50_gr_construct_gene_eng2d()
2121 	xf_emit(ctx, 1, 0);		/* 00000001 UNK888 */  in nv50_gr_construct_gene_eng2d()
2123 	xf_emit(ctx, 1, 0);		/* 00000007 UNK880 */  in nv50_gr_construct_gene_eng2d()
2125 	xf_emit(ctx, 1, 0x15);		/* 000000ff tesla UNK128C */  in nv50_gr_construct_gene_eng2d()
2126 	xf_emit(ctx, 2, 0);		/* 00000007, ffff0ff3 */  in nv50_gr_construct_gene_eng2d()
2127 	xf_emit(ctx, 1, 0);		/* 00000001 UNK260 */  in nv50_gr_construct_gene_eng2d()
2128 	xf_emit(ctx, 1, 0x4444480);	/* 1fffffff UNK870 */  in nv50_gr_construct_gene_eng2d()
2130 	xf_emit(ctx, 0x10, 0);  in nv50_gr_construct_gene_eng2d()
2132 	xf_emit(ctx, 0x27, 0);  in nv50_gr_construct_gene_eng2d()
2139 	/* middle of strand 1 on pre-NVA0 [after eng2d], middle of strand 0 on NVAx */  in nv50_gr_construct_gene_csched()
2141 	xf_emit(ctx, 2, 0);		/* 00007fff WINDOW_OFFSET_XY... what is it doing here??? */  in nv50_gr_construct_gene_csched()
2142 	xf_emit(ctx, 1, 0);		/* 00000001 tesla UNK1924 */  in nv50_gr_construct_gene_csched()
2143 	xf_emit(ctx, 1, 0);		/* 00000003 WINDOW_ORIGIN */  in nv50_gr_construct_gene_csched()
2144 	xf_emit(ctx, 1, 0x8100c12);	/* 1fffffff FP_INTERPOLANT_CTRL */  in nv50_gr_construct_gene_csched()
2145 	xf_emit(ctx, 1, 0);		/* 000003ff */  in nv50_gr_construct_gene_csched()
2147 	xf_emit(ctx, 1, 0);		/* ffffffff turing UNK364 */  in nv50_gr_construct_gene_csched()
2148 	xf_emit(ctx, 1, 0);		/* 0000000f turing UNK36C */  in nv50_gr_construct_gene_csched()
2149 	xf_emit(ctx, 1, 0);		/* 0000ffff USER_PARAM_COUNT */  in nv50_gr_construct_gene_csched()
2150 	xf_emit(ctx, 1, 0x100);		/* 00ffffff turing UNK384 */  in nv50_gr_construct_gene_csched()
2151 	xf_emit(ctx, 1, 0);		/* 0000000f turing UNK2A0 */  in nv50_gr_construct_gene_csched()
2152 	xf_emit(ctx, 1, 0);		/* 0000ffff GRIDID */  in nv50_gr_construct_gene_csched()
2153 	xf_emit(ctx, 1, 0x10001);	/* ffffffff GRIDDIM_XY */  in nv50_gr_construct_gene_csched()
2154 	xf_emit(ctx, 1, 0);		/* ffffffff */  in nv50_gr_construct_gene_csched()
2155 	xf_emit(ctx, 1, 0x10001);	/* ffffffff BLOCKDIM_XY */  in nv50_gr_construct_gene_csched()
2157 	xf_emit(ctx, 1, 0x10001);	/* 00ffffff BLOCK_ALLOC */  in nv50_gr_construct_gene_csched()
2162 	xf_emit(ctx, 0x40, 0);		/* ffffffff USER_PARAM */  in nv50_gr_construct_gene_csched()
2164 	case 0x50:  in nv50_gr_construct_gene_csched()
2165 	case 0x92:  in nv50_gr_construct_gene_csched()
2166 		xf_emit(ctx, 8, 0);	/* 7, 0, 0, 0, ... */  in nv50_gr_construct_gene_csched()
2167 		xf_emit(ctx, 0x80, 0);	/* fff */  in nv50_gr_construct_gene_csched()
2168 		xf_emit(ctx, 2, 0);	/* ff, fff */  in nv50_gr_construct_gene_csched()
2169 		xf_emit(ctx, 0x10*2, 0);	/* ffffffff, 1f */  in nv50_gr_construct_gene_csched()
2171 	case 0x84:  in nv50_gr_construct_gene_csched()
2172 		xf_emit(ctx, 8, 0);	/* 7, 0, 0, 0, ... */  in nv50_gr_construct_gene_csched()
2173 		xf_emit(ctx, 0x60, 0);	/* fff */  in nv50_gr_construct_gene_csched()
2174 		xf_emit(ctx, 2, 0);	/* ff, fff */  in nv50_gr_construct_gene_csched()
2175 		xf_emit(ctx, 0xc*2, 0);	/* ffffffff, 1f */  in nv50_gr_construct_gene_csched()
2177 	case 0x94:  in nv50_gr_construct_gene_csched()
2178 	case 0x96:  in nv50_gr_construct_gene_csched()
2179 		xf_emit(ctx, 8, 0);	/* 7, 0, 0, 0, ... */  in nv50_gr_construct_gene_csched()
2180 		xf_emit(ctx, 0x40, 0);	/* fff */  in nv50_gr_construct_gene_csched()
2181 		xf_emit(ctx, 2, 0);	/* ff, fff */  in nv50_gr_construct_gene_csched()
2182 		xf_emit(ctx, 8*2, 0);	/* ffffffff, 1f */  in nv50_gr_construct_gene_csched()
2184 	case 0x86:  in nv50_gr_construct_gene_csched()
2185 	case 0x98:  in nv50_gr_construct_gene_csched()
2186 		xf_emit(ctx, 4, 0);	/* f, 0, 0, 0 */  in nv50_gr_construct_gene_csched()
2187 		xf_emit(ctx, 0x10, 0);	/* fff */  in nv50_gr_construct_gene_csched()
2188 		xf_emit(ctx, 2, 0);	/* ff, fff */  in nv50_gr_construct_gene_csched()
2189 		xf_emit(ctx, 2*2, 0);	/* ffffffff, 1f */  in nv50_gr_construct_gene_csched()
2191 	case 0xa0:  in nv50_gr_construct_gene_csched()
2192 		xf_emit(ctx, 8, 0);	/* 7, 0, 0, 0, ... */  in nv50_gr_construct_gene_csched()
2193 		xf_emit(ctx, 0xf0, 0);	/* fff */  in nv50_gr_construct_gene_csched()
2194 		xf_emit(ctx, 2, 0);	/* ff, fff */  in nv50_gr_construct_gene_csched()
2195 		xf_emit(ctx, 0x1e*2, 0);	/* ffffffff, 1f */  in nv50_gr_construct_gene_csched()
2197 	case 0xa3:  in nv50_gr_construct_gene_csched()
2198 		xf_emit(ctx, 8, 0);	/* 7, 0, 0, 0, ... */  in nv50_gr_construct_gene_csched()
2199 		xf_emit(ctx, 0x60, 0);	/* fff */  in nv50_gr_construct_gene_csched()
2200 		xf_emit(ctx, 2, 0);	/* ff, fff */  in nv50_gr_construct_gene_csched()
2201 		xf_emit(ctx, 0xc*2, 0);	/* ffffffff, 1f */  in nv50_gr_construct_gene_csched()
2203 	case 0xa5:  in nv50_gr_construct_gene_csched()
2204 	case 0xaf:  in nv50_gr_construct_gene_csched()
2205 		xf_emit(ctx, 8, 0);	/* 7, 0, 0, 0, ... */  in nv50_gr_construct_gene_csched()
2206 		xf_emit(ctx, 0x30, 0);	/* fff */  in nv50_gr_construct_gene_csched()
2207 		xf_emit(ctx, 2, 0);	/* ff, fff */  in nv50_gr_construct_gene_csched()
2208 		xf_emit(ctx, 6*2, 0);	/* ffffffff, 1f */  in nv50_gr_construct_gene_csched()
2210 	case 0xaa:  in nv50_gr_construct_gene_csched()
2211 		xf_emit(ctx, 0x12, 0);  in nv50_gr_construct_gene_csched()
2213 	case 0xa8:  in nv50_gr_construct_gene_csched()
2214 	case 0xac:  in nv50_gr_construct_gene_csched()
2215 		xf_emit(ctx, 4, 0);	/* f, 0, 0, 0 */  in nv50_gr_construct_gene_csched()
2216 		xf_emit(ctx, 0x10, 0);	/* fff */  in nv50_gr_construct_gene_csched()
2217 		xf_emit(ctx, 2, 0);	/* ff, fff */  in nv50_gr_construct_gene_csched()
2218 		xf_emit(ctx, 2*2, 0);	/* ffffffff, 1f */  in nv50_gr_construct_gene_csched()
2221 	xf_emit(ctx, 1, 0);		/* 0000000f */  in nv50_gr_construct_gene_csched()
2222 	xf_emit(ctx, 1, 0);		/* 00000000 */  in nv50_gr_construct_gene_csched()
2223 	xf_emit(ctx, 1, 0);		/* ffffffff */  in nv50_gr_construct_gene_csched()
2224 	xf_emit(ctx, 1, 0);		/* 0000001f */  in nv50_gr_construct_gene_csched()
2225 	xf_emit(ctx, 4, 0);		/* ffffffff */  in nv50_gr_construct_gene_csched()
2226 	xf_emit(ctx, 1, 0);		/* 00000003 turing UNK35C */  in nv50_gr_construct_gene_csched()
2227 	xf_emit(ctx, 1, 0);		/* ffffffff */  in nv50_gr_construct_gene_csched()
2228 	xf_emit(ctx, 4, 0);		/* ffffffff */  in nv50_gr_construct_gene_csched()
2229 	xf_emit(ctx, 1, 0);		/* 00000003 turing UNK35C */  in nv50_gr_construct_gene_csched()
2230 	xf_emit(ctx, 1, 0);		/* ffffffff */  in nv50_gr_construct_gene_csched()
2231 	xf_emit(ctx, 1, 0);		/* 000000ff */  in nv50_gr_construct_gene_csched()
2238 	xf_emit(ctx, 2, 0);		/* 00007fff WINDOW_OFFSET_XY */  in nv50_gr_construct_gene_unk1cxx()
2239 	xf_emit(ctx, 1, 0x3f800000);	/* ffffffff LINE_WIDTH */  in nv50_gr_construct_gene_unk1cxx()
2240 	xf_emit(ctx, 1, 0);		/* 00000001 LINE_SMOOTH_ENABLE */  in nv50_gr_construct_gene_unk1cxx()
2241 	xf_emit(ctx, 1, 0);		/* 00000001 tesla UNK1658 */  in nv50_gr_construct_gene_unk1cxx()
2242 	xf_emit(ctx, 1, 0);		/* 00000001 POLYGON_SMOOTH_ENABLE */  in nv50_gr_construct_gene_unk1cxx()
2243 	xf_emit(ctx, 3, 0);		/* 00000001 POLYGON_OFFSET_*_ENABLE */  in nv50_gr_construct_gene_unk1cxx()
2245 	xf_emit(ctx, 1, 0x1a);		/* 0000001f POLYGON_MODE */  in nv50_gr_construct_gene_unk1cxx()
2246 	xf_emit(ctx, 1, 0);		/* 0000000f ZETA_FORMAT */  in nv50_gr_construct_gene_unk1cxx()
2247 	xf_emit(ctx, 1, 0);		/* 00000001 POINT_SPRITE_ENABLE */  in nv50_gr_construct_gene_unk1cxx()
2249 	xf_emit(ctx, 0x10, 0);		/* 00000001 SCISSOR_ENABLE */  in nv50_gr_construct_gene_unk1cxx()
2250 	xf_emit(ctx, 1, 0);		/* 00000001 tesla UNK1534 */  in nv50_gr_construct_gene_unk1cxx()
2251 	xf_emit(ctx, 1, 0);		/* 00000001 LINE_STIPPLE_ENABLE */  in nv50_gr_construct_gene_unk1cxx()
2252 	xf_emit(ctx, 1, 0x00ffff00);	/* 00ffffff LINE_STIPPLE_PATTERN */  in nv50_gr_construct_gene_unk1cxx()
2253 	xf_emit(ctx, 1, 0);		/* ffffffff POLYGON_OFFSET_UNITS */  in nv50_gr_construct_gene_unk1cxx()
2254 	xf_emit(ctx, 1, 0);		/* ffffffff POLYGON_OFFSET_FACTOR */  in nv50_gr_construct_gene_unk1cxx()
2255 	xf_emit(ctx, 1, 0);		/* 00000003 tesla UNK1668 */  in nv50_gr_construct_gene_unk1cxx()
2256 	xf_emit(ctx, 2, 0);		/* 07ffffff SCREEN_SCISSOR */  in nv50_gr_construct_gene_unk1cxx()
2257 	xf_emit(ctx, 1, 0);		/* 00000001 tesla UNK1900 */  in nv50_gr_construct_gene_unk1cxx()
2258 	xf_emit(ctx, 1, 0xf);		/* 0000000f COLOR_MASK */  in nv50_gr_construct_gene_unk1cxx()
2259 	xf_emit(ctx, 7, 0);		/* 0000000f COLOR_MASK */  in nv50_gr_construct_gene_unk1cxx()
2260 	xf_emit(ctx, 1, 0x0fac6881);	/* 0fffffff RT_CONTROL */  in nv50_gr_construct_gene_unk1cxx()
2261 	xf_emit(ctx, 1, 0x11);		/* 0000007f RT_FORMAT */  in nv50_gr_construct_gene_unk1cxx()
2262 	xf_emit(ctx, 7, 0);		/* 0000007f RT_FORMAT */  in nv50_gr_construct_gene_unk1cxx()
2263 	xf_emit(ctx, 8, 0);		/* 00000001 RT_HORIZ_LINEAR */  in nv50_gr_construct_gene_unk1cxx()
2265 	xf_emit(ctx, 1, 0);		/* 00000001 ALPHA_TEST_ENABLE */  in nv50_gr_construct_gene_unk1cxx()
2266 	xf_emit(ctx, 1, 0);		/* 00000007 ALPHA_TEST_FUNC */  in nv50_gr_construct_gene_unk1cxx()
2269 	else if (device->chipset >= 0xa0)  in nv50_gr_construct_gene_unk1cxx()
2271 	xf_emit(ctx, 1, 0);		/* 00000003 MULTISAMPLE_CTRL */  in nv50_gr_construct_gene_unk1cxx()
2272 	xf_emit(ctx, 1, 0);		/* 00000003 tesla UNK0F90 */  in nv50_gr_construct_gene_unk1cxx()
2274 	xf_emit(ctx, 2, 0x04000000);	/* 07ffffff tesla UNK0D6C */  in nv50_gr_construct_gene_unk1cxx()
2275 	xf_emit(ctx, 1, 0);		/* 000000ff STENCIL_FRONT_MASK */  in nv50_gr_construct_gene_unk1cxx()
2276 	xf_emit(ctx, 1, 0);		/* 00000001 DEPTH_WRITE_ENABLE */  in nv50_gr_construct_gene_unk1cxx()
2277 	xf_emit(ctx, 1, 0);		/* 00000001 SAMPLECNT_ENABLE */  in nv50_gr_construct_gene_unk1cxx()
2279 	xf_emit(ctx, 1, 0x52);		/* 000001ff SEMANTIC_PTSZ */  in nv50_gr_construct_gene_unk1cxx()
2280 	xf_emit(ctx, 1, 0);		/* ffffffff POINT_SIZE */  in nv50_gr_construct_gene_unk1cxx()
2281 	xf_emit(ctx, 1, 0);		/* 00000001 */  in nv50_gr_construct_gene_unk1cxx()
2282 	xf_emit(ctx, 1, 0);		/* 00000007 tesla UNK0FB4 */  in nv50_gr_construct_gene_unk1cxx()
2283 	if (device->chipset != 0x50) {  in nv50_gr_construct_gene_unk1cxx()
2284 		xf_emit(ctx, 1, 0);	/* 3ff */  in nv50_gr_construct_gene_unk1cxx()
2288 		xf_emit(ctx, 1, 0);	/* 00000003 tesla UNK1928 */  in nv50_gr_construct_gene_unk1cxx()
2289 	xf_emit(ctx, 0x10, 0);		/* ffffffff DEPTH_RANGE_NEAR */  in nv50_gr_construct_gene_unk1cxx()
2290 	xf_emit(ctx, 0x10, 0x3f800000);	/* ffffffff DEPTH_RANGE_FAR */  in nv50_gr_construct_gene_unk1cxx()
2291 	xf_emit(ctx, 1, 0x10);		/* 000000ff VIEW_VOLUME_CLIP_CTRL */  in nv50_gr_construct_gene_unk1cxx()
2292 …xf_emit(ctx, 0x20, 0);		/* 07ffffff VIEWPORT_HORIZ, then VIEWPORT_VERT. (W&0x3fff)<<13 | (X&0x1fff…  in nv50_gr_construct_gene_unk1cxx()
2293 	xf_emit(ctx, 1, 0);		/* ffffffff tesla UNK187C */  in nv50_gr_construct_gene_unk1cxx()
2294 	xf_emit(ctx, 1, 0);		/* 00000003 WINDOW_ORIGIN */  in nv50_gr_construct_gene_unk1cxx()
2295 	xf_emit(ctx, 1, 0);		/* 00000001 STENCIL_FRONT_ENABLE */  in nv50_gr_construct_gene_unk1cxx()
2296 	xf_emit(ctx, 1, 0);		/* 00000001 DEPTH_TEST_ENABLE */  in nv50_gr_construct_gene_unk1cxx()
2297 	xf_emit(ctx, 1, 0);		/* 00000001 STENCIL_BACK_ENABLE */  in nv50_gr_construct_gene_unk1cxx()
2298 	xf_emit(ctx, 1, 0);		/* 000000ff STENCIL_BACK_MASK */  in nv50_gr_construct_gene_unk1cxx()
2299 	xf_emit(ctx, 1, 0x8100c12);	/* 1fffffff FP_INTERPOLANT_CTRL */  in nv50_gr_construct_gene_unk1cxx()
2301 	xf_emit(ctx, 1, 0);		/* 00000007 MULTISAMPLE_SAMPLES_LOG2 */  in nv50_gr_construct_gene_unk1cxx()
2302 	xf_emit(ctx, 1, 0);		/* 000000ff tesla UNK1A20 */  in nv50_gr_construct_gene_unk1cxx()
2304 	xf_emit(ctx, 1, 0);		/* 00000001 VERTEX_TWO_SIDE_ENABLE */  in nv50_gr_construct_gene_unk1cxx()
2305 	xf_emit(ctx, 4, 0xffff);	/* 0000ffff MSAA_MASK */  in nv50_gr_construct_gene_unk1cxx()
2306 	if (device->chipset != 0x50)  in nv50_gr_construct_gene_unk1cxx()
2308 	if (device->chipset < 0xa0)  in nv50_gr_construct_gene_unk1cxx()
2309 		xf_emit(ctx, 0x1c, 0);	/* RO */  in nv50_gr_construct_gene_unk1cxx()
2311 		xf_emit(ctx, 0x9, 0);  in nv50_gr_construct_gene_unk1cxx()
2312 	xf_emit(ctx, 1, 0);		/* 00000001 UNK1534 */  in nv50_gr_construct_gene_unk1cxx()
2313 	xf_emit(ctx, 1, 0);		/* 00000001 LINE_SMOOTH_ENABLE */  in nv50_gr_construct_gene_unk1cxx()
2314 	xf_emit(ctx, 1, 0);		/* 00000001 LINE_STIPPLE_ENABLE */  in nv50_gr_construct_gene_unk1cxx()
2315 	xf_emit(ctx, 1, 0x00ffff00);	/* 00ffffff LINE_STIPPLE_PATTERN */  in nv50_gr_construct_gene_unk1cxx()
2316 	xf_emit(ctx, 1, 0x1a);		/* 0000001f POLYGON_MODE */  in nv50_gr_construct_gene_unk1cxx()
2317 	xf_emit(ctx, 1, 0);		/* 00000003 WINDOW_ORIGIN */  in nv50_gr_construct_gene_unk1cxx()
2318 	if (device->chipset != 0x50) {  in nv50_gr_construct_gene_unk1cxx()
2320 		xf_emit(ctx, 1, 0);	/* 3ff */  in nv50_gr_construct_gene_unk1cxx()
2324 	if (device->chipset < 0xa0)  in nv50_gr_construct_gene_unk1cxx()
2325 		xf_emit(ctx, 0x25, 0);  in nv50_gr_construct_gene_unk1cxx()
2327 		xf_emit(ctx, 0x3b, 0);  in nv50_gr_construct_gene_unk1cxx()
2334 	xf_emit(ctx, 1, 0x102);		/* 0000ffff STRMOUT_BUFFER_CTRL */  in nv50_gr_construct_gene_strmout()
2335 	xf_emit(ctx, 1, 0);		/* ffffffff STRMOUT_PRIMITIVE_COUNT */  in nv50_gr_construct_gene_strmout()
2337 	if (device->chipset >= 0xa0) {  in nv50_gr_construct_gene_strmout()
2338 		xf_emit(ctx, 4, 0);	/* ffffffff UNK1A8C */  in nv50_gr_construct_gene_strmout()
2339 		xf_emit(ctx, 4, 0);	/* ffffffff UNK1780 */  in nv50_gr_construct_gene_strmout()
2343 	xf_emit(ctx, 1, 0);		/* 00000001 GP_ENABLE */  in nv50_gr_construct_gene_strmout()
2344 	if (device->chipset == 0x50)  in nv50_gr_construct_gene_strmout()
2345 		xf_emit(ctx, 1, 0x3ff);	/* 000003ff tesla UNK0D68 */  in nv50_gr_construct_gene_strmout()
2347 		xf_emit(ctx, 1, 0x7ff);	/* 000007ff tesla UNK0D68 */  in nv50_gr_construct_gene_strmout()
2348 	xf_emit(ctx, 1, 0);		/* ffffffff tesla UNK1A30 */  in nv50_gr_construct_gene_strmout()
2350 	xf_emit(ctx, 1, 0x102);		/* 0000ffff STRMOUT_BUFFER_CTRL */  in nv50_gr_construct_gene_strmout()
2351 	xf_emit(ctx, 1, 0);		/* ffffffff STRMOUT_PRIMITIVE_COUNT */  in nv50_gr_construct_gene_strmout()
2352 	xf_emit(ctx, 4, 0);		/* 000000ff STRMOUT_ADDRESS_HIGH */  in nv50_gr_construct_gene_strmout()
2353 	xf_emit(ctx, 4, 0);		/* ffffffff STRMOUT_ADDRESS_LOW */  in nv50_gr_construct_gene_strmout()
2355 	if (device->chipset >= 0xa0) {  in nv50_gr_construct_gene_strmout()
2356 		xf_emit(ctx, 4, 0);	/* ffffffff UNK1A8C */  in nv50_gr_construct_gene_strmout()
2357 		xf_emit(ctx, 4, 0);	/* ffffffff UNK1780 */  in nv50_gr_construct_gene_strmout()
2359 	xf_emit(ctx, 1, 0);		/* 0000ffff DMA_STRMOUT */  in nv50_gr_construct_gene_strmout()
2360 	xf_emit(ctx, 1, 0);		/* 0000ffff DMA_QUERY */  in nv50_gr_construct_gene_strmout()
2361 	xf_emit(ctx, 1, 0);		/* 000000ff QUERY_ADDRESS_HIGH */  in nv50_gr_construct_gene_strmout()
2362 	xf_emit(ctx, 2, 0);		/* ffffffff QUERY_ADDRESS_LOW QUERY_COUNTER */  in nv50_gr_construct_gene_strmout()
2363 	xf_emit(ctx, 2, 0);		/* ffffffff */  in nv50_gr_construct_gene_strmout()
2364 	xf_emit(ctx, 1, 0);		/* ffffffff tesla UNK1A30 */  in nv50_gr_construct_gene_strmout()
2366 	xf_emit(ctx, 0x20, 0);		/* ffffffff STRMOUT_MAP */  in nv50_gr_construct_gene_strmout()
2367 	xf_emit(ctx, 1, 0);		/* 0000000f */  in nv50_gr_construct_gene_strmout()
2368 	xf_emit(ctx, 1, 0);		/* 00000000? */  in nv50_gr_construct_gene_strmout()
2369 	xf_emit(ctx, 2, 0);		/* ffffffff */  in nv50_gr_construct_gene_strmout()
2376 	xf_emit(ctx, 1, 0x4e3bfdf);	/* ffffffff UNK0D64 */  in nv50_gr_construct_gene_ropm1()
2377 	xf_emit(ctx, 1, 0x4e3bfdf);	/* ffffffff UNK0DF4 */  in nv50_gr_construct_gene_ropm1()
2378 	xf_emit(ctx, 1, 0);		/* 00000007 */  in nv50_gr_construct_gene_ropm1()
2379 	xf_emit(ctx, 1, 0);		/* 000003ff */  in nv50_gr_construct_gene_ropm1()
2381 		xf_emit(ctx, 1, 0x11);	/* 000000ff tesla UNK1968 */  in nv50_gr_construct_gene_ropm1()
2382 	xf_emit(ctx, 1, 0);		/* ffffffff tesla UNK1A3C */  in nv50_gr_construct_gene_ropm1()
2390 	xf_emit(ctx, 1, 0);		/* 0000ffff DMA_QUERY */  in nv50_gr_construct_gene_ropm2()
2391 	xf_emit(ctx, 1, 0x0fac6881);	/* 0fffffff RT_CONTROL */  in nv50_gr_construct_gene_ropm2()
2392 	xf_emit(ctx, 2, 0);		/* ffffffff */  in nv50_gr_construct_gene_ropm2()
2393 	xf_emit(ctx, 1, 0);		/* 000000ff QUERY_ADDRESS_HIGH */  in nv50_gr_construct_gene_ropm2()
2394 	xf_emit(ctx, 2, 0);		/* ffffffff QUERY_ADDRESS_LOW, COUNTER */  in nv50_gr_construct_gene_ropm2()
2395 	xf_emit(ctx, 1, 0);		/* 00000001 SAMPLECNT_ENABLE */  in nv50_gr_construct_gene_ropm2()
2396 	xf_emit(ctx, 1, 0);		/* 7 */  in nv50_gr_construct_gene_ropm2()
2398 	xf_emit(ctx, 1, 0);		/* 0000ffff DMA_QUERY */  in nv50_gr_construct_gene_ropm2()
2399 	xf_emit(ctx, 1, 0);		/* 000000ff QUERY_ADDRESS_HIGH */  in nv50_gr_construct_gene_ropm2()
2400 	xf_emit(ctx, 2, 0);		/* ffffffff QUERY_ADDRESS_LOW, COUNTER */  in nv50_gr_construct_gene_ropm2()
2401 	xf_emit(ctx, 1, 0x4e3bfdf);	/* ffffffff UNK0D64 */  in nv50_gr_construct_gene_ropm2()
2402 	xf_emit(ctx, 1, 0x4e3bfdf);	/* ffffffff UNK0DF4 */  in nv50_gr_construct_gene_ropm2()
2403 	xf_emit(ctx, 1, 0);		/* 00000001 eng2d UNK260 */  in nv50_gr_construct_gene_ropm2()
2404 	xf_emit(ctx, 1, 0);		/* ff/3ff */  in nv50_gr_construct_gene_ropm2()
2405 	xf_emit(ctx, 1, 0);		/* 00000007 */  in nv50_gr_construct_gene_ropm2()
2407 		xf_emit(ctx, 1, 0x11);	/* 000000ff tesla UNK1968 */  in nv50_gr_construct_gene_ropm2()
2408 	xf_emit(ctx, 1, 0);		/* ffffffff tesla UNK1A3C */  in nv50_gr_construct_gene_ropm2()
2416 	if (device->chipset == 0x50) {  in nv50_gr_construct_gene_ropc()
2417 		magic2 = 0x00003e60;  in nv50_gr_construct_gene_ropc()
2419 		magic2 = 0x001ffe67;  in nv50_gr_construct_gene_ropc()
2421 		magic2 = 0x00087e67;  in nv50_gr_construct_gene_ropc()
2423 	xf_emit(ctx, 1, 0);		/* f/7 MUTISAMPLE_SAMPLES_LOG2 */  in nv50_gr_construct_gene_ropc()
2424 	xf_emit(ctx, 1, 0);		/* 00000001 tesla UNK1534 */  in nv50_gr_construct_gene_ropc()
2425 	xf_emit(ctx, 1, 0);		/* 00000007 STENCIL_BACK_FUNC_FUNC */  in nv50_gr_construct_gene_ropc()
2426 	xf_emit(ctx, 1, 0);		/* 000000ff STENCIL_BACK_FUNC_MASK */  in nv50_gr_construct_gene_ropc()
2427 	xf_emit(ctx, 1, 0);		/* 000000ff STENCIL_BACK_MASK */  in nv50_gr_construct_gene_ropc()
2428 	xf_emit(ctx, 3, 0);		/* 00000007 STENCIL_BACK_OP_FAIL, ZFAIL, ZPASS */  in nv50_gr_construct_gene_ropc()
2430 	xf_emit(ctx, 1, 0);		/* ffff0ff3 */  in nv50_gr_construct_gene_ropc()
2432 	xf_emit(ctx, 1, 0);		/* 00000001 DEPTH_BOUNDS_EN */  in nv50_gr_construct_gene_ropc()
2433 	xf_emit(ctx, 1, 0);		/* 00000007 DEPTH_TEST_FUNC */  in nv50_gr_construct_gene_ropc()
2434 	xf_emit(ctx, 1, 0);		/* 00000001 DEPTH_TEST_ENABLE */  in nv50_gr_construct_gene_ropc()
2435 	xf_emit(ctx, 1, 0);		/* 00000001 DEPTH_WRITE_ENABLE */  in nv50_gr_construct_gene_ropc()
2438 	xf_emit(ctx, 1, 0);		/* 00000007 STENCIL_FRONT_FUNC_FUNC */  in nv50_gr_construct_gene_ropc()
2439 	xf_emit(ctx, 1, 0);		/* 000000ff STENCIL_FRONT_FUNC_MASK */  in nv50_gr_construct_gene_ropc()
2440 	xf_emit(ctx, 1, 0);		/* 000000ff STENCIL_FRONT_MASK */  in nv50_gr_construct_gene_ropc()
2441 	xf_emit(ctx, 3, 0);		/* 00000007 STENCIL_FRONT_OP_FAIL, ZFAIL, ZPASS */  in nv50_gr_construct_gene_ropc()
2442 	xf_emit(ctx, 1, 0);		/* 00000001 STENCIL_FRONT_ENABLE */  in nv50_gr_construct_gene_ropc()
2443 	if (device->chipset >= 0xa0 && !IS_NVAAF(device->chipset))  in nv50_gr_construct_gene_ropc()
2444 		xf_emit(ctx, 1, 0x15);	/* 000000ff */  in nv50_gr_construct_gene_ropc()
2445 	xf_emit(ctx, 1, 0);		/* 00000001 STENCIL_BACK_ENABLE */  in nv50_gr_construct_gene_ropc()
2447 	xf_emit(ctx, 1, 0x10);		/* 3ff/ff VIEW_VOLUME_CLIP_CTRL */  in nv50_gr_construct_gene_ropc()
2448 	xf_emit(ctx, 1, 0);		/* ffffffff CLEAR_DEPTH */  in nv50_gr_construct_gene_ropc()
2449 	xf_emit(ctx, 1, 0);		/* 0000000f ZETA_FORMAT */  in nv50_gr_construct_gene_ropc()
2451 	xf_emit(ctx, 1, 0);		/* ffffffff tesla UNK1A3C */  in nv50_gr_construct_gene_ropc()
2452 …if (device->chipset == 0x86 || device->chipset == 0x92 || device->chipset == 0x98 || device->chips…  in nv50_gr_construct_gene_ropc()
2453 		xf_emit(ctx, 3, 0);	/* ff, ffffffff, ffffffff */  in nv50_gr_construct_gene_ropc()
2455 		xf_emit(ctx, 1, 0x400);	/* fffffff */  in nv50_gr_construct_gene_ropc()
2456 		xf_emit(ctx, 1, 0x300);	/* ffff */  in nv50_gr_construct_gene_ropc()
2457 		xf_emit(ctx, 1, 0x1001);	/* 1fff */  in nv50_gr_construct_gene_ropc()
2458 		if (device->chipset != 0xa0) {  in nv50_gr_construct_gene_ropc()
2460 				xf_emit(ctx, 1, 0);	/* 0000000f UNK15C8 */  in nv50_gr_construct_gene_ropc()
2462 				xf_emit(ctx, 1, 0x15);	/* ff */  in nv50_gr_construct_gene_ropc()
2465 	xf_emit(ctx, 1, 0);		/* 00000007 MULTISAMPLE_SAMPLES_LOG2 */  in nv50_gr_construct_gene_ropc()
2466 	xf_emit(ctx, 1, 0);		/* 00000001 tesla UNK1534 */  in nv50_gr_construct_gene_ropc()
2467 	xf_emit(ctx, 1, 0);		/* 00000007 STENCIL_BACK_FUNC_FUNC */  in nv50_gr_construct_gene_ropc()
2468 	xf_emit(ctx, 1, 0);		/* 000000ff STENCIL_BACK_FUNC_MASK */  in nv50_gr_construct_gene_ropc()
2469 	xf_emit(ctx, 1, 0);		/* ffff0ff3 */  in nv50_gr_construct_gene_ropc()
2471 	xf_emit(ctx, 1, 0);		/* 00000001 DEPTH_BOUNDS_EN */  in nv50_gr_construct_gene_ropc()
2472 	xf_emit(ctx, 1, 0);		/* 00000007 DEPTH_TEST_FUNC */  in nv50_gr_construct_gene_ropc()
2473 	xf_emit(ctx, 1, 0);		/* 00000001 DEPTH_TEST_ENABLE */  in nv50_gr_construct_gene_ropc()
2474 	xf_emit(ctx, 1, 0);		/* 00000001 DEPTH_WRITE_ENABLE */  in nv50_gr_construct_gene_ropc()
2475 	xf_emit(ctx, 1, 0);		/* 00000007 STENCIL_FRONT_FUNC_FUNC */  in nv50_gr_construct_gene_ropc()
2476 	xf_emit(ctx, 1, 0);		/* 000000ff STENCIL_FRONT_FUNC_MASK */  in nv50_gr_construct_gene_ropc()
2477 	xf_emit(ctx, 1, 0);		/* 00000001 STENCIL_FRONT_ENABLE */  in nv50_gr_construct_gene_ropc()
2478 	xf_emit(ctx, 1, 0);		/* 00000001 STENCIL_BACK_ENABLE */  in nv50_gr_construct_gene_ropc()
2480 	xf_emit(ctx, 1, 0x10);		/* 7f/ff VIEW_VOLUME_CLIP_CTRL */  in nv50_gr_construct_gene_ropc()
2481 	xf_emit(ctx, 1, 0);		/* 0000000f ZETA_FORMAT */  in nv50_gr_construct_gene_ropc()
2483 	xf_emit(ctx, 1, 0);		/* ffffffff tesla UNK1A3C */  in nv50_gr_construct_gene_ropc()
2484 	xf_emit(ctx, 1, 0);		/* 00000001 tesla UNK1534 */  in nv50_gr_construct_gene_ropc()
2485 	xf_emit(ctx, 1, 0);		/* 00000001 tesla UNK1900 */  in nv50_gr_construct_gene_ropc()
2486 	xf_emit(ctx, 1, 0);		/* 00000007 STENCIL_BACK_FUNC_FUNC */  in nv50_gr_construct_gene_ropc()
2487 	xf_emit(ctx, 1, 0);		/* 000000ff STENCIL_BACK_FUNC_MASK */  in nv50_gr_construct_gene_ropc()
2488 	xf_emit(ctx, 1, 0);		/* 000000ff STENCIL_BACK_FUNC_REF */  in nv50_gr_construct_gene_ropc()
2489 	xf_emit(ctx, 2, 0);		/* ffffffff DEPTH_BOUNDS */  in nv50_gr_construct_gene_ropc()
2490 	xf_emit(ctx, 1, 0);		/* 00000001 DEPTH_BOUNDS_EN */  in nv50_gr_construct_gene_ropc()
2491 	xf_emit(ctx, 1, 0);		/* 00000007 DEPTH_TEST_FUNC */  in nv50_gr_construct_gene_ropc()
2492 	xf_emit(ctx, 1, 0);		/* 00000001 DEPTH_TEST_ENABLE */  in nv50_gr_construct_gene_ropc()
2493 	xf_emit(ctx, 1, 0);		/* 00000001 DEPTH_WRITE_ENABLE */  in nv50_gr_construct_gene_ropc()
2494 	xf_emit(ctx, 1, 0);		/* 0000000f */  in nv50_gr_construct_gene_ropc()
2495 	xf_emit(ctx, 1, 0);		/* 00000001 tesla UNK0FB0 */  in nv50_gr_construct_gene_ropc()
2496 	xf_emit(ctx, 1, 0);		/* 00000007 STENCIL_FRONT_FUNC_FUNC */  in nv50_gr_construct_gene_ropc()
2497 	xf_emit(ctx, 1, 0);		/* 000000ff STENCIL_FRONT_FUNC_MASK */  in nv50_gr_construct_gene_ropc()
2498 	xf_emit(ctx, 1, 0);		/* 000000ff STENCIL_FRONT_FUNC_REF */  in nv50_gr_construct_gene_ropc()
2499 	xf_emit(ctx, 1, 0);		/* 00000001 STENCIL_FRONT_ENABLE */  in nv50_gr_construct_gene_ropc()
2500 	xf_emit(ctx, 1, 0);		/* 00000001 STENCIL_BACK_ENABLE */  in nv50_gr_construct_gene_ropc()
2501 	xf_emit(ctx, 1, 0x10);		/* 7f/ff VIEW_VOLUME_CLIP_CTRL */  in nv50_gr_construct_gene_ropc()
2502 	xf_emit(ctx, 0x10, 0);		/* ffffffff DEPTH_RANGE_NEAR */  in nv50_gr_construct_gene_ropc()
2503 	xf_emit(ctx, 0x10, 0x3f800000);	/* ffffffff DEPTH_RANGE_FAR */  in nv50_gr_construct_gene_ropc()
2504 	xf_emit(ctx, 1, 0);		/* 0000000f ZETA_FORMAT */  in nv50_gr_construct_gene_ropc()
2505 	xf_emit(ctx, 1, 0);		/* 00000007 MULTISAMPLE_SAMPLES_LOG2 */  in nv50_gr_construct_gene_ropc()
2506 	xf_emit(ctx, 1, 0);		/* 00000007 STENCIL_BACK_FUNC_FUNC */  in nv50_gr_construct_gene_ropc()
2507 	xf_emit(ctx, 1, 0);		/* 000000ff STENCIL_BACK_FUNC_MASK */  in nv50_gr_construct_gene_ropc()
2508 	xf_emit(ctx, 1, 0);		/* 000000ff STENCIL_BACK_FUNC_REF */  in nv50_gr_construct_gene_ropc()
2509 	xf_emit(ctx, 1, 0);		/* 000000ff STENCIL_BACK_MASK */  in nv50_gr_construct_gene_ropc()
2510 	xf_emit(ctx, 3, 0);		/* 00000007 STENCIL_BACK_OP_FAIL, ZFAIL, ZPASS */  in nv50_gr_construct_gene_ropc()
2511 	xf_emit(ctx, 2, 0);		/* ffffffff DEPTH_BOUNDS */  in nv50_gr_construct_gene_ropc()
2512 	xf_emit(ctx, 1, 0);		/* 00000001 DEPTH_BOUNDS_EN */  in nv50_gr_construct_gene_ropc()
2513 	xf_emit(ctx, 1, 0);		/* 00000007 DEPTH_TEST_FUNC */  in nv50_gr_construct_gene_ropc()
2514 	xf_emit(ctx, 1, 0);		/* 00000001 DEPTH_TEST_ENABLE */  in nv50_gr_construct_gene_ropc()
2515 	xf_emit(ctx, 1, 0);		/* 00000001 DEPTH_WRITE_ENABLE */  in nv50_gr_construct_gene_ropc()
2516 	xf_emit(ctx, 1, 0);		/* 000000ff CLEAR_STENCIL */  in nv50_gr_construct_gene_ropc()
2517 	xf_emit(ctx, 1, 0);		/* 00000007 STENCIL_FRONT_FUNC_FUNC */  in nv50_gr_construct_gene_ropc()
2518 	xf_emit(ctx, 1, 0);		/* 000000ff STENCIL_FRONT_FUNC_MASK */  in nv50_gr_construct_gene_ropc()
2519 	xf_emit(ctx, 1, 0);		/* 000000ff STENCIL_FRONT_FUNC_REF */  in nv50_gr_construct_gene_ropc()
2520 	xf_emit(ctx, 1, 0);		/* 000000ff STENCIL_FRONT_MASK */  in nv50_gr_construct_gene_ropc()
2521 	xf_emit(ctx, 3, 0);		/* 00000007 STENCIL_FRONT_OP_FAIL, ZFAIL, ZPASS */  in nv50_gr_construct_gene_ropc()
2522 	xf_emit(ctx, 1, 0);		/* 00000001 STENCIL_FRONT_ENABLE */  in nv50_gr_construct_gene_ropc()
2523 	xf_emit(ctx, 1, 0);		/* 00000001 STENCIL_BACK_ENABLE */  in nv50_gr_construct_gene_ropc()
2524 	xf_emit(ctx, 1, 0x10);		/* 7f/ff VIEW_VOLUME_CLIP_CTRL */  in nv50_gr_construct_gene_ropc()
2525 	xf_emit(ctx, 1, 0);		/* 0000000f ZETA_FORMAT */  in nv50_gr_construct_gene_ropc()
2526 	xf_emit(ctx, 1, 0x3f);		/* 0000003f UNK1590 */  in nv50_gr_construct_gene_ropc()
2527 	xf_emit(ctx, 1, 0);		/* 00000007 MULTISAMPLE_SAMPLES_LOG2 */  in nv50_gr_construct_gene_ropc()
2528 	xf_emit(ctx, 1, 0);		/* 00000001 tesla UNK1534 */  in nv50_gr_construct_gene_ropc()
2529 	xf_emit(ctx, 2, 0);		/* ffff0ff3, ffff */  in nv50_gr_construct_gene_ropc()
2530 	xf_emit(ctx, 1, 0);		/* 00000001 tesla UNK0FB0 */  in nv50_gr_construct_gene_ropc()
2531 	xf_emit(ctx, 1, 0);		/* 0001ffff GP_BUILTIN_RESULT_EN */  in nv50_gr_construct_gene_ropc()
2533 	xf_emit(ctx, 1, 0);		/* 0000000f ZETA_FORMAT */  in nv50_gr_construct_gene_ropc()
2535 	xf_emit(ctx, 1, 0);		/* ffffffff CLEAR_DEPTH */  in nv50_gr_construct_gene_ropc()
2537 	if (device->chipset >= 0xa0) {  in nv50_gr_construct_gene_ropc()
2538 		xf_emit(ctx, 2, 0);  in nv50_gr_construct_gene_ropc()
2539 		xf_emit(ctx, 1, 0x1001);  in nv50_gr_construct_gene_ropc()
2540 		xf_emit(ctx, 0xb, 0);  in nv50_gr_construct_gene_ropc()
2542 		xf_emit(ctx, 1, 0);	/* 00000007 */  in nv50_gr_construct_gene_ropc()
2543 		xf_emit(ctx, 1, 0);	/* 00000001 tesla UNK1534 */  in nv50_gr_construct_gene_ropc()
2544 		xf_emit(ctx, 1, 0);	/* 00000007 MULTISAMPLE_SAMPLES_LOG2 */  in nv50_gr_construct_gene_ropc()
2545 		xf_emit(ctx, 8, 0);	/* 00000001 BLEND_ENABLE */  in nv50_gr_construct_gene_ropc()
2546 		xf_emit(ctx, 1, 0);	/* ffff0ff3 */  in nv50_gr_construct_gene_ropc()
2548 	xf_emit(ctx, 1, 0x11);		/* 3f/7f RT_FORMAT */  in nv50_gr_construct_gene_ropc()
2549 	xf_emit(ctx, 7, 0);		/* 3f/7f RT_FORMAT */  in nv50_gr_construct_gene_ropc()
2550 	xf_emit(ctx, 1, 0xf);		/* 0000000f COLOR_MASK */  in nv50_gr_construct_gene_ropc()
2551 	xf_emit(ctx, 7, 0);		/* 0000000f COLOR_MASK */  in nv50_gr_construct_gene_ropc()
2552 	xf_emit(ctx, 1, 0x11);		/* 3f/7f */  in nv50_gr_construct_gene_ropc()
2553 	xf_emit(ctx, 1, 0);		/* 00000001 LOGIC_OP_ENABLE */  in nv50_gr_construct_gene_ropc()
2554 	if (device->chipset != 0x50) {  in nv50_gr_construct_gene_ropc()
2555 		xf_emit(ctx, 1, 0);	/* 0000000f LOGIC_OP */  in nv50_gr_construct_gene_ropc()
2556 		xf_emit(ctx, 1, 0);	/* 000000ff */  in nv50_gr_construct_gene_ropc()
2558 	xf_emit(ctx, 1, 0);		/* 00000007 OPERATION */  in nv50_gr_construct_gene_ropc()
2559 	xf_emit(ctx, 1, 0);		/* ff/3ff */  in nv50_gr_construct_gene_ropc()
2560 	xf_emit(ctx, 1, 0);		/* 00000003 UNK0F90 */  in nv50_gr_construct_gene_ropc()
2567 	xf_emit(ctx, 1, 0);		/* 00000001 */  in nv50_gr_construct_gene_ropc()
2569 	xf_emit(ctx, 1, 0);		/* ffffffff tesla UNK1A3C */  in nv50_gr_construct_gene_ropc()
2570 	xf_emit(ctx, 1, 0x0fac6881);	/* 0fffffff RT_CONTROL */  in nv50_gr_construct_gene_ropc()
2572 		xf_emit(ctx, 1, 0);	/* 00000001 tesla UNK12E4 */  in nv50_gr_construct_gene_ropc()
2580 		xf_emit(ctx, 1, 0);	/* 00000001 tesla UNK1140 */  in nv50_gr_construct_gene_ropc()
2581 		xf_emit(ctx, 2, 0);	/* 00000001 */  in nv50_gr_construct_gene_ropc()
2583 		xf_emit(ctx, 1, 0);	/* 0000000f */  in nv50_gr_construct_gene_ropc()
2584 		xf_emit(ctx, 1, 0);	/* 00000003 */  in nv50_gr_construct_gene_ropc()
2585 		xf_emit(ctx, 1, 0);	/* ffffffff */  in nv50_gr_construct_gene_ropc()
2586 		xf_emit(ctx, 2, 0);	/* 00000001 */  in nv50_gr_construct_gene_ropc()
2588 		xf_emit(ctx, 1, 0);	/* 00000001 */  in nv50_gr_construct_gene_ropc()
2589 		xf_emit(ctx, 1, 0);	/* 000003ff */  in nv50_gr_construct_gene_ropc()
2590 	} else if (device->chipset >= 0xa0) {  in nv50_gr_construct_gene_ropc()
2591 		xf_emit(ctx, 2, 0);	/* 00000001 */  in nv50_gr_construct_gene_ropc()
2592 		xf_emit(ctx, 1, 0);	/* 00000007 */  in nv50_gr_construct_gene_ropc()
2593 		xf_emit(ctx, 1, 0);	/* 00000003 */  in nv50_gr_construct_gene_ropc()
2594 		xf_emit(ctx, 1, 0);	/* ffffffff */  in nv50_gr_construct_gene_ropc()
2595 		xf_emit(ctx, 2, 0);	/* 00000001 */  in nv50_gr_construct_gene_ropc()
2597 		xf_emit(ctx, 1, 0);	/* 00000007 MULTISAMPLE_SAMPLES_LOG2 */  in nv50_gr_construct_gene_ropc()
2598 		xf_emit(ctx, 1, 0);	/* 00000003 tesla UNK1430 */  in nv50_gr_construct_gene_ropc()
2599 		xf_emit(ctx, 1, 0);	/* ffffffff tesla UNK1A3C */  in nv50_gr_construct_gene_ropc()
2601 	xf_emit(ctx, 4, 0);		/* ffffffff CLEAR_COLOR */  in nv50_gr_construct_gene_ropc()
2602 	xf_emit(ctx, 4, 0);		/* ffffffff BLEND_COLOR A R G B */  in nv50_gr_construct_gene_ropc()
2603 	xf_emit(ctx, 1, 0);		/* 00000fff eng2d UNK2B0 */  in nv50_gr_construct_gene_ropc()
2604 	if (device->chipset >= 0xa0)  in nv50_gr_construct_gene_ropc()
2605 		xf_emit(ctx, 2, 0);	/* 00000001 */  in nv50_gr_construct_gene_ropc()
2606 	xf_emit(ctx, 1, 0);		/* 000003ff */  in nv50_gr_construct_gene_ropc()
2607 	xf_emit(ctx, 8, 0);		/* 00000001 BLEND_ENABLE */  in nv50_gr_construct_gene_ropc()
2615 	xf_emit(ctx, 1, 0);		/* 00000001 UNK19C0 */  in nv50_gr_construct_gene_ropc()
2616 	xf_emit(ctx, 1, 0);		/* 00000001 LOGIC_OP_ENABLE */  in nv50_gr_construct_gene_ropc()
2617 	xf_emit(ctx, 1, 0);		/* 0000000f LOGIC_OP */  in nv50_gr_construct_gene_ropc()
2618 	if (device->chipset >= 0xa0)  in nv50_gr_construct_gene_ropc()
2619 		xf_emit(ctx, 1, 0);	/* 00000001 UNK12E4? NVA3+ only? */  in nv50_gr_construct_gene_ropc()
2628 		xf_emit(ctx, 1, 0);	/* 00000001 tesla UNK15C4 */  in nv50_gr_construct_gene_ropc()
2629 		xf_emit(ctx, 1, 0);	/* 00000001 */  in nv50_gr_construct_gene_ropc()
2630 		xf_emit(ctx, 1, 0);	/* 00000001 tesla UNK1140 */  in nv50_gr_construct_gene_ropc()
2632 	xf_emit(ctx, 1, 0x11);		/* 3f/7f DST_FORMAT */  in nv50_gr_construct_gene_ropc()
2634 	xf_emit(ctx, 1, 0);		/* 00000007 PATTERN_COLOR_FORMAT */  in nv50_gr_construct_gene_ropc()
2635 	xf_emit(ctx, 2, 0);		/* ffffffff PATTERN_MONO_COLOR */  in nv50_gr_construct_gene_ropc()
2636 	xf_emit(ctx, 1, 0);		/* 00000001 PATTERN_MONO_FORMAT */  in nv50_gr_construct_gene_ropc()
2637 	xf_emit(ctx, 2, 0);		/* ffffffff PATTERN_MONO_BITMAP */  in nv50_gr_construct_gene_ropc()
2638 	xf_emit(ctx, 1, 0);		/* 00000003 PATTERN_SELECT */  in nv50_gr_construct_gene_ropc()
2639 	xf_emit(ctx, 1, 0);		/* 000000ff ROP */  in nv50_gr_construct_gene_ropc()
2640 	xf_emit(ctx, 1, 0);		/* ffffffff BETA1 */  in nv50_gr_construct_gene_ropc()
2641 	xf_emit(ctx, 1, 0);		/* ffffffff BETA4 */  in nv50_gr_construct_gene_ropc()
2642 	xf_emit(ctx, 1, 0);		/* 00000007 OPERATION */  in nv50_gr_construct_gene_ropc()
2643 	xf_emit(ctx, 0x50, 0);		/* 10x ffffff, ffffff, ffffff, ffffff, 3 PATTERN */  in nv50_gr_construct_gene_ropc()
2652 	case 0x50:  in nv50_gr_construct_xfer_unk84xx()
2653 		magic3 = 0x1000;  in nv50_gr_construct_xfer_unk84xx()
2655 	case 0x86:  in nv50_gr_construct_xfer_unk84xx()
2656 	case 0x98:  in nv50_gr_construct_xfer_unk84xx()
2657 	case 0xa8:  in nv50_gr_construct_xfer_unk84xx()
2658 	case 0xaa:  in nv50_gr_construct_xfer_unk84xx()
2659 	case 0xac:  in nv50_gr_construct_xfer_unk84xx()
2660 	case 0xaf:  in nv50_gr_construct_xfer_unk84xx()
2661 		magic3 = 0x1e00;  in nv50_gr_construct_xfer_unk84xx()
2664 		magic3 = 0;  in nv50_gr_construct_xfer_unk84xx()
2666 	xf_emit(ctx, 1, 0);		/* 00000001 GP_ENABLE */  in nv50_gr_construct_xfer_unk84xx()
2668 	xf_emit(ctx, 1, 0);		/* 00000001 GP_ENABLE */  in nv50_gr_construct_xfer_unk84xx()
2669 	xf_emit(ctx, 1, 0);		/* ffffffff tesla UNK1A30 */  in nv50_gr_construct_xfer_unk84xx()
2670 	xf_emit(ctx, 1, 0);		/* 111/113[NVA0+] */  in nv50_gr_construct_xfer_unk84xx()
2672 		xf_emit(ctx, 0x1f, 0);	/* ffffffff */  in nv50_gr_construct_xfer_unk84xx()
2673 	else if (device->chipset >= 0xa0)  in nv50_gr_construct_xfer_unk84xx()
2674 		xf_emit(ctx, 0x0f, 0);	/* ffffffff */  in nv50_gr_construct_xfer_unk84xx()
2676 		xf_emit(ctx, 0x10, 0);	/* fffffff VP_RESULT_MAP_1 up */  in nv50_gr_construct_xfer_unk84xx()
2677 	xf_emit(ctx, 2, 0);		/* f/1f[NVA3], fffffff/ffffffff[NVA0+] */  in nv50_gr_construct_xfer_unk84xx()
2680 	if (device->chipset >= 0xa0)  in nv50_gr_construct_xfer_unk84xx()
2681 		xf_emit(ctx, 1, 0x03020100);	/* ffffffff */  in nv50_gr_construct_xfer_unk84xx()
2683 		xf_emit(ctx, 1, 0x00608080);	/* fffffff VP_RESULT_MAP_0 */  in nv50_gr_construct_xfer_unk84xx()
2684 	xf_emit(ctx, 1, 0);		/* 00000001 GP_ENABLE */  in nv50_gr_construct_xfer_unk84xx()
2685 	xf_emit(ctx, 1, 0);		/* ffffffff tesla UNK1A30 */  in nv50_gr_construct_xfer_unk84xx()
2686 	xf_emit(ctx, 2, 0);		/* 111/113, 7f/ff */  in nv50_gr_construct_xfer_unk84xx()
2688 	xf_emit(ctx, 1, 0);		/* ffffffff tesla UNK1A30 */  in nv50_gr_construct_xfer_unk84xx()
2689 	xf_emit(ctx, 1, 0);		/* 00000001 GP_ENABLE */  in nv50_gr_construct_xfer_unk84xx()
2692 	xf_emit(ctx, 1, 0x80);		/* 0000ffff GP_VERTEX_OUTPUT_COUNT */  in nv50_gr_construct_xfer_unk84xx()
2696 	xf_emit(ctx, 1, 0);		/* ffffffff tesla UNK1A30 */  in nv50_gr_construct_xfer_unk84xx()
2697 	xf_emit(ctx, 1, 0);		/* 111/113 */  in nv50_gr_construct_xfer_unk84xx()
2698 	xf_emit(ctx, 0x1f, 0);		/* ffffffff GP_RESULT_MAP_1 up */  in nv50_gr_construct_xfer_unk84xx()
2699 	xf_emit(ctx, 1, 0);		/* 0000001f */  in nv50_gr_construct_xfer_unk84xx()
2700 	xf_emit(ctx, 1, 0);		/* ffffffff */  in nv50_gr_construct_xfer_unk84xx()
2701 	xf_emit(ctx, 1, 0);		/* 00000001 GP_ENABLE */  in nv50_gr_construct_xfer_unk84xx()
2703 	xf_emit(ctx, 1, 0x80);		/* 0000ffff GP_VERTEX_OUTPUT_COUNT */  in nv50_gr_construct_xfer_unk84xx()
2705 	xf_emit(ctx, 1, 0x03020100);	/* ffffffff GP_RESULT_MAP_0 */  in nv50_gr_construct_xfer_unk84xx()
2710 	xf_emit(ctx, 1, 0);		/* 00000001 PROVOKING_VERTEX_LAST */  in nv50_gr_construct_xfer_unk84xx()
2711 	xf_emit(ctx, 1, 0);		/* ffffffff tesla UNK1A30 */  in nv50_gr_construct_xfer_unk84xx()
2712 	xf_emit(ctx, 1, 0);		/* 111/113 */  in nv50_gr_construct_xfer_unk84xx()
2713 	xf_emit(ctx, 1, 0);		/* 00000001 GP_ENABLE */  in nv50_gr_construct_xfer_unk84xx()
2716 	xf_emit(ctx, 1, 0);		/* 00000001 PROVOKING_VERTEX_LAST */  in nv50_gr_construct_xfer_unk84xx()
2717 	xf_emit(ctx, 1, 0);		/* ffffffff tesla UNK1A30 */  in nv50_gr_construct_xfer_unk84xx()
2718 	xf_emit(ctx, 1, 0);		/* 00000003 tesla UNK13A0 */  in nv50_gr_construct_xfer_unk84xx()
2720 	xf_emit(ctx, 1, 0);		/* 00000001 GP_ENABLE */  in nv50_gr_construct_xfer_unk84xx()
2721 	xf_emit(ctx, 1, 0);		/* ffffffff tesla UNK1A30 */  in nv50_gr_construct_xfer_unk84xx()
2722 	xf_emit(ctx, 1, 0);		/* 111/113 */  in nv50_gr_construct_xfer_unk84xx()
2723 	if (device->chipset == 0x94 || device->chipset == 0x96)  in nv50_gr_construct_xfer_unk84xx()
2724 		xf_emit(ctx, 0x1020, 0);	/* 4 x (0x400 x 0xffffffff, ff, 0, 0, 0, 4 x ffffffff) */  in nv50_gr_construct_xfer_unk84xx()
2725 	else if (device->chipset < 0xa0)  in nv50_gr_construct_xfer_unk84xx()
2726 		xf_emit(ctx, 0xa20, 0);	/* 4 x (0x280 x 0xffffffff, ff, 0, 0, 0, 4 x ffffffff) */  in nv50_gr_construct_xfer_unk84xx()
2728 		xf_emit(ctx, 0x210, 0);	/* ffffffff */  in nv50_gr_construct_xfer_unk84xx()
2730 		xf_emit(ctx, 0x410, 0);	/* ffffffff */  in nv50_gr_construct_xfer_unk84xx()
2731 	xf_emit(ctx, 1, 0);		/* 00000001 GP_ENABLE */  in nv50_gr_construct_xfer_unk84xx()
2734 	xf_emit(ctx, 1, 0);		/* 00000001 PROVOKING_VERTEX_LAST */  in nv50_gr_construct_xfer_unk84xx()
2735 	xf_emit(ctx, 1, 0);		/* ffffffff tesla UNK1A30 */  in nv50_gr_construct_xfer_unk84xx()
2743 	if (device->chipset == 0x50) {  in nv50_gr_construct_xfer_tprop()
2744 		magic1 = 0x3ff;  in nv50_gr_construct_xfer_tprop()
2745 		magic2 = 0x00003e60;  in nv50_gr_construct_xfer_tprop()
2747 		magic1 = 0x7ff;  in nv50_gr_construct_xfer_tprop()
2748 		magic2 = 0x001ffe67;  in nv50_gr_construct_xfer_tprop()
2750 		magic1 = 0x7ff;  in nv50_gr_construct_xfer_tprop()
2751 		magic2 = 0x00087e67;  in nv50_gr_construct_xfer_tprop()
2753 	xf_emit(ctx, 1, 0);		/* 00000007 ALPHA_TEST_FUNC */  in nv50_gr_construct_xfer_tprop()
2754 	xf_emit(ctx, 1, 0);		/* ffffffff ALPHA_TEST_REF */  in nv50_gr_construct_xfer_tprop()
2755 	xf_emit(ctx, 1, 0);		/* 00000001 ALPHA_TEST_ENABLE */  in nv50_gr_construct_xfer_tprop()
2758 	xf_emit(ctx, 1, 0);		/* 7/f MULTISAMPLE_SAMPLES_LOG2 */  in nv50_gr_construct_xfer_tprop()
2759 	xf_emit(ctx, 1, 0);		/* 00000001 tesla UNK1534 */  in nv50_gr_construct_xfer_tprop()
2760 	xf_emit(ctx, 1, 0);		/* 000000ff STENCIL_BACK_MASK */  in nv50_gr_construct_xfer_tprop()
2761 	xf_emit(ctx, 3, 0);		/* 00000007 STENCIL_BACK_OP_FAIL, ZFAIL, ZPASS */  in nv50_gr_construct_xfer_tprop()
2762 	xf_emit(ctx, 4, 0);		/* ffffffff BLEND_COLOR */  in nv50_gr_construct_xfer_tprop()
2763 	xf_emit(ctx, 1, 0);		/* 00000001 UNK19C0 */  in nv50_gr_construct_xfer_tprop()
2764 	xf_emit(ctx, 1, 0);		/* 00000001 UNK0FDC */  in nv50_gr_construct_xfer_tprop()
2765 	xf_emit(ctx, 1, 0xf);		/* 0000000f COLOR_MASK */  in nv50_gr_construct_xfer_tprop()
2766 	xf_emit(ctx, 7, 0);		/* 0000000f COLOR_MASK */  in nv50_gr_construct_xfer_tprop()
2767 	xf_emit(ctx, 1, 0);		/* 00000001 DEPTH_TEST_ENABLE */  in nv50_gr_construct_xfer_tprop()
2768 	xf_emit(ctx, 1, 0);		/* 00000001 DEPTH_WRITE_ENABLE */  in nv50_gr_construct_xfer_tprop()
2769 	xf_emit(ctx, 1, 0);		/* 00000001 LOGIC_OP_ENABLE */  in nv50_gr_construct_xfer_tprop()
2770 	xf_emit(ctx, 1, 0);		/* ff[NV50]/3ff[NV84+] */  in nv50_gr_construct_xfer_tprop()
2772 	xf_emit(ctx, 4, 0xffff);	/* 0000ffff MSAA_MASK */  in nv50_gr_construct_xfer_tprop()
2773 	xf_emit(ctx, 1, 0);		/* 000000ff STENCIL_FRONT_MASK */  in nv50_gr_construct_xfer_tprop()
2774 	xf_emit(ctx, 3, 0);		/* 00000007 STENCIL_FRONT_OP_FAIL, ZFAIL, ZPASS */  in nv50_gr_construct_xfer_tprop()
2775 	xf_emit(ctx, 1, 0);		/* 00000001 STENCIL_FRONT_ENABLE */  in nv50_gr_construct_xfer_tprop()
2776 	xf_emit(ctx, 1, 0);		/* 00000001 STENCIL_BACK_ENABLE */  in nv50_gr_construct_xfer_tprop()
2777 	xf_emit(ctx, 2, 0);		/* 00007fff WINDOW_OFFSET_XY */  in nv50_gr_construct_xfer_tprop()
2779 	xf_emit(ctx, 1, 0);		/* 7 */  in nv50_gr_construct_xfer_tprop()
2780 	xf_emit(ctx, 1, 0);		/* 00000001 SAMPLECNT_ENABLE */  in nv50_gr_construct_xfer_tprop()
2781 	xf_emit(ctx, 1, 0);		/* 0000000f ZETA_FORMAT */  in nv50_gr_construct_xfer_tprop()
2783 	xf_emit(ctx, 1, 0);		/* ffffffff COLOR_KEY */  in nv50_gr_construct_xfer_tprop()
2784 	xf_emit(ctx, 1, 0);		/* 00000001 COLOR_KEY_ENABLE */  in nv50_gr_construct_xfer_tprop()
2785 	xf_emit(ctx, 1, 0);		/* 00000007 COLOR_KEY_FORMAT */  in nv50_gr_construct_xfer_tprop()
2786 	xf_emit(ctx, 2, 0);		/* ffffffff SIFC_BITMAP_COLOR */  in nv50_gr_construct_xfer_tprop()
2788 	xf_emit(ctx, 1, 0);		/* 00000007 ALPHA_TEST_FUNC */  in nv50_gr_construct_xfer_tprop()
2789 	xf_emit(ctx, 1, 0);		/* 00000001 ALPHA_TEST_ENABLE */  in nv50_gr_construct_xfer_tprop()
2792 		xf_emit(ctx, 1, 0);	/* 00000003 */  in nv50_gr_construct_xfer_tprop()
2793 		xf_emit(ctx, 1, 0);	/* 00000003 tesla UNK1298 */  in nv50_gr_construct_xfer_tprop()
2794 	} else if (device->chipset >= 0xa0) {  in nv50_gr_construct_xfer_tprop()
2796 		xf_emit(ctx, 1, 0);	/* 00000003 */  in nv50_gr_construct_xfer_tprop()
2798 		xf_emit(ctx, 1, 0);	/* 00000003 MULTISAMPLE_CTRL */  in nv50_gr_construct_xfer_tprop()
2800 	xf_emit(ctx, 1, 0);		/* 00000001 tesla UNK1534 */  in nv50_gr_construct_xfer_tprop()
2801 	xf_emit(ctx, 8, 0);		/* 00000001 BLEND_ENABLE */  in nv50_gr_construct_xfer_tprop()
2809 		xf_emit(ctx, 1, 0);	/* 00000001 UNK12E4 */  in nv50_gr_construct_xfer_tprop()
2817 		xf_emit(ctx, 1, 0);	/* 00000001 UNK1140 */  in nv50_gr_construct_xfer_tprop()
2820 	xf_emit(ctx, 1, 0);		/* ffff0ff3 */  in nv50_gr_construct_xfer_tprop()
2821 	xf_emit(ctx, 1, 0x11);		/* 3f/7f RT_FORMAT */  in nv50_gr_construct_xfer_tprop()
2822 	xf_emit(ctx, 7, 0);		/* 3f/7f RT_FORMAT */  in nv50_gr_construct_xfer_tprop()
2823 	xf_emit(ctx, 1, 0x0fac6881);	/* 0fffffff RT_CONTROL */  in nv50_gr_construct_xfer_tprop()
2824 	xf_emit(ctx, 1, 0);		/* 00000001 LOGIC_OP_ENABLE */  in nv50_gr_construct_xfer_tprop()
2825 	xf_emit(ctx, 1, 0);		/* ff/3ff */  in nv50_gr_construct_xfer_tprop()
2827 	xf_emit(ctx, 1, 0);		/* 00000003 UNK0F90 */  in nv50_gr_construct_xfer_tprop()
2828 	xf_emit(ctx, 1, 0);		/* 00000001 FRAMEBUFFER_SRGB */  in nv50_gr_construct_xfer_tprop()
2829 	xf_emit(ctx, 1, 0);		/* 7 */  in nv50_gr_construct_xfer_tprop()
2830 	xf_emit(ctx, 1, 0x11);		/* 3f/7f DST_FORMAT */  in nv50_gr_construct_xfer_tprop()
2832 	xf_emit(ctx, 1, 0);		/* 00000007 OPERATION */  in nv50_gr_construct_xfer_tprop()
2833 	xf_emit(ctx, 1, 0xcf);		/* 000000ff SIFC_FORMAT */  in nv50_gr_construct_xfer_tprop()
2834 	xf_emit(ctx, 1, 0xcf);		/* 000000ff DRAW_COLOR_FORMAT */  in nv50_gr_construct_xfer_tprop()
2835 	xf_emit(ctx, 1, 0xcf);		/* 000000ff SRC_FORMAT */  in nv50_gr_construct_xfer_tprop()
2838 	xf_emit(ctx, 1, 0);		/* ffffffff tesla UNK1A3C */  in nv50_gr_construct_xfer_tprop()
2839 	xf_emit(ctx, 1, 0);		/* 7/f[NVA3] MULTISAMPLE_SAMPLES_LOG2 */  in nv50_gr_construct_xfer_tprop()
2840 	xf_emit(ctx, 8, 0);		/* 00000001 BLEND_ENABLE */  in nv50_gr_construct_xfer_tprop()
2848 	xf_emit(ctx, 1, 0);		/* ffff0ff3 */  in nv50_gr_construct_xfer_tprop()
2850 	xf_emit(ctx, 1, 0x11);		/* 3f/7f RT_FORMAT */  in nv50_gr_construct_xfer_tprop()
2851 	xf_emit(ctx, 7, 0);		/* 3f/7f RT_FORMAT */  in nv50_gr_construct_xfer_tprop()
2852 	xf_emit(ctx, 1, 0x0fac6881);	/* 0fffffff RT_CONTROL */  in nv50_gr_construct_xfer_tprop()
2853 	xf_emit(ctx, 1, 0xf);		/* 0000000f COLOR_MASK */  in nv50_gr_construct_xfer_tprop()
2854 	xf_emit(ctx, 7, 0);		/* 0000000f COLOR_MASK */  in nv50_gr_construct_xfer_tprop()
2856 	xf_emit(ctx, 1, 0);		/* 00000001 DEPTH_BOUNDS_EN */  in nv50_gr_construct_xfer_tprop()
2857 	xf_emit(ctx, 1, 0);		/* 00000001 DEPTH_TEST_ENABLE */  in nv50_gr_construct_xfer_tprop()
2858 	xf_emit(ctx, 1, 0x11);		/* 3f/7f DST_FORMAT */  in nv50_gr_construct_xfer_tprop()
2862 	if (device->chipset == 0x50)  in nv50_gr_construct_xfer_tprop()
2863 		xf_emit(ctx, 1, 0);	/* ff */  in nv50_gr_construct_xfer_tprop()
2865 		xf_emit(ctx, 3, 0);	/* 1, 7, 3ff */  in nv50_gr_construct_xfer_tprop()
2867 	xf_emit(ctx, 1, 0);		/* 00000003 UNK0F90 */  in nv50_gr_construct_xfer_tprop()
2868 	xf_emit(ctx, 1, 0);		/* 00000001 STENCIL_FRONT_ENABLE */  in nv50_gr_construct_xfer_tprop()
2869 	xf_emit(ctx, 1, 0);		/* 00000007 */  in nv50_gr_construct_xfer_tprop()
2870 	xf_emit(ctx, 1, 0);		/* 00000001 SAMPLECNT_ENABLE */  in nv50_gr_construct_xfer_tprop()
2871 	xf_emit(ctx, 1, 0);		/* 0000000f ZETA_FORMAT */  in nv50_gr_construct_xfer_tprop()
2873 	xf_emit(ctx, 1, 0);		/* ffffffff tesla UNK1A3C */  in nv50_gr_construct_xfer_tprop()
2874 	xf_emit(ctx, 1, 0);		/* 7/f MULTISAMPLE_SAMPLES_LOG2 */  in nv50_gr_construct_xfer_tprop()
2875 	xf_emit(ctx, 1, 0);		/* 00000001 tesla UNK1534 */  in nv50_gr_construct_xfer_tprop()
2876 	xf_emit(ctx, 1, 0);		/* ffff0ff3 */  in nv50_gr_construct_xfer_tprop()
2877 	xf_emit(ctx, 1, 0x11);		/* 3f/7f RT_FORMAT */  in nv50_gr_construct_xfer_tprop()
2878 	xf_emit(ctx, 7, 0);		/* 3f/7f RT_FORMAT */  in nv50_gr_construct_xfer_tprop()
2879 	xf_emit(ctx, 1, 0x0fac6881);	/* 0fffffff RT_CONTROL */  in nv50_gr_construct_xfer_tprop()
2880 	xf_emit(ctx, 1, 0);		/* 00000001 DEPTH_BOUNDS_EN */  in nv50_gr_construct_xfer_tprop()
2881 	xf_emit(ctx, 1, 0);		/* 00000001 DEPTH_TEST_ENABLE */  in nv50_gr_construct_xfer_tprop()
2882 	xf_emit(ctx, 1, 0);		/* 00000001 DEPTH_WRITE_ENABLE */  in nv50_gr_construct_xfer_tprop()
2883 	xf_emit(ctx, 1, 0x11);		/* 3f/7f DST_FORMAT */  in nv50_gr_construct_xfer_tprop()
2885 	xf_emit(ctx, 1, 0);		/* 000fffff BLIT_DU_DX_FRACT */  in nv50_gr_construct_xfer_tprop()
2887 	xf_emit(ctx, 1, 0);		/* 000fffff BLIT_DV_DY_FRACT */  in nv50_gr_construct_xfer_tprop()
2889 	xf_emit(ctx, 1, 0);		/* ff/3ff */  in nv50_gr_construct_xfer_tprop()
2891 	xf_emit(ctx, 1, 0);		/* 00000001 STENCIL_FRONT_ENABLE */  in nv50_gr_construct_xfer_tprop()
2893 	xf_emit(ctx, 1, 0);		/* 0000000f ZETA_FORMAT */  in nv50_gr_construct_xfer_tprop()
2895 	xf_emit(ctx, 1, 0);		/* 00000007 */  in nv50_gr_construct_xfer_tprop()
2896 	xf_emit(ctx, 1, 0);		/* ffffffff tesla UNK1A3C */  in nv50_gr_construct_xfer_tprop()
2899 	xf_emit(ctx, 8, 0);		/* 0000ffff DMA_COLOR */  in nv50_gr_construct_xfer_tprop()
2900 	xf_emit(ctx, 1, 0);		/* 0000ffff DMA_GLOBAL */  in nv50_gr_construct_xfer_tprop()
2901 	xf_emit(ctx, 1, 0);		/* 0000ffff DMA_LOCAL */  in nv50_gr_construct_xfer_tprop()
2902 	xf_emit(ctx, 1, 0);		/* 0000ffff DMA_STACK */  in nv50_gr_construct_xfer_tprop()
2903 	xf_emit(ctx, 1, 0);		/* ff/3ff */  in nv50_gr_construct_xfer_tprop()
2904 	xf_emit(ctx, 1, 0);		/* 0000ffff DMA_DST */  in nv50_gr_construct_xfer_tprop()
2905 	xf_emit(ctx, 1, 0);		/* 7 */  in nv50_gr_construct_xfer_tprop()
2906 	xf_emit(ctx, 1, 0);		/* 7/f MULTISAMPLE_SAMPLES_LOG2 */  in nv50_gr_construct_xfer_tprop()
2907 	xf_emit(ctx, 1, 0);		/* ffff0ff3 */  in nv50_gr_construct_xfer_tprop()
2908 	xf_emit(ctx, 8, 0);		/* 000000ff RT_ADDRESS_HIGH */  in nv50_gr_construct_xfer_tprop()
2909 	xf_emit(ctx, 8, 0);		/* ffffffff RT_LAYER_STRIDE */  in nv50_gr_construct_xfer_tprop()
2910 	xf_emit(ctx, 8, 0);		/* ffffffff RT_ADDRESS_LOW */  in nv50_gr_construct_xfer_tprop()
2912 	xf_emit(ctx, 1, 0x11);		/* 3f/7f RT_FORMAT */  in nv50_gr_construct_xfer_tprop()
2913 	xf_emit(ctx, 7, 0);		/* 3f/7f RT_FORMAT */  in nv50_gr_construct_xfer_tprop()
2914 	xf_emit(ctx, 1, 0x0fac6881);	/* 0fffffff RT_CONTROL */  in nv50_gr_construct_xfer_tprop()
2915 	xf_emit(ctx, 8, 0x400);		/* 0fffffff RT_HORIZ */  in nv50_gr_construct_xfer_tprop()
2916 	xf_emit(ctx, 8, 0x300);		/* 0000ffff RT_VERT */  in nv50_gr_construct_xfer_tprop()
2918 	xf_emit(ctx, 1, 0xf);		/* 0000000f COLOR_MASK */  in nv50_gr_construct_xfer_tprop()
2919 	xf_emit(ctx, 7, 0);		/* 0000000f COLOR_MASK */  in nv50_gr_construct_xfer_tprop()
2920 	xf_emit(ctx, 1, 0x20);		/* 00000fff DST_TILE_MODE */  in nv50_gr_construct_xfer_tprop()
2921 	xf_emit(ctx, 1, 0x11);		/* 3f/7f DST_FORMAT */  in nv50_gr_construct_xfer_tprop()
2922 	xf_emit(ctx, 1, 0x100);		/* 0001ffff DST_HEIGHT */  in nv50_gr_construct_xfer_tprop()
2923 	xf_emit(ctx, 1, 0);		/* 000007ff DST_LAYER */  in nv50_gr_construct_xfer_tprop()
2925 	xf_emit(ctx, 1, 0);		/* ffffffff DST_ADDRESS_LOW */  in nv50_gr_construct_xfer_tprop()
2926 	xf_emit(ctx, 1, 0);		/* 000000ff DST_ADDRESS_HIGH */  in nv50_gr_construct_xfer_tprop()
2927 	xf_emit(ctx, 1, 0x40);		/* 0007ffff DST_PITCH */  in nv50_gr_construct_xfer_tprop()
2928 	xf_emit(ctx, 1, 0x100);		/* 0001ffff DST_WIDTH */  in nv50_gr_construct_xfer_tprop()
2929 	xf_emit(ctx, 1, 0);		/* 0000ffff */  in nv50_gr_construct_xfer_tprop()
2931 	xf_emit(ctx, 1, 0);		/* ff/3ff */  in nv50_gr_construct_xfer_tprop()
2932 	xf_emit(ctx, 1, 0);		/* 0001ffff GP_BUILTIN_RESULT_EN */  in nv50_gr_construct_xfer_tprop()
2933 	xf_emit(ctx, 1, 0);		/* 00000003 UNK0F90 */  in nv50_gr_construct_xfer_tprop()
2934 	xf_emit(ctx, 1, 0);		/* 00000007 */  in nv50_gr_construct_xfer_tprop()
2938 	xf_emit(ctx, 1, 0);		/* 7/f MULTISAMPLE_SAMPLES_LOG2 */  in nv50_gr_construct_xfer_tprop()
2939 	xf_emit(ctx, 1, 0);		/* 00000001 tesla UNK1534 */  in nv50_gr_construct_xfer_tprop()
2940 	xf_emit(ctx, 1, 0);		/* ffff0ff3 */  in nv50_gr_construct_xfer_tprop()
2942 	xf_emit(ctx, 1, 0x0fac6881);	/* 0fffffff RT_CONTROL */  in nv50_gr_construct_xfer_tprop()
2943 	xf_emit(ctx, 1, 0);		/* 0000ffff DMA_ZETA */  in nv50_gr_construct_xfer_tprop()
2944 	xf_emit(ctx, 1, 0);		/* 00000001 DEPTH_BOUNDS_EN */  in nv50_gr_construct_xfer_tprop()
2945 	xf_emit(ctx, 1, 0);		/* 00000001 DEPTH_TEST_ENABLE */  in nv50_gr_construct_xfer_tprop()
2946 	xf_emit(ctx, 1, 0);		/* 00000001 DEPTH_WRITE_ENABLE */  in nv50_gr_construct_xfer_tprop()
2947 	xf_emit(ctx, 2, 0);		/* ffff, ff/3ff */  in nv50_gr_construct_xfer_tprop()
2948 	xf_emit(ctx, 1, 0);		/* 0001ffff GP_BUILTIN_RESULT_EN */  in nv50_gr_construct_xfer_tprop()
2949 	xf_emit(ctx, 1, 0);		/* 00000001 STENCIL_FRONT_ENABLE */  in nv50_gr_construct_xfer_tprop()
2950 	xf_emit(ctx, 1, 0);		/* 000000ff STENCIL_FRONT_MASK */  in nv50_gr_construct_xfer_tprop()
2952 	xf_emit(ctx, 1, 0);		/* 00000007 */  in nv50_gr_construct_xfer_tprop()
2953 	xf_emit(ctx, 1, 0);		/* ffffffff ZETA_LAYER_STRIDE */  in nv50_gr_construct_xfer_tprop()
2954 	xf_emit(ctx, 1, 0);		/* 000000ff ZETA_ADDRESS_HIGH */  in nv50_gr_construct_xfer_tprop()
2955 	xf_emit(ctx, 1, 0);		/* ffffffff ZETA_ADDRESS_LOW */  in nv50_gr_construct_xfer_tprop()
2957 	xf_emit(ctx, 1, 0);		/* 0000000f ZETA_FORMAT */  in nv50_gr_construct_xfer_tprop()
2959 	xf_emit(ctx, 1, 0x400);		/* 0fffffff ZETA_HORIZ */  in nv50_gr_construct_xfer_tprop()
2960 	xf_emit(ctx, 1, 0x300);		/* 0000ffff ZETA_VERT */  in nv50_gr_construct_xfer_tprop()
2961 	xf_emit(ctx, 1, 0x1001);	/* 00001fff ZETA_ARRAY_MODE */  in nv50_gr_construct_xfer_tprop()
2962 	xf_emit(ctx, 1, 0);		/* ffffffff tesla UNK1A3C */  in nv50_gr_construct_xfer_tprop()
2963 	xf_emit(ctx, 1, 0);		/* 7/f MULTISAMPLE_SAMPLES_LOG2 */  in nv50_gr_construct_xfer_tprop()
2965 		xf_emit(ctx, 1, 0);	/* 00000001 */  in nv50_gr_construct_xfer_tprop()
2966 	xf_emit(ctx, 1, 0);		/* ffff0ff3 */  in nv50_gr_construct_xfer_tprop()
2967 	xf_emit(ctx, 1, 0x11);		/* 3f/7f RT_FORMAT */  in nv50_gr_construct_xfer_tprop()
2968 	xf_emit(ctx, 7, 0);		/* 3f/7f RT_FORMAT */  in nv50_gr_construct_xfer_tprop()
2969 	xf_emit(ctx, 1, 0x0fac6881);	/* 0fffffff RT_CONTROL */  in nv50_gr_construct_xfer_tprop()
2970 	xf_emit(ctx, 1, 0xf);		/* 0000000f COLOR_MASK */  in nv50_gr_construct_xfer_tprop()
2971 	xf_emit(ctx, 7, 0);		/* 0000000f COLOR_MASK */  in nv50_gr_construct_xfer_tprop()
2972 	xf_emit(ctx, 1, 0);		/* ff/3ff */  in nv50_gr_construct_xfer_tprop()
2973 	xf_emit(ctx, 8, 0);		/* 00000001 BLEND_ENABLE */  in nv50_gr_construct_xfer_tprop()
2974 	xf_emit(ctx, 1, 0);		/* 00000003 UNK0F90 */  in nv50_gr_construct_xfer_tprop()
2975 	xf_emit(ctx, 1, 0);		/* 00000001 FRAMEBUFFER_SRGB */  in nv50_gr_construct_xfer_tprop()
2976 	xf_emit(ctx, 1, 0);		/* 7 */  in nv50_gr_construct_xfer_tprop()
2977 	xf_emit(ctx, 1, 0);		/* 00000001 LOGIC_OP_ENABLE */  in nv50_gr_construct_xfer_tprop()
2979 		xf_emit(ctx, 1, 0);	/* 00000001 UNK1140 */  in nv50_gr_construct_xfer_tprop()
2982 	xf_emit(ctx, 1, 0);		/* 7/f MULTISAMPLE_SAMPLES_LOG2 */  in nv50_gr_construct_xfer_tprop()
2983 	xf_emit(ctx, 1, 0);		/* 00000001 UNK1534 */  in nv50_gr_construct_xfer_tprop()
2984 	xf_emit(ctx, 1, 0);		/* ffff0ff3 */  in nv50_gr_construct_xfer_tprop()
2985 	if (device->chipset >= 0xa0)  in nv50_gr_construct_xfer_tprop()
2986 		xf_emit(ctx, 1, 0x0fac6881);	/* fffffff */  in nv50_gr_construct_xfer_tprop()
2988 	xf_emit(ctx, 1, 0);		/* 00000001 DEPTH_BOUNDS_EN */  in nv50_gr_construct_xfer_tprop()
2989 	xf_emit(ctx, 1, 0);		/* 00000001 DEPTH_TEST_ENABLE */  in nv50_gr_construct_xfer_tprop()
2990 	xf_emit(ctx, 1, 0);		/* 00000001 DEPTH_WRITE_ENABLE */  in nv50_gr_construct_xfer_tprop()
2991 	xf_emit(ctx, 1, 0x11);		/* 3f/7f DST_FORMAT */  in nv50_gr_construct_xfer_tprop()
2992 	xf_emit(ctx, 1, 0);		/* 00000001 tesla UNK0FB0 */  in nv50_gr_construct_xfer_tprop()
2993 	xf_emit(ctx, 1, 0);		/* ff/3ff */  in nv50_gr_construct_xfer_tprop()
2995 	xf_emit(ctx, 1, 0);		/* 00000001 STENCIL_FRONT_ENABLE */  in nv50_gr_construct_xfer_tprop()
2998 	xf_emit(ctx, 1, 0);		/* 00000007 */  in nv50_gr_construct_xfer_tprop()
2999 	xf_emit(ctx, 1, 0);		/* 00000001 SAMPLECNT_ENABLE */  in nv50_gr_construct_xfer_tprop()
3000 	xf_emit(ctx, 1, 0);		/* 0000000f ZETA_FORMAT */  in nv50_gr_construct_xfer_tprop()
3004 		xf_emit(ctx, 1, 0);	/* 0000000f tesla UNK15C8 */  in nv50_gr_construct_xfer_tprop()
3006 	xf_emit(ctx, 1, 0);		/* ffffffff tesla UNK1A3C */  in nv50_gr_construct_xfer_tprop()
3007 	if (device->chipset >= 0xa0) {  in nv50_gr_construct_xfer_tprop()
3008 		xf_emit(ctx, 3, 0);		/* 7/f, 1, ffff0ff3 */  in nv50_gr_construct_xfer_tprop()
3009 		xf_emit(ctx, 1, 0xfac6881);	/* fffffff */  in nv50_gr_construct_xfer_tprop()
3010 		xf_emit(ctx, 4, 0);		/* 1, 1, 1, 3ff */  in nv50_gr_construct_xfer_tprop()
3012 		xf_emit(ctx, 1, 0);		/* 1 */  in nv50_gr_construct_xfer_tprop()
3014 		xf_emit(ctx, 2, 0);		/* 7, f */  in nv50_gr_construct_xfer_tprop()
3016 		xf_emit(ctx, 1, 0);		/* 7/f */  in nv50_gr_construct_xfer_tprop()
3018 			xf_emit(ctx, 0x9, 0);	/* 1 */  in nv50_gr_construct_xfer_tprop()
3020 			xf_emit(ctx, 0x8, 0);	/* 1 */  in nv50_gr_construct_xfer_tprop()
3021 		xf_emit(ctx, 1, 0);		/* ffff0ff3 */  in nv50_gr_construct_xfer_tprop()
3023 		xf_emit(ctx, 1, 0x11);		/* 7f */  in nv50_gr_construct_xfer_tprop()
3024 		xf_emit(ctx, 7, 0);		/* 7f */  in nv50_gr_construct_xfer_tprop()
3025 		xf_emit(ctx, 1, 0xfac6881);	/* fffffff */  in nv50_gr_construct_xfer_tprop()
3026 		xf_emit(ctx, 1, 0xf);		/* f */  in nv50_gr_construct_xfer_tprop()
3027 		xf_emit(ctx, 7, 0);		/* f */  in nv50_gr_construct_xfer_tprop()
3028 		xf_emit(ctx, 1, 0x11);		/* 7f */  in nv50_gr_construct_xfer_tprop()
3030 		xf_emit(ctx, 5, 0);		/* 1, 7, 3ff, 3, 7 */  in nv50_gr_construct_xfer_tprop()
3032 			xf_emit(ctx, 1, 0);	/* 00000001 UNK1140 */  in nv50_gr_construct_xfer_tprop()
3042 	xf_emit(ctx, 2, 0);		/* 1 LINKED_TSC. yes, 2. */  in nv50_gr_construct_xfer_tex()
3043 	if (device->chipset != 0x50)  in nv50_gr_construct_xfer_tex()
3044 		xf_emit(ctx, 1, 0);	/* 3 */  in nv50_gr_construct_xfer_tex()
3046 	xf_emit(ctx, 1, 0);		/* fffff BLIT_DU_DX_FRACT */  in nv50_gr_construct_xfer_tex()
3048 	xf_emit(ctx, 1, 0);		/* fffff BLIT_DV_DY_FRACT */  in nv50_gr_construct_xfer_tex()
3049 	if (device->chipset == 0x50)  in nv50_gr_construct_xfer_tex()
3050 		xf_emit(ctx, 1, 0);	/* 3 BLIT_CONTROL */  in nv50_gr_construct_xfer_tex()
3052 		xf_emit(ctx, 2, 0);	/* 3ff, 1 */  in nv50_gr_construct_xfer_tex()
3053 	xf_emit(ctx, 1, 0x2a712488);	/* ffffffff SRC_TIC_0 */  in nv50_gr_construct_xfer_tex()
3054 	xf_emit(ctx, 1, 0);		/* ffffffff SRC_TIC_1 */  in nv50_gr_construct_xfer_tex()
3055 	xf_emit(ctx, 1, 0x4085c000);	/* ffffffff SRC_TIC_2 */  in nv50_gr_construct_xfer_tex()
3056 	xf_emit(ctx, 1, 0x40);		/* ffffffff SRC_TIC_3 */  in nv50_gr_construct_xfer_tex()
3057 	xf_emit(ctx, 1, 0x100);		/* ffffffff SRC_TIC_4 */  in nv50_gr_construct_xfer_tex()
3058 	xf_emit(ctx, 1, 0x10100);	/* ffffffff SRC_TIC_5 */  in nv50_gr_construct_xfer_tex()
3059 	xf_emit(ctx, 1, 0x02800000);	/* ffffffff SRC_TIC_6 */  in nv50_gr_construct_xfer_tex()
3060 	xf_emit(ctx, 1, 0);		/* ffffffff SRC_TIC_7 */  in nv50_gr_construct_xfer_tex()
3061 	if (device->chipset == 0x50) {  in nv50_gr_construct_xfer_tex()
3062 		xf_emit(ctx, 1, 0);	/* 00000001 turing UNK358 */  in nv50_gr_construct_xfer_tex()
3063 		xf_emit(ctx, 1, 0);	/* ffffffff tesla UNK1A34? */  in nv50_gr_construct_xfer_tex()
3064 		xf_emit(ctx, 1, 0);	/* 00000003 turing UNK37C tesla UNK1690 */  in nv50_gr_construct_xfer_tex()
3065 		xf_emit(ctx, 1, 0);	/* 00000003 BLIT_CONTROL */  in nv50_gr_construct_xfer_tex()
3066 		xf_emit(ctx, 1, 0);	/* 00000001 turing UNK32C tesla UNK0F94 */  in nv50_gr_construct_xfer_tex()
3068 		xf_emit(ctx, 1, 0);	/* ffffffff tesla UNK1A34? */  in nv50_gr_construct_xfer_tex()
3069 		xf_emit(ctx, 1, 0);	/* 00000003 */  in nv50_gr_construct_xfer_tex()
3070 		xf_emit(ctx, 1, 0);	/* 000003ff */  in nv50_gr_construct_xfer_tex()
3071 		xf_emit(ctx, 1, 0);	/* 00000003 */  in nv50_gr_construct_xfer_tex()
3072 		xf_emit(ctx, 1, 0);	/* 000003ff */  in nv50_gr_construct_xfer_tex()
3073 		xf_emit(ctx, 1, 0);	/* 00000003 tesla UNK1664 / turing UNK03E8 */  in nv50_gr_construct_xfer_tex()
3074 		xf_emit(ctx, 1, 0);	/* 00000003 */  in nv50_gr_construct_xfer_tex()
3075 		xf_emit(ctx, 1, 0);	/* 000003ff */  in nv50_gr_construct_xfer_tex()
3077 		xf_emit(ctx, 0x6, 0);  in nv50_gr_construct_xfer_tex()
3079 	xf_emit(ctx, 1, 0);		/* ffffffff tesla UNK1A34 */  in nv50_gr_construct_xfer_tex()
3080 	xf_emit(ctx, 1, 0);		/* 0000ffff DMA_TEXTURE */  in nv50_gr_construct_xfer_tex()
3081 	xf_emit(ctx, 1, 0);		/* 0000ffff DMA_SRC */  in nv50_gr_construct_xfer_tex()
3088 	xf_emit(ctx, 1, 0);		/* 00000001 UNK1534 */  in nv50_gr_construct_xfer_unk8cxx()
3089 	xf_emit(ctx, 1, 0);		/* 7/f MULTISAMPLE_SAMPLES_LOG2 */  in nv50_gr_construct_xfer_unk8cxx()
3090 	xf_emit(ctx, 2, 0);		/* 7, ffff0ff3 */  in nv50_gr_construct_xfer_unk8cxx()
3091 	xf_emit(ctx, 1, 0);		/* 00000001 DEPTH_TEST_ENABLE */  in nv50_gr_construct_xfer_unk8cxx()
3092 	xf_emit(ctx, 1, 0);		/* 00000001 DEPTH_WRITE */  in nv50_gr_construct_xfer_unk8cxx()
3093 	xf_emit(ctx, 1, 0x04e3bfdf);	/* ffffffff UNK0D64 */  in nv50_gr_construct_xfer_unk8cxx()
3094 	xf_emit(ctx, 1, 0x04e3bfdf);	/* ffffffff UNK0DF4 */  in nv50_gr_construct_xfer_unk8cxx()
3096 	xf_emit(ctx, 1, 0);		/* 00000001 LINE_STIPPLE_ENABLE */  in nv50_gr_construct_xfer_unk8cxx()
3097 	xf_emit(ctx, 1, 0x00ffff00);	/* 00ffffff LINE_STIPPLE_PATTERN */  in nv50_gr_construct_xfer_unk8cxx()
3101 	xf_emit(ctx, 1, 0);		/* 00000003 tesla UNK1668 */  in nv50_gr_construct_xfer_unk8cxx()
3102 	xf_emit(ctx, 1, 0);		/* 00000001 LINE_STIPPLE_ENABLE */  in nv50_gr_construct_xfer_unk8cxx()
3103 	xf_emit(ctx, 1, 0x00ffff00);	/* 00ffffff LINE_STIPPLE_PATTERN */  in nv50_gr_construct_xfer_unk8cxx()
3104 	xf_emit(ctx, 1, 0);		/* 00000001 POLYGON_SMOOTH_ENABLE */  in nv50_gr_construct_xfer_unk8cxx()
3105 	xf_emit(ctx, 1, 0);		/* 00000001 UNK1534 */  in nv50_gr_construct_xfer_unk8cxx()
3106 	xf_emit(ctx, 1, 0);		/* 7/f MULTISAMPLE_SAMPLES_LOG2 */  in nv50_gr_construct_xfer_unk8cxx()
3107 	xf_emit(ctx, 1, 0);		/* 00000001 tesla UNK1658 */  in nv50_gr_construct_xfer_unk8cxx()
3108 	xf_emit(ctx, 1, 0);		/* 00000001 LINE_SMOOTH_ENABLE */  in nv50_gr_construct_xfer_unk8cxx()
3109 	xf_emit(ctx, 1, 0);		/* ffff0ff3 */  in nv50_gr_construct_xfer_unk8cxx()
3110 	xf_emit(ctx, 1, 0);		/* 00000001 DEPTH_TEST_ENABLE */  in nv50_gr_construct_xfer_unk8cxx()
3111 	xf_emit(ctx, 1, 0);		/* 00000001 DEPTH_WRITE */  in nv50_gr_construct_xfer_unk8cxx()
3113 	xf_emit(ctx, 1, 0);		/* 00000001 POINT_SPRITE_ENABLE */  in nv50_gr_construct_xfer_unk8cxx()
3115 	xf_emit(ctx, 1, 0x30201000);	/* ffffffff tesla UNK1670 */  in nv50_gr_construct_xfer_unk8cxx()
3116 	xf_emit(ctx, 1, 0x70605040);	/* ffffffff tesla UNK1670 */  in nv50_gr_construct_xfer_unk8cxx()
3117 	xf_emit(ctx, 1, 0xb8a89888);	/* ffffffff tesla UNK1670 */  in nv50_gr_construct_xfer_unk8cxx()
3118 	xf_emit(ctx, 1, 0xf8e8d8c8);	/* ffffffff tesla UNK1670 */  in nv50_gr_construct_xfer_unk8cxx()
3119 	xf_emit(ctx, 1, 0);		/* 00000001 VERTEX_TWO_SIDE_ENABLE */  in nv50_gr_construct_xfer_unk8cxx()
3120 	xf_emit(ctx, 1, 0x1a);		/* 0000001f POLYGON_MODE */  in nv50_gr_construct_xfer_unk8cxx()
3127 	if (device->chipset < 0xa0) {  in nv50_gr_construct_xfer_tp()
3146 		case 0x98:  in nv50_gr_construct_xfer_mpc()
3147 		case 0xaa:  in nv50_gr_construct_xfer_mpc()
3150 		case 0x50:  in nv50_gr_construct_xfer_mpc()
3151 		case 0x84:  in nv50_gr_construct_xfer_mpc()
3152 		case 0x86:  in nv50_gr_construct_xfer_mpc()
3153 		case 0x92:  in nv50_gr_construct_xfer_mpc()
3154 		case 0x94:  in nv50_gr_construct_xfer_mpc()
3155 		case 0x96:  in nv50_gr_construct_xfer_mpc()
3156 		case 0xa8:  in nv50_gr_construct_xfer_mpc()
3157 		case 0xac:  in nv50_gr_construct_xfer_mpc()
3160 		case 0xa0:  in nv50_gr_construct_xfer_mpc()
3161 		case 0xa3:  in nv50_gr_construct_xfer_mpc()
3162 		case 0xa5:  in nv50_gr_construct_xfer_mpc()
3163 		case 0xaf:  in nv50_gr_construct_xfer_mpc()
3167 	for (i = 0; i < mpcnt; i++) {  in nv50_gr_construct_xfer_mpc()
3168 		xf_emit(ctx, 1, 0);		/* ff */  in nv50_gr_construct_xfer_mpc()
3169 		xf_emit(ctx, 1, 0x80);		/* ffffffff tesla UNK1404 */  in nv50_gr_construct_xfer_mpc()
3170 		xf_emit(ctx, 1, 0x80007004);	/* ffffffff tesla UNK12B0 */  in nv50_gr_construct_xfer_mpc()
3171 		xf_emit(ctx, 1, 0x04000400);	/* ffffffff */  in nv50_gr_construct_xfer_mpc()
3172 		if (device->chipset >= 0xa0)  in nv50_gr_construct_xfer_mpc()
3173 			xf_emit(ctx, 1, 0xc0);	/* 00007fff tesla UNK152C */  in nv50_gr_construct_xfer_mpc()
3174 		xf_emit(ctx, 1, 0x1000);	/* 0000ffff tesla UNK0D60 */  in nv50_gr_construct_xfer_mpc()
3175 		xf_emit(ctx, 1, 0);		/* ff/3ff */  in nv50_gr_construct_xfer_mpc()
3176 		xf_emit(ctx, 1, 0);		/* ffffffff tesla UNK1A30 */  in nv50_gr_construct_xfer_mpc()
3177 …if (device->chipset == 0x86 || device->chipset == 0x98 || device->chipset == 0xa8 || IS_NVAAF(devi…  in nv50_gr_construct_xfer_mpc()
3178 			xf_emit(ctx, 1, 0xe00);		/* 7fff */  in nv50_gr_construct_xfer_mpc()
3179 			xf_emit(ctx, 1, 0x1e00);	/* 7fff */  in nv50_gr_construct_xfer_mpc()
3182 		xf_emit(ctx, 1, 0);		/* 00000001 LINKED_TSC */  in nv50_gr_construct_xfer_mpc()
3183 		xf_emit(ctx, 1, 0);		/* 00000001 GP_ENABLE */  in nv50_gr_construct_xfer_mpc()
3184 		if (device->chipset == 0x50)  in nv50_gr_construct_xfer_mpc()
3185 			xf_emit(ctx, 2, 0x1000);	/* 7fff tesla UNK141C */  in nv50_gr_construct_xfer_mpc()
3187 		xf_emit(ctx, 1, 0);		/* 00000001 GP_ENABLE */  in nv50_gr_construct_xfer_mpc()
3191 			xf_emit(ctx, 0xb, 0);	/* RO */  in nv50_gr_construct_xfer_mpc()
3192 		else if (device->chipset >= 0xa0)  in nv50_gr_construct_xfer_mpc()
3193 			xf_emit(ctx, 0xc, 0);	/* RO */  in nv50_gr_construct_xfer_mpc()
3195 			xf_emit(ctx, 0xa, 0);	/* RO */  in nv50_gr_construct_xfer_mpc()
3197 	xf_emit(ctx, 1, 0x08100c12);		/* 1fffffff FP_INTERPOLANT_CTRL */  in nv50_gr_construct_xfer_mpc()
3198 	xf_emit(ctx, 1, 0);			/* ff/3ff */  in nv50_gr_construct_xfer_mpc()
3199 	if (device->chipset >= 0xa0) {  in nv50_gr_construct_xfer_mpc()
3200 		xf_emit(ctx, 1, 0x1fe21);	/* 0003ffff tesla UNK0FAC */  in nv50_gr_construct_xfer_mpc()
3202 	xf_emit(ctx, 3, 0);			/* 7fff, 0, 0 */  in nv50_gr_construct_xfer_mpc()
3203 	xf_emit(ctx, 1, 0);			/* 00000001 tesla UNK1534 */  in nv50_gr_construct_xfer_mpc()
3204 	xf_emit(ctx, 1, 0);			/* 7/f MULTISAMPLE_SAMPLES_LOG2 */  in nv50_gr_construct_xfer_mpc()
3205 	xf_emit(ctx, 4, 0xffff);		/* 0000ffff MSAA_MASK */  in nv50_gr_construct_xfer_mpc()
3207 	xf_emit(ctx, 1, 0x10001);		/* 00ffffff BLOCK_ALLOC */  in nv50_gr_construct_xfer_mpc()
3208 	xf_emit(ctx, 1, 0x10001);		/* ffffffff BLOCKDIM_XY */  in nv50_gr_construct_xfer_mpc()
3210 	xf_emit(ctx, 1, 0);			/* ffffffff SHARED_SIZE */  in nv50_gr_construct_xfer_mpc()
3211 	xf_emit(ctx, 1, 0x1fe21);		/* 1ffff/3ffff[NVA0+] tesla UNk0FAC */  in nv50_gr_construct_xfer_mpc()
3212 	xf_emit(ctx, 1, 0);			/* ffffffff tesla UNK1A34 */  in nv50_gr_construct_xfer_mpc()
3215 	xf_emit(ctx, 1, 0);			/* ff/3ff */  in nv50_gr_construct_xfer_mpc()
3216 	xf_emit(ctx, 1, 0);			/* 1 LINKED_TSC */  in nv50_gr_construct_xfer_mpc()
3217 	xf_emit(ctx, 1, 0);			/* ff FP_ADDRESS_HIGH */  in nv50_gr_construct_xfer_mpc()
3218 	xf_emit(ctx, 1, 0);			/* ffffffff FP_ADDRESS_LOW */  in nv50_gr_construct_xfer_mpc()
3219 	xf_emit(ctx, 1, 0x08100c12);		/* 1fffffff FP_INTERPOLANT_CTRL */  in nv50_gr_construct_xfer_mpc()
3221 	xf_emit(ctx, 1, 0);			/* 000000ff FRAG_COLOR_CLAMP_EN */  in nv50_gr_construct_xfer_mpc()
3223 	xf_emit(ctx, 1, 0x11);			/* 0000007f RT_FORMAT */  in nv50_gr_construct_xfer_mpc()
3224 	xf_emit(ctx, 7, 0);			/* 0000007f RT_FORMAT */  in nv50_gr_construct_xfer_mpc()
3225 	xf_emit(ctx, 1, 0);			/* 00000007 */  in nv50_gr_construct_xfer_mpc()
3226 	xf_emit(ctx, 1, 0xfac6881);		/* 0fffffff RT_CONTROL */  in nv50_gr_construct_xfer_mpc()
3227 	xf_emit(ctx, 1, 0);			/* 00000003 MULTISAMPLE_CTRL */  in nv50_gr_construct_xfer_mpc()
3230 	xf_emit(ctx, 1, 0);			/* 00000001 ALPHA_TEST_ENABLE */  in nv50_gr_construct_xfer_mpc()
3231 	xf_emit(ctx, 1, 0);			/* 00000007 ALPHA_TEST_FUNC */  in nv50_gr_construct_xfer_mpc()
3232 	xf_emit(ctx, 1, 0);			/* 00000001 FRAMEBUFFER_SRGB */  in nv50_gr_construct_xfer_mpc()
3234 	xf_emit(ctx, 8, 0);			/* 00000001 BLEND_ENABLE */  in nv50_gr_construct_xfer_mpc()
3235 	xf_emit(ctx, 1, 0);			/* 00000001 LOGIC_OP_ENABLE */  in nv50_gr_construct_xfer_mpc()
3244 		xf_emit(ctx, 1, 0);		/* 00000001 UNK12E4 */  in nv50_gr_construct_xfer_mpc()
3252 		xf_emit(ctx, 1, 0);		/* 00000003 tesla UNK1928 */  in nv50_gr_construct_xfer_mpc()
3253 		xf_emit(ctx, 1, 0);		/* 00000001 UNK1140 */  in nv50_gr_construct_xfer_mpc()
3255 	xf_emit(ctx, 1, 0);			/* 00000003 tesla UNK0F90 */  in nv50_gr_construct_xfer_mpc()
3258 	if (device->chipset == 0x50)  in nv50_gr_construct_xfer_mpc()
3259 		xf_emit(ctx, 0x3a0, 0);  in nv50_gr_construct_xfer_mpc()
3260 	else if (device->chipset < 0x94)  in nv50_gr_construct_xfer_mpc()
3261 		xf_emit(ctx, 0x3a2, 0);  in nv50_gr_construct_xfer_mpc()
3262 	else if (device->chipset == 0x98 || device->chipset == 0xaa)  in nv50_gr_construct_xfer_mpc()
3263 		xf_emit(ctx, 0x39f, 0);  in nv50_gr_construct_xfer_mpc()
3265 		xf_emit(ctx, 0x3a3, 0);  in nv50_gr_construct_xfer_mpc()
3266 	xf_emit(ctx, 1, 0x11);			/* 3f/7f DST_FORMAT */  in nv50_gr_construct_xfer_mpc()
3267 	xf_emit(ctx, 1, 0);			/* 7 OPERATION */  in nv50_gr_construct_xfer_mpc()
3269 	xf_emit(ctx, 0x2d, 0);  in nv50_gr_construct_xfer_mpc()
3278 	u32 units = nvkm_rd32(device, 0x1540);  in nv50_gr_construct_xfer2()
3279 	int size = 0;  in nv50_gr_construct_xfer2()
3281 	offset = (ctx->ctxvals_pos+0x3f)&~0x3f;  in nv50_gr_construct_xfer2()
3283 	if (device->chipset < 0xa0) {  in nv50_gr_construct_xfer2()
3284 		for (i = 0; i < 8; i++) {  in nv50_gr_construct_xfer2()
3288 			if (i == 0)  in nv50_gr_construct_xfer2()
3289 				xf_emit(ctx, 1, 0x08100c12); /* FP_INTERPOLANT_CTRL */  in nv50_gr_construct_xfer2()
3296 		/* Strand 0: TPs 0, 1 */  in nv50_gr_construct_xfer2()
3300 		xf_emit(ctx, 1, 0x08100c12); /* FP_INTERPOLANT_CTRL */  in nv50_gr_construct_xfer2()
3301 		if (units & (1 << 0))  in nv50_gr_construct_xfer2()
3340 	ctx->ctxvals_pos = (ctx->ctxvals_pos+0x3f)&~0x3f;  in nv50_gr_construct_xfer2()