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/illumos-gate/usr/src/uts/intel/io/vmm/io/
H A Dvlapic_priv.h52 #define APIC_OFFSET_ID 0x20 /* Local APIC ID */
53 #define APIC_OFFSET_VER 0x30 /* Local APIC Version */
54 #define APIC_OFFSET_TPR 0x80 /* Task Priority Register */
55 #define APIC_OFFSET_APR 0x90 /* Arbitration Priority */
56 #define APIC_OFFSET_PPR 0xA0 /* Processor Priority Register */
57 #define APIC_OFFSET_EOI 0xB0 /* EOI Register */
58 #define APIC_OFFSET_RRR 0xC0 /* Remote read */
59 #define APIC_OFFSET_LDR 0xD0 /* Logical Destination */
60 #define APIC_OFFSET_DFR 0xE0 /* Destination Format Register */
61 #define APIC_OFFSET_SVR 0xF0 /* Spurious Vector Register */
[all …]
/illumos-gate/usr/src/uts/common/io/bnxe/577xx/hsi/hw/include/
H A Dbigmac_addresses.h4 #define BIGMAC_REGISTER_BMAC_CONTROL (0x00<<3) //0x000
5 #define BIGMAC_REGISTER_BMAC_XGXS_CONTROL (0x01<<3) //0x008
6 #define BIGMAC_REGISTER_BMAC_XGXS_STATUS (0x02<<3) //0x010
7 #define BIGMAC_REGISTER_TX_MUX_CONTROL (0x03<<3) //0x018
8 #define BIGMAC_REGISTER_RX_MUX_CONTROL (0x04<<3) //0x020
9 #define BIGMAC_REGISTER_CNT_MAX_SIZE (0x05<<3) //0x028
10 #define BIGMAC_REGISTER_TX_CONTROL (0x07<<3) //0x038
11 #define BIGMAC_REGISTER_TX_SOURCE_ADDR (0x08<<3) //0x040
12 #define BIGMAC_REGISTER_TX_MAX_SIZE (0x09<<3) //0x048
13 #define BIGMAC_REGISTER_TX_PAUSE_THRESHOLD (0x0A<<3) //0x050
[all …]
/illumos-gate/usr/src/test/util-tests/tests/dis/i386/
H A D64.sse-4.1.out1 libdis_test: 66 0f 3a 0d c8 42 blendpd $0x42,%xmm0,%xmm1
2 libdis_test+0x6: 66 0f 3a 0d 0b 42 blendpd $0x42,(%rbx),%xmm1
3 libdis_test+0xc: 66 0f 3a 0c c8 42 blendps $0x42,%xmm0,%xmm1
4 libdis_test+0x12: 66 0f 3a 0c 0b 42 blendps $0x42,(%rbx),%xmm1
5 libdis_test+0x18: 66 0f 38 15 d1 blendvpd %xmm1,%xmm2
6 libdis_test+0x1d: 66 0f 38 15 13 blendvpd (%rbx),%xmm2
7 libdis_test+0x22: 66 0f 38 15 53 42 blendvpd 0x42(%rbx),%xmm2
8 libdis_test+0x28: 66 0f 38 14 d1 blendvps %xmm1,%xmm2
9 libdis_test+0x2d: 66 0f 38 14 13 blendvps (%rbx),%xmm2
10 libdis_test+0x32: 66 0f 38 14 53 42 blendvps 0x42(%rbx),%xmm2
[all …]
H A D64.avx512.out2 libdis_test+0x4: c5 f8 28 da vmovaps %xmm2,%xmm3
3 libdis_test+0x8: c5 f8 28 ec vmovaps %xmm4,%xmm5
4 libdis_test+0xc: c5 f8 28 fe vmovaps %xmm6,%xmm7
5 libdis_test+0x10: c4 41 78 28 c8 vmovaps %xmm8,%xmm9
6 libdis_test+0x15: c4 41 78 28 da vmovaps %xmm10,%xmm11
7 libdis_test+0x1a: c4 41 78 28 ec vmovaps %xmm12,%xmm13
8 libdis_test+0x1f: c4 41 78 28 fe vmovaps %xmm14,%xmm15
9 libdis_test+0x24: 62 a1 7c 08 28 c8 vmovaps %xmm16,%xmm17
10 libdis_test+0x2a: 62 a1 7c 08 28 da vmovaps %xmm18,%xmm19
11 libdis_test+0x30: 62 a1 7c 08 28 ec vmovaps %xmm20,%xmm21
[all …]
H A D64.avx.out2 libdis_test+0x4: c5 e1 58 20 vaddpd (%rax),%xmm3,%xmm4
3 libdis_test+0x8: c5 d1 58 71 42 vaddpd 0x42(%rcx),%xmm5,%xmm6
4 libdis_test+0xd: c5 f5 58 d0 vaddpd %ymm0,%ymm1,%ymm2
5 libdis_test+0x11: c5 e5 58 23 vaddpd (%rbx),%ymm3,%ymm4
6 libdis_test+0x15: c5 d5 58 72 42 vaddpd 0x42(%rdx),%ymm5,%ymm6
7 libdis_test+0x1a: c5 f0 58 d0 vaddps %xmm0,%xmm1,%xmm2
8 libdis_test+0x1e: c5 e0 58 20 vaddps (%rax),%xmm3,%xmm4
9 libdis_test+0x22: c5 d0 58 71 42 vaddps 0x42(%rcx),%xmm5,%xmm6
10 libdis_test+0x27: c5 f4 58 d0 vaddps %ymm0,%ymm1,%ymm2
11 libdis_test+0x2b: c5 e4 58 23 vaddps (%rbx),%ymm3,%ymm4
[all …]
H A D32.avx.out2 libdis_test+0x4: c5 e1 58 20 vaddpd (%eax),%xmm3,%xmm4
3 libdis_test+0x8: c5 d1 58 71 42 vaddpd 0x42(%ecx),%xmm5,%xmm6
4 libdis_test+0xd: c5 f5 58 d0 vaddpd %ymm0,%ymm1,%ymm2
5 libdis_test+0x11: c5 e5 58 23 vaddpd (%ebx),%ymm3,%ymm4
6 libdis_test+0x15: c5 d5 58 72 42 vaddpd 0x42(%edx),%ymm5,%ymm6
7 libdis_test+0x1a: c5 f0 58 d0 vaddps %xmm0,%xmm1,%xmm2
8 libdis_test+0x1e: c5 e0 58 20 vaddps (%eax),%xmm3,%xmm4
9 libdis_test+0x22: c5 d0 58 71 42 vaddps 0x42(%ecx),%xmm5,%xmm6
10 libdis_test+0x27: c5 f4 58 d0 vaddps %ymm0,%ymm1,%ymm2
11 libdis_test+0x2b: c5 e4 58 23 vaddps (%ebx),%ymm3,%ymm4
[all …]
/illumos-gate/usr/src/uts/common/sys/nxge/
H A Dnxge_mac_hw.h55 #define FILTER_M_CTL 0xDCEF1
59 #define BROADCAST_HASH_WORD 0x0f
60 #define BROADCAST_HASH_BIT 0x8000
66 #define XMAC_PORT_0 0
73 #define MAC_ADDR_REG_MASK 0xFFFF
79 * are reserved for port PHY type (Copper/Fibre). Bits 0 thru 3 are for port0
83 * type encoding for the ports 0 thru 3.
89 * 31..28 27..24 23..20 19..16 15..12 11.. 8 7.. 4 3.. 0
92 #define NXGE_PORT_SPD_NONE 0x0
93 #define NXGE_PORT_SPD_1G 0x1
[all …]
/illumos-gate/usr/src/cmd/cxgbetool/
H A Dcudbg_view_entity.h68 { "TxCongestion", 0, 1 },
117 { "ERssFceFipPkt", 0, 1 },
164 { "ERssFceFipPkt", 0, 1 },
234 {"0x0", "TP_MIB_MAC_IN_ERR_0"},
235 {"0x1", "TP_MIB_MAC_IN_ERR_1"},
236 {"0x2", "TP_MIB_MAC_IN_ERR_2"},
237 {"0x3", "TP_MIB_MAC_IN_ERR_3"},
238 {"0x4", "TP_MIB_HDR_IN_ERR_0"},
239 {"0x5", "TP_MIB_HDR_IN_ERR_1"},
240 {"0x6", "TP_MIB_HDR_IN_ERR_2"},
[all …]
/illumos-gate/usr/src/uts/common/io/cxgbe/common/
H A Dt4_regs.h19 #define MYPF_BASE 0x1b000
22 #define PF0_BASE 0x1e000
25 #define PF1_BASE 0x1e400
28 #define PF2_BASE 0x1e800
31 #define PF3_BASE 0x1ec00
34 #define PF4_BASE 0x1f000
37 #define PF5_BASE 0x1f400
40 #define PF6_BASE 0x1f800
43 #define PF7_BASE 0x1fc00
46 #define PF_STRIDE 0x400
[all …]