Lines Matching +full:0 +full:x2f0

68 	{ "TxCongestion", 0, 1 },
117 	{ "ERssFceFipPkt", 0, 1 },
164 	{ "ERssFceFipPkt", 0, 1 },
234 	{"0x0", "TP_MIB_MAC_IN_ERR_0"},
235 	{"0x1", "TP_MIB_MAC_IN_ERR_1"},
236 	{"0x2", "TP_MIB_MAC_IN_ERR_2"},
237 	{"0x3", "TP_MIB_MAC_IN_ERR_3"},
238 	{"0x4", "TP_MIB_HDR_IN_ERR_0"},
239 	{"0x5", "TP_MIB_HDR_IN_ERR_1"},
240 	{"0x6", "TP_MIB_HDR_IN_ERR_2"},
241 	{"0x7", "TP_MIB_HDR_IN_ERR_3"},
242 	{"0x8", "TP_MIB_TCP_IN_ERR_0"},
243 	{"0x9", "TP_MIB_TCP_IN_ERR_1"},
244 	{"0xA", "TP_MIB_TCP_IN_ERR_2"},
245 	{"0xB", "TP_MIB_TCP_IN_ERR_3"},
246 	{"0xC", "TP_MIB_TCP_OUT_RST"},
247 	{"0x10", "TP_MIB_TCP_IN_SEG_HI"},
248 	{"0x11", "TP_MIB_TCP_IN_SEG_LO"},
249 	{"0x12", "TP_MIB_TCP_OUT_SEG_HI"},
250 	{"0x13", "TP_MIB_TCP_OUT_SEG_LO"},
251 	{"0x14", "TP_MIB_TCP_RXT_SEG_HI"},
252 	{"0x15", "TP_MIB_TCP_RXT_SEG_LO"},
253 	{"0x18", "TP_MIB_TNL_CNG_DROP_0"},
254 	{"0x19", "TP_MIB_TNL_CNG_DROP_1"},
255 	{"0x1A", "TP_MIB_TNL_CNG_DROP_2"},
256 	{"0x1B", "TP_MIB_TNL_CNG_DROP_3"},
257 	{"0x1C", "TP_MIB_OFD_CHN_DROP_0"},
258 	{"0x1D", "TP_MIB_OFD_CHN_DROP_1"},
259 	{"0x1E", "TP_MIB_OFD_CHN_DROP_2"},
260 	{"0x1F", "TP_MIB_OFD_CHN_DROP_3"},
261 	{"0x20", "TP_MIB_TNL_OUT_PKT_0"},
262 	{"0x21", "TP_MIB_TNL_OUT_PKT_1"},
263 	{"0x22", "TP_MIB_TNL_OUT_PKT_2"},
264 	{"0x23", "TP_MIB_TNL_OUT_PKT_3"},
265 	{"0x24", "TP_MIB_TNL_IN_PKT_0"},
266 	{"0x25", "TP_MIB_TNL_IN_PKT_1"},
267 	{"0x26", "TP_MIB_TNL_IN_PKT_2"},
268 	{"0x27", "TP_MIB_TNL_IN_PKT_3"},
269 	{"0x28", "TP_MIB_TCP_V6IN_ERR_0"},
270 	{"0x29", "TP_MIB_TCP_V6IN_ERR_1"},
271 	{"0x2A", "TP_MIB_TCP_V6IN_ERR_2"},
272 	{"0x2B", "TP_MIB_TCP_V6IN_ERR_3"},
273 	{"0x2C", "TP_MIB_TCP_V6OUT_RST"},
274 	{"0x30", "TP_MIB_TCP_V6IN_SEG_HI"},
275 	{"0x31", "TP_MIB_TCP_V6IN_SEG_LO"},
276 	{"0x32", "TP_MIB_TCP_V6OUT_SEG_HI"},
277 	{"0x33", "TP_MIB_TCP_V6OUT_SEG_LO"},
278 	{"0x34", "TP_MIB_TCP_V6RXT_SEG_HI"},
279 	{"0x35", "TP_MIB_TCP_V6RXT_SEG_LO"},
280 	{"0x36", "TP_MIB_OFD_ARP_DROP"},
281 	{"0x37", "TP_MIB_OFD_DFR_DROP"},
282 	{"0x38", "TP_MIB_CPL_IN_REQ_0"},
283 	{"0x39", "TP_MIB_CPL_IN_REQ_1"},
284 	{"0x3A", "TP_MIB_CPL_IN_REQ_2"},
285 	{"0x3B", "TP_MIB_CPL_IN_REQ_3"},
286 	{"0x3C", "TP_MIB_CPL_OUT_RSP_0"},
287 	{"0x3D", "TP_MIB_CPL_OUT_RSP_1"},
288 	{"0x3E", "TP_MIB_CPL_OUT_RSP_2"},
289 	{"0x3F", "TP_MIB_CPL_OUT_RSP_3"},
290 	{"0x40", "TP_MIB_TNL_LPBK_0"},
291 	{"0x41", "TP_MIB_TNL_LPBK_1"},
292 	{"0x42", "TP_MIB_TNL_LPBK_2"},
293 	{"0x43", "TP_MIB_TNL_LPBK_3"},
294 	{"0x44", "TP_MIB_TNL_DROP_0"},
295 	{"0x45", "TP_MIB_TNL_DROP_1"},
296 	{"0x46", "TP_MIB_TNL_DROP_2"},
297 	{"0x47", "TP_MIB_TNL_DROP_3"},
298 	{"0x48", "TP_MIB_FCOE_DDP_0"},
299 	{"0x49", "TP_MIB_FCOE_DDP_1"},
300 	{"0x4A", "TP_MIB_FCOE_DDP_2"},
301 	{"0x4B", "TP_MIB_FCOE_DDP_3"},
302 	{"0x4C", "TP_MIB_FCOE_DROP_0"},
303 	{"0x4D", "TP_MIB_FCOE_DROP_1"},
304 	{"0x4E", "TP_MIB_FCOE_DROP_2"},
305 	{"0x4F", "TP_MIB_FCOE_DROP_3"},
306 	{"0x50", "TP_MIB_FCOE_BYTE_0_HI"},
307 	{"0x51", "TP_MIB_FCOE_BYTE_0_LO"},
308 	{"0x52", "TP_MIB_FCOE_BYTE_1_HI"},
309 	{"0x53", "TP_MIB_FCOE_BYTE_1_LO"},
310 	{"0x54", "TP_MIB_FCOE_BYTE_2_HI"},
311 	{"0x55", "TP_MIB_FCOE_BYTE_2_LO"},
312 	{"0x56", "TP_MIB_FCOE_BYTE_3_HI"},
313 	{"0x57", "TP_MIB_FCOE_BYTE_3_LO"},
314 	{"0x58", "TP_MIB_OFD_VLN_DROP_0"},
315 	{"0x59", "TP_MIB_OFD_VLN_DROP_1"},
316 	{"0x5A", "TP_MIB_OFD_VLN_DROP_2"},
317 	{"0x5B", "TP_MIB_OFD_VLN_DROP_3"},
318 	{"0x5C", "TP_MIB_USM_PKTS"},
319 	{"0x5D", "TP_MIB_USM_DROP"},
320 	{"0x5E", "TP_MIB_USM_BYTES_HI"},
321 	{"0x5F", "TP_MIB_USM_BYTES_LO"},
322 	{"0x60", "TP_MIB_TID_DEL"},
323 	{"0x61", "TP_MIB_TID_INV"},
324 	{"0x62", "TP_MIB_TID_ACT"},
325 	{"0x63", "TP_MIB_TID_PAS"},
326 	{"0x64", "TP_MIB_RQE_DFR_PKT"},
327 	{"0x65", "TP_MIB_RQE_DFR_MOD"},
328 	{"0x68", "TP_MIB_CPL_OUT_ERR_0"},
329 	{"0x69", "TP_MIB_CPL_OUT_ERR_1"},
330 	{"0x6A", "TP_MIB_CPL_OUT_ERR_2"},
331 	{"0x6B", "TP_MIB_CPL_OUT_ERR_3"},
332 	{"0x6c", "TP_MIB_ENG_LINE_0"},
333 	{"0x6d", "TP_MIB_ENG_LINE_1"},
334 	{"0x6e", "TP_MIB_ENG_LINE_2"},
335 	{"0x6f", "TP_MIB_ENG_LINE_3"},
336 	{"0x70", "TP_MIB_TNL_ERR_0"},
337 	{"0x71", "TP_MIB_TNL_ERR_1"},
338 	{"0x72", "TP_MIB_TNL_ERR_2"},
339 	{"0x73", "TP_MIB_TNL_ERR_3"}
343 	{"0x0", "TP_MIB_MAC_IN_ERR_0"},
344 	{"0x1", "TP_MIB_MAC_IN_ERR_1"},
345 	{"0x2", "TP_MIB_MAC_IN_ERR_2"},
346 	{"0x3", "TP_MIB_MAC_IN_ERR_3"},
347 	{"0x4", "TP_MIB_HDR_IN_ERR_0"},
348 	{"0x5", "TP_MIB_HDR_IN_ERR_1"},
349 	{"0x6", "TP_MIB_HDR_IN_ERR_2"},
350 	{"0x7", "TP_MIB_HDR_IN_ERR_3"},
351 	{"0x8", "TP_MIB_TCP_IN_ERR_0"},
352 	{"0x9", "TP_MIB_TCP_IN_ERR_1"},
353 	{"0xA", "TP_MIB_TCP_IN_ERR_2"},
354 	{"0xB", "TP_MIB_TCP_IN_ERR_3"},
355 	{"0xC", "TP_MIB_TCP_OUT_RST"},
356 	{"0x10", "TP_MIB_TCP_IN_SEG_HI"},
357 	{"0x11", "TP_MIB_TCP_IN_SEG_LO"},
358 	{"0x12", "TP_MIB_TCP_OUT_SEG_HI"},
359 	{"0x13", "TP_MIB_TCP_OUT_SEG_LO"},
360 	{"0x14", "TP_MIB_TCP_RXT_SEG_HI"},
361 	{"0x15", "TP_MIB_TCP_RXT_SEG_LO"},
362 	{"0x18", "TP_MIB_TNL_CNG_DROP_0"},
363 	{"0x19", "TP_MIB_TNL_CNG_DROP_1"},
364 	{"0x1A", "TP_MIB_TNL_CNG_DROP_2"},
365 	{"0x1B", "TP_MIB_TNL_CNG_DROP_3"},
366 	{"0x1C", "TP_MIB_OFD_CHN_DROP_0"},
367 	{"0x1D", "TP_MIB_OFD_CHN_DROP_1"},
368 	{"0x1E", "TP_MIB_OFD_CHN_DROP_2"},
369 	{"0x1F", "TP_MIB_OFD_CHN_DROP_3"},
370 	{"0x20", "TP_MIB_TNL_OUT_PKT_0"},
371 	{"0x21", "TP_MIB_TNL_OUT_PKT_1"},
372 	{"0x22", "TP_MIB_TNL_OUT_PKT_2"},
373 	{"0x23", "TP_MIB_TNL_OUT_PKT_3"},
374 	{"0x24", "TP_MIB_TNL_IN_PKT_0"},
375 	{"0x25", "TP_MIB_TNL_IN_PKT_1"},
376 	{"0x26", "TP_MIB_TNL_IN_PKT_2"},
377 	{"0x27", "TP_MIB_TNL_IN_PKT_3"},
378 	{"0x28", "TP_MIB_TCP_V6IN_ERR_0"},
379 	{"0x29", "TP_MIB_TCP_V6IN_ERR_1"},
380 	{"0x2A", "TP_MIB_TCP_V6IN_ERR_2"},
381 	{"0x2B", "TP_MIB_TCP_V6IN_ERR_3"},
382 	{"0x2C", "TP_MIB_TCP_V6OUT_RST"},
383 	{"0x30", "TP_MIB_TCP_V6IN_SEG_HI"},
384 	{"0x31", "TP_MIB_TCP_V6IN_SEG_LO"},
385 	{"0x32", "TP_MIB_TCP_V6OUT_SEG_HI"},
386 	{"0x33", "TP_MIB_TCP_V6OUT_SEG_LO"},
387 	{"0x34", "TP_MIB_TCP_V6RXT_SEG_HI"},
388 	{"0x35", "TP_MIB_TCP_V6RXT_SEG_LO"},
389 	{"0x36", "TP_MIB_OFD_ARP_DROP"},
390 	{"0x37", "TP_MIB_OFD_DFR_DROP"},
391 	{"0x38", "TP_MIB_CPL_IN_REQ_0"},
392 	{"0x39", "TP_MIB_CPL_IN_REQ_1"},
393 	{"0x3A", "TP_MIB_CPL_IN_REQ_2"},
394 	{"0x3B", "TP_MIB_CPL_IN_REQ_3"},
395 	{"0x3C", "TP_MIB_CPL_OUT_RSP_0"},
396 	{"0x3D", "TP_MIB_CPL_OUT_RSP_1"},
397 	{"0x3E", "TP_MIB_CPL_OUT_RSP_2"},
398 	{"0x3F", "TP_MIB_CPL_OUT_RSP_3"},
399 	{"0x40", "TP_MIB_TNL_LPBK_0"},
400 	{"0x41", "TP_MIB_TNL_LPBK_1"},
401 	{"0x42", "TP_MIB_TNL_LPBK_2"},
402 	{"0x43", "TP_MIB_TNL_LPBK_3"},
403 	{"0x44", "TP_MIB_TNL_DROP_0"},
404 	{"0x45", "TP_MIB_TNL_DROP_1"},
405 	{"0x46", "TP_MIB_TNL_DROP_2"},
406 	{"0x47", "TP_MIB_TNL_DROP_3"},
407 	{"0x48", "TP_MIB_FCOE_DDP_0"},
408 	{"0x49", "TP_MIB_FCOE_DDP_1"},
409 	{"0x4A", "TP_MIB_FCOE_DDP_2"},
410 	{"0x4B", "TP_MIB_FCOE_DDP_3"},
411 	{"0x4C", "TP_MIB_FCOE_DROP_0"},
412 	{"0x4D", "TP_MIB_FCOE_DROP_1"},
413 	{"0x4E", "TP_MIB_FCOE_DROP_2"},
414 	{"0x4F", "TP_MIB_FCOE_DROP_3"},
415 	{"0x50", "TP_MIB_FCOE_BYTE_0_HI"},
416 	{"0x51", "TP_MIB_FCOE_BYTE_0_LO"},
417 	{"0x52", "TP_MIB_FCOE_BYTE_1_HI"},
418 	{"0x53", "TP_MIB_FCOE_BYTE_1_LO"},
419 	{"0x54", "TP_MIB_FCOE_BYTE_2_HI"},
420 	{"0x55", "TP_MIB_FCOE_BYTE_2_LO"},
421 	{"0x56", "TP_MIB_FCOE_BYTE_3_HI"},
422 	{"0x57", "TP_MIB_FCOE_BYTE_3_LO"},
423 	{"0x58", "TP_MIB_OFD_VLN_DROP_0"},
424 	{"0x59", "TP_MIB_OFD_VLN_DROP_1"},
425 	{"0x5A", "TP_MIB_OFD_VLN_DROP_2"},
426 	{"0x5B", "TP_MIB_OFD_VLN_DROP_3"},
427 	{"0x5C", "TP_MIB_USM_PKTS"},
428 	{"0x5D", "TP_MIB_USM_DROP"},
429 	{"0x5E", "TP_MIB_USM_BYTES_HI"},
430 	{"0x5F", "TP_MIB_USM_BYTES_LO"},
431 	{"0x60", "TP_MIB_TID_DEL"},
432 	{"0x61", "TP_MIB_TID_INV"},
433 	{"0x62", "TP_MIB_TID_ACT"},
434 	{"0x63", "TP_MIB_TID_PAS"},
435 	{"0x64", "TP_MIB_RQE_DFR_PKT"},
436 	{"0x65", "TP_MIB_RQE_DFR_MOD"},
437 	{"0x68", "TP_MIB_CPL_OUT_ERR_0"},
438 	{"0x69", "TP_MIB_CPL_OUT_ERR_1"},
439 	{"0x6A", "TP_MIB_CPL_OUT_ERR_2"},
440 	{"0x6B", "TP_MIB_CPL_OUT_ERR_3"}
444 	{ "TP_TX_MOD_Q7_Q6_TIMER_SEPARATOR", 0x0, 0 },
446 	{ "S_TXTIMERSEPQ6", 0, 16 },
447 	{ "TP_TX_MOD_Q5_Q4_TIMER_SEPARATOR", 0x1, 0 },
449 	{ "S_TXTIMERSEPQ4", 0, 16 },
450 	{ "TP_TX_MOD_Q3_Q2_TIMER_SEPARATOR", 0x2, 0 },
452 	{ "S_TXTIMERSEPQ2", 0, 16 },
453 	{ "TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR", 0x3, 0 },
455 	{ "S_TXTIMERSEPQ0", 0, 16 },
456 	{ "TP_RX_MOD_Q1_Q0_TIMER_SEPARATOR", 0x4, 0 },
458 	{ "S_RXTIMERSEPQ0", 0, 16 },
459 	{ "TP_TX_MOD_Q7_Q6_RATE_LIMIT", 0x5, 0 },
463 	{ "S_TXRATETCKQ6", 0, 8 },
464 	{ "TP_TX_MOD_Q5_Q4_RATE_LIMIT", 0x6, 0 },
468 	{ "S_TXRATETCKQ4", 0, 8 },
469 	{ "TP_TX_MOD_Q3_Q2_RATE_LIMIT", 0x7, 0 },
473 	{ "S_TXRATETCKQ2", 0, 8 },
474 	{ "TP_TX_MOD_Q1_Q0_RATE_LIMIT", 0x8, 0 },
478 	{ "S_TXRATETCKQ0", 0, 8 },
479 	{ "TP_RX_MOD_Q1_Q0_RATE_LIMIT", 0x9, 0 },
483 	{ "S_RXRATETCKQ0", 0, 8 },
484 	{ "TP_TX_MOD_C3_C2_RATE_LIMIT", 0xA, 0 },
485 	{ "TP_TX_MOD_C1_C0_RATE_LIMIT", 0xB, 0 },
490 	{ "TP_TX_MOD_Q7_Q6_TIMER_SEPARATOR", 0x0, 0 },
492 	{ "S_TXTIMERSEPQ6", 0, 16 },
493 	{ "TP_TX_MOD_Q5_Q4_TIMER_SEPARATOR", 0x1, 0 },
495 	{ "S_TXTIMERSEPQ4", 0, 16 },
496 	{ "TP_TX_MOD_Q3_Q2_TIMER_SEPARATOR", 0x2, 0 },
498 	{ "S_TXTIMERSEPQ2", 0, 16 },
499 	{ "TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR", 0x3, 0 },
501 	{ "S_TXTIMERSEPQ0", 0, 16 },
502 	{ "TP_RX_MOD_Q1_Q0_TIMER_SEPARATOR", 0x4, 0 },
504 	{ "S_RXTIMERSEPQ0", 0, 16 },
505 	{ "TP_TX_MOD_Q7_Q6_RATE_LIMIT", 0x5, 0 },
509 	{ "S_TXRATETCKQ6", 0, 8 },
510 	{ "TP_TX_MOD_Q5_Q4_RATE_LIMIT", 0x6, 0 },
514 	{ "S_TXRATETCKQ4", 0, 8 },
515 	{ "TP_TX_MOD_Q3_Q2_RATE_LIMIT", 0x7, 0 },
519 	{ "S_TXRATETCKQ2", 0, 8 },
520 	{ "TP_TX_MOD_Q1_Q0_RATE_LIMIT", 0x8, 0 },
524 	{ "S_TXRATETCKQ0", 0, 8 },
525 	{ "TP_RX_MOD_Q1_Q0_RATE_LIMIT", 0x9, 0 },
529 	{ "S_RXRATETCKQ0", 0, 8 },
530 	{ "TP_TX_MOD_C3_C2_RATE_LIMIT", 0xA, 0 },
531 	{ "TP_TX_MOD_C1_C0_RATE_LIMIT", 0xB, 0 },
536 	{ "TP_RX_SCHED_MAP", 0x20, 0 },
540 	{ "S_RXMAPCHANNEL0", 0, 8 },
541 	{ "TP_RX_SCHED_SGE", 0x21, 0 },
547 	{ "S_RXSGECHANNEL0", 0, 1 },
548 	{ "TP_TX_SCHED_MAP", 0x22, 0 },
552 	{ "S_TXMAPCHANNEL0", 0, 4 },
553 	{ "TP_TX_SCHED_HDR", 0x23, 0 },
561 	{ "S_TXMAPHDRCHANNEL0", 0, 4 },
562 	{ "TP_TX_SCHED_FIFO", 0x24, 0 },
570 	{ "S_TXMAPFIFOCHANNEL0", 0, 4 },
571 	{ "TP_TX_SCHED_PCMD", 0x25, 0 },
579 	{ "S_TXMAPPCMDCHANNEL0", 0, 4 },
580 	{ "TP_TX_SCHED_LPBK", 0x26, 0 },
588 	{ "S_TXMAPLPBKCHANNEL0", 0, 4 },
589 	{ "TP_CHANNEL_MAP", 0x27, 0 },
602 	{ "RxMapE2CChannel0", 0, 1 },
603 	{ "TP_RX_LPBK", 0x28, 0 },
615 	{ "CommitLimit0", 0, 6 },
616 	{ "TP_TX_LPBK", 0x29, 0 },
628 	{ "CommitLimit0", 0, 6 },
630 	{ "TP_TX_SCHED_PPP", 0x2A, 0 },
634 	{ "S_TXPPPENPORT0", 0, 8 },
635 	{ "TP_RX_SCHED_FIFO", 0x2B, 0 },
639 	{ "S_COMMITLIMIT0L", 0, 8 },
640 	{ "TP_IPMI_CFG1", 0x2E, 0 },
645 	{ "S_IPMI_VLAN", 0, 16 },
646 	{ "TP_IPMI_CFG2", 0x2F, 0 },
648 	{ "S_PRIMARYPORT", 0, 16 },
649 	{ "TP_RSS_PF0_CONFIG", 0x30, 0 },
660 	{ "S_CH0DEFAULTQUEUE", 0, 10 },
661 	{ "TP_RSS_PF1_CONFIG", 0x31, 0 },
672 	{ "S_CH0DEFAULTQUEUE", 0, 10 },
673 	{ "TP_RSS_PF2_CONFIG", 0x32, 0 },
684 	{ "S_CH0DEFAULTQUEUE", 0, 10 },
685 	{ "TP_RSS_PF3_CONFIG", 0x33, 0 },
696 	{ "S_CH0DEFAULTQUEUE", 0, 10 },
697 	{ "TP_RSS_PF4_CONFIG", 0x34, 0 },
708 	{ "S_CH0DEFAULTQUEUE", 0, 10 },
709 	{ "TP_RSS_PF5_CONFIG", 0x35, 0 },
720 	{ "S_CH0DEFAULTQUEUE", 0, 10 },
721 	{ "TP_RSS_PF6_CONFIG", 0x36, 0 },
732 	{ "S_CH0DEFAULTQUEUE", 0, 10 },
733 	{ "TP_RSS_PF7_CONFIG", 0x37, 0 },
744 	{ "S_CH0DEFAULTQUEUE", 0, 10 },
745 	{ "TP_RSS_PF_MAP", 0x38, 0 },
754 	{ "S_PF0LKPIDX", 0, 3 },
755 	{ "TP_RSS_PF_MSK", 0x39, 0 },
763 	{ "S_PF0MSKSIZE", 0, 4 },
764 	{ "TP_RSS_VFL_CONFIG", 0x3A, 0 },
765 	{ "S_KEYSCRAMBLE", 0, 32 },
766 	{ "TP_RSS_VFH_CONFIG", 0x3B, 0 },
779 	{ "S_KEYINDEX", 0, 4 },
784 	{ "TP_RX_SCHED_MAP", 0x20, 0 },
788 	{ "S_RXMAPCHANNEL0", 0, 8 },
789 	{ "TP_RX_SCHED_SGE", 0x21, 0 },
795 	{ "S_RXSGECHANNEL0", 0, 1 },
796 	{ "TP_TX_SCHED_MAP", 0x22, 0 },
800 	{ "S_TXMAPCHANNEL0", 0, 4 },
801 	{ "TP_TX_SCHED_HDR", 0x23, 0 },
809 	{ "S_TXMAPHDRCHANNEL0", 0, 4 },
810 	{ "TP_TX_SCHED_FIFO", 0x24, 0 },
818 	{ "S_TXMAPFIFOCHANNEL0", 0, 4 },
819 	{ "TP_TX_SCHED_PCMD", 0x25, 0 },
827 	{ "S_TXMAPPCMDCHANNEL0", 0, 4 },
828 	{ "TP_TX_SCHED_LPBK", 0x26, 0 },
836 	{ "S_TXMAPLPBKCHANNEL0", 0, 4 },
837 	{ "TP_CHANNEL_MAP", 0x27, 0 },
850 	{ "RxMapE2CChannel0", 0, 1 },
851 	{ "TP_RX_LPBK", 0x28, 0 },
852 	{ "TP_TX_LPBK", 0x29, 0 },
853 	{ "TP_TX_SCHED_PPP", 0x2A, 0 },
857 	{ "S_TXPPPENPORT0", 0, 8 },
858 	{ "TP_RX_SCHED_FIFO", 0x2B, 0 },
862 	{ "S_COMMITLIMIT0L", 0, 8 },
863 	{ "TP_IPMI_CFG1", 0x2E, 0 },
868 	{ "S_IPMI_VLAN", 0, 16 },
869 	{ "TP_IPMI_CFG2", 0x2F, 0 },
871 	{ "S_PRIMARYPORT", 0, 16 },
872 	{ "TP_RSS_PF0_CONFIG", 0x30, 0 },
883 	{ "S_CH0DEFAULTQUEUE", 0, 10 },
884 	{ "TP_RSS_PF1_CONFIG", 0x31, 0 },
895 	{ "S_CH0DEFAULTQUEUE", 0, 10 },
896 	{ "TP_RSS_PF2_CONFIG", 0x32, 0 },
907 	{ "S_CH0DEFAULTQUEUE", 0, 10 },
908 	{ "TP_RSS_PF3_CONFIG", 0x33, 0 },
919 	{ "S_CH0DEFAULTQUEUE", 0, 10 },
920 	{ "TP_RSS_PF4_CONFIG", 0x34, 0 },
931 	{ "S_CH0DEFAULTQUEUE", 0, 10 },
932 	{ "TP_RSS_PF5_CONFIG", 0x35, 0 },
943 	{ "S_CH0DEFAULTQUEUE", 0, 10 },
944 	{ "TP_RSS_PF6_CONFIG", 0x36, 0 },
955 	{ "S_CH0DEFAULTQUEUE", 0, 10 },
956 	{ "TP_RSS_PF7_CONFIG", 0x37, 0 },
967 	{ "S_CH0DEFAULTQUEUE", 0, 10 },
968 	{ "TP_RSS_PF_MAP", 0x38, 0 },
977 	{ "S_PF0LKPIDX", 0, 3 },
978 	{ "TP_RSS_PF_MSK", 0x39, 0 },
986 	{ "S_PF0MSKSIZE", 0, 4 },
987 	{ "TP_RSS_VFL_CONFIG", 0x3A, 0 },
988 	{ "S_KEYSCRAMBLE", 0, 32 },
989 	{ "TP_RSS_VFH_CONFIG", 0x3B, 0 },
1002 	{ "S_KEYINDEX", 0, 4 },
1007 	{ "TP_RSS_SECRET_KEY0", 0x40, 0 },
1008 	{ "TP_RSS_SECRET_KEY1", 0x41, 0 },
1009 	{ "TP_RSS_SECRET_KEY2", 0x42, 0 },
1010 	{ "TP_RSS_SECRET_KEY3", 0x43, 0 },
1011 	{ "TP_RSS_SECRET_KEY4", 0x44, 0 },
1012 	{ "TP_RSS_SECRET_KEY5", 0x45, 0 },
1013 	{ "TP_RSS_SECRET_KEY6", 0x46, 0 },
1014 	{ "TP_RSS_SECRET_KEY7", 0x47, 0 },
1015 	{ "TP_RSS_SECRET_KEY8", 0x48, 0 },
1016 	{ "TP_RSS_SECRET_KEY9", 0x49, 0 },
1021 	{ "TP_ETHER_TYPE_VL", 0x50, 0 },
1023 	{ "S_VLANTYPE", 0, 16 },
1024 	{ "TP_ETHER_TYPE_IP", 0x51, 0 },
1026 	{ "S_IPV4TYPE", 0, 16 },
1027 	{ "TP_ETHER_TYPE_FW", 0x52, 0 },
1029 	{ "S_ETHTYPE0", 0, 16 },
1030 	{ "TP_VXLAN_HEADER", 0x53, 0 },
1031 	{ "S_VXLANPORT", 0, 16 },
1032 	{ "TP_CORE_POWER", 0x54, 0 },
1042 	{ "S_SLEEPREQRSS", 0, 1 },
1043 	{ "TP_CORE_RDMA", 0x55, 0 },
1051 	{ "S_IMMEDIATEEN", 0, 1 },
1052 	{ "TP_FRAG_CONFIG", 0x56, 0 },
1061 	{ "PassMode", 0, 2 },
1062 	{ "TP_CMM_CONFIG", 0x57, 0 },
1068 	{ "WrThrThresh", 0, 5},
1069 	{ "TP_VXLAN_CONFIG", 0x58, 0 },
1071 	{ "VxLanType", 0, 16},
1072 	{ "TP_NVGRE_CONFIG", 0x59, 0 },
1074 	{ "GreType", 0, 16 },
1079 	{ "TP_RSS_SECRET_KEY0", 0x40, 0 },
1080 	{ "TP_RSS_SECRET_KEY1", 0x41, 0 },
1081 	{ "TP_RSS_SECRET_KEY2", 0x42, 0 },
1082 	{ "TP_RSS_SECRET_KEY3", 0x43, 0 },
1083 	{ "TP_RSS_SECRET_KEY4", 0x44, 0 },
1084 	{ "TP_RSS_SECRET_KEY5", 0x45, 0 },
1085 	{ "TP_RSS_SECRET_KEY6", 0x46, 0 },
1086 	{ "TP_RSS_SECRET_KEY7", 0x47, 0 },
1087 	{ "TP_RSS_SECRET_KEY8", 0x48, 0 },
1088 	{ "TP_RSS_SECRET_KEY9", 0x49, 0 },
1089 	{ "TP_ETHER_TYPE_VL", 0x50, 0 },
1091 	{ "S_VLANTYPE", 0, 16 },
1092 	{ "TP_ETHER_TYPE_IP", 0x51, 0 },
1094 	{ "S_IPV4TYPE", 0, 16 },
1095 	{ "TP_ETHER_TYPE_FW", 0x52, 0 },
1097 	{ "S_ETHTYPE0", 0, 16 },
1102 	{ "TP_CORE_POWER", 0x54, 0 },
1112 	{ "S_SLEEPREQRSS", 0, 1 },
1113 	{ "TP_CORE_RDMA", 0x55, 0 },
1119 	{ "S_IMMEDIATEEN", 0, 1 },
1124 	{"SGE_DEBUG_DATA_HIGH_INDEX_0", 0x1280},
1125 	{"SGE_DEBUG_DATA_HIGH_INDEX_1", 0x1284},
1126 	{"SGE_DEBUG_DATA_HIGH_INDEX_2", 0x1288},
1127 	{"SGE_DEBUG_DATA_HIGH_INDEX_3", 0x128c},
1128 	{"SGE_DEBUG_DATA_HIGH_INDEX_4", 0x1290},
1129 	{"SGE_DEBUG_DATA_HIGH_INDEX_5", 0x1294},
1130 	{"SGE_DEBUG_DATA_HIGH_INDEX_6", 0x1298},
1131 	{"SGE_DEBUG_DATA_HIGH_INDEX_7", 0x129c},
1132 	{"SGE_DEBUG_DATA_HIGH_INDEX_8", 0x12a0},
1133 	{"SGE_DEBUG_DATA_HIGH_INDEX_9", 0x12a4},
1134 	{"SGE_DEBUG_DATA_HIGH_INDEX_10", 0x12a8},
1135 	{"SGE_DEBUG_DATA_HIGH_INDEX_11", 0x12ac},
1136 	{"SGE_DEBUG_DATA_HIGH_INDEX_12", 0x12b0},
1137 	{"SGE_DEBUG_DATA_HIGH_INDEX_13", 0x12b4},
1138 	{"SGE_DEBUG_DATA_HIGH_INDEX_14", 0x12b8},
1139 	{"SGE_DEBUG_DATA_HIGH_INDEX_15", 0x12bc},
1144 	{"SGE_DEBUG_DATA_LOW_INDEX_0", 0x12c0},
1145 	{"SGE_DEBUG_DATA_LOW_INDEX_1", 0x12c4},
1146 	{"SGE_DEBUG_DATA_LOW_INDEX_2", 0x12c8},
1147 	{"SGE_DEBUG_DATA_LOW_INDEX_3", 0x12cc},
1148 	{"SGE_DEBUG_DATA_LOW_INDEX_4", 0x12d0},
1149 	{"SGE_DEBUG_DATA_LOW_INDEX_5", 0x12d4},
1150 	{"SGE_DEBUG_DATA_LOW_INDEX_6", 0x12d8},
1151 	{"SGE_DEBUG_DATA_LOW_INDEX_7", 0x12dc},
1152 	{"SGE_DEBUG_DATA_LOW_INDEX_8", 0x12e0},
1153 	{"SGE_DEBUG_DATA_LOW_INDEX_9", 0x12e4},
1154 	{"SGE_DEBUG_DATA_LOW_INDEX_10", 0x12e8},
1155 	{"SGE_DEBUG_DATA_LOW_INDEX_11", 0x12ec},
1156 	{"SGE_DEBUG_DATA_LOW_INDEX_12", 0x12f0},
1157 	{"SGE_DEBUG_DATA_LOW_INDEX_13", 0x12f4},
1158 	{"SGE_DEBUG_DATA_LOW_INDEX_14", 0x12f8},
1159 	{"SGE_DEBUG_DATA_LOW_INDEX_15", 0x12fc},
1163 	{ "TP_DBG_CLEAR", 0x60, 0 },
1164 	{ "TP_DBG_CORE_HDR0", 0x61, 0 },
1182 	{ "S_E_TCP_OPT_RXVALID", 0, 1 },
1183 	{ "TP_DBG_CORE_HDR1", 0x62, 0 },
1191 	{ "S_E_TCP_OPT_RXFULL", 0, 1 },
1192 	{ "TP_DBG_CORE_FATAL", 0x63, 0 },
1210 	{ "S_CPCMDEOICNT", 0, 2 },
1211 	{ "TP_DBG_CORE_OUT", 0x64, 0 },
1243 	{ "S_EPLDTXZEROPDRDY", 0, 1 },
1244 	{ "TP_DBG_CORE_TID", 0x65, 0 },
1249 	{ "S_TIDVALUE", 0, 20 },
1250 	{ "TP_DBG_ENG_RES0", 0x66, 0 },
1275 	{ "S_EPCMDBUSY", 0, 1 },
1276 	{ "TP_DBG_ENG_RES1", 0x67, 0 },
1296 	{ "TP_DBG_ENG_RES2", 0x68, 0 },
1311 	{ "S_RCFREASONOUT", 0, 4 },
1312 	{ "TP_DBG_CORE_PCMD", 0x69, 0 },
1316 	{ "S_EPCMDLENSAVE", 0, 14 },
1317 	{ "TP_DBG_SCHED_TX", 0x6A, 0 },
1323 	{ "S_TXMODXOFF", 0, 8 },
1324 	{ "TP_DBG_SCHED_RX", 0x6B, 0 },
1333 	{ "S_RXMODXOFF", 0, 2 },
1334 	{ "TP_DBG_ERROR_CNT", 0x6C, 0 },
1335 	{ "TP_DBG_CORE_CPL", 0x6d, 0 },
1339 	{ "CplCmdOut0", 0, 8 },
1345 	{ "TP_DBG_CLEAR", 0x60, 0 },
1346 	{ "TP_DBG_CORE_HDR0", 0x61, 0 },
1364 	{ "S_E_TCP_OPT_RXVALID", 0, 1 },
1365 	{ "TP_DBG_CORE_HDR1", 0x62, 0 },
1373 	{ "S_E_TCP_OPT_RXFULL", 0, 1 },
1374 	{ "TP_DBG_CORE_FATAL", 0x63, 0 },
1392 	{ "S_CPCMDEOICNT", 0, 2 },
1393 	{ "TP_DBG_CORE_OUT", 0x64, 0 },
1420 	{ "S_EPLDTXZEROPDRDY", 0, 1 },
1421 	{ "TP_DBG_CORE_TID", 0x65, 0 },
1426 	{ "S_TIDVALUE", 0, 20 },
1427 	{ "TP_DBG_ENG_RES0", 0x66, 0 },
1452 	{ "S_EPCMDBUSY", 0, 1 },
1453 	{ "TP_DBG_ENG_RES1", 0x67, 0 },
1474 	{ "S_RCFDATACMRDY", 0, 1 },
1475 	{ "TP_DBG_ENG_RES2", 0x68, 0 },
1490 	{ "S_RCFREASONOUT", 0, 4 },
1491 	{ "TP_DBG_CORE_PCMD", 0x69, 0 },
1495 	{ "S_EPCMDLENSAVE", 0, 14 },
1496 	{ "TP_DBG_SCHED_TX", 0x6A, 0 },
1502 	{ "S_TXMODXOFF", 0, 8 },
1503 	{ "TP_DBG_SCHED_RX", 0x6B, 0 },
1512 	{ "S_RXMODXOFF", 0, 2 },
1513 	{ "TP_DBG_ERROR_CNT", 0x6C, 0 },
1518 	{ "TP_MIB_DEBUG", 0x6F, 0 },
1526 	{ "S_LINENUM0", 0, 7 },
1531 	{ "TP_DBG_ESIDE_PKT0", 0x130, 0 },
1539 	{ "S_ERXPLDEOPCNT", 0, 4 },
1540 	{ "TP_DBG_ESIDE_PKT1", 0x131, 0 },
1548 	{ "S_ERXPLDEOPCNT", 0, 4 },
1549 	{ "TP_DBG_ESIDE_PKT2", 0x132, 0 },
1557 	{ "S_ERXPLDEOPCNT", 0, 4 },
1558 	{ "TP_DBG_ESIDE_PKT3", 0x133, 0 },
1566 	{ "S_ERXPLDEOPCNT", 0, 4 },
1567 	{ "TP_DBG_ESIDE_FIFO0", 0x134, 0 },
1599 	{ "S_ERXFULL0", 0, 1 },
1600 	{ "TP_DBG_ESIDE_FIFO1", 0x135, 0 },
1632 	{ "S_ERXFULL2", 0, 1 },
1633 	{ "TP_DBG_ESIDE_DISP0", 0x136, 0 },
1658 	{ "S_TXFULL", 0, 1 },
1659 	{ "TP_DBG_ESIDE_DISP1", 0x137, 0 },
1684 	{ "S_TXFULL", 0, 1 },
1685 	{ "TP_MAC_MATCH_MAP0", 0x138, 0 },
1690 	{ "S_MAPWRITE", 0, 1 },
1691 	{ "TP_MAC_MATCH_MAP1", 0x139, 0 },
1693 	{ "S_MAPVALUERD", 0, 9 },
1694 	{ "TP_DBG_ESIDE_DISP2", 0x13A, 0 },
1719 	{ "S_TXFULL", 0, 1 },
1720 	{ "TP_DBG_ESIDE_DISP3", 0x13B, 0 },
1745 	{ "S_TXFULL", 0, 1 },
1746 	{ "TP_DBG_ESIDE_HDR0", 0x13C, 0 },
1754 	{ "S_CPLEOPCNT", 0, 4 },
1755 	{ "TP_DBG_ESIDE_HDR1", 0x13D, 0 },
1763 	{ "S_CPLEOPCNT", 0, 4 },
1764 	{ "TP_DBG_ESIDE_HDR2", 0x13E, 0 },
1772 	{ "S_CPLEOPCNT", 0, 4 },
1773 	{ "TP_DBG_ESIDE_HDR3", 0x13F, 0 },
1781 	{ "S_CPLEOPCNT", 0, 4 },
1782 	{ "TP_VLAN_PRI_MAP", 0x140, 0 },
1795 	{ "S_FCOE", 0, 1 },
1796 	{ "TP_INGRESS_CONFIG", 0x141, 0 },
1806 	{ "S_IPV6_EXT_HDR_SKIP", 0, 8 },
1811 	{ "TP_INGRESS_CONFIG2", 0x145, 0 },
1816 	{ "S_TNL_PLD_FILTER_OFFSET", 0, 10 },
1817 	{ "TP_EHDR_CONFIG_LO", 0x146, 0 },
1821 	{ "S_TCPLIMIT", 0, 8 },
1822 	{ "TP_EHDR_CONFIG_HI", 0x147, 0 },
1826 	{ "S_TCPLIMIT", 0, 8 },
1827 	{ "TP_DBG_ESIDE_INT", 0x148, 0 },
1841 	{ "S_TCPOPTTXFULL", 0, 1 },
1842 	{ "TP_DBG_ESIDE_DEMUX", 0x149, 0 },
1850 	{ "S_ETCPOPDONE", 0, 4 },
1851 	{ "TP_DBG_ESIDE_IN0", 0x14A, 0 },
1883 	{ "S_RX_PKT_ATTR_DRDY", 0, 1 },
1884 	{ "TP_DBG_ESIDE_IN1", 0x14B, 0 },
1916 	{ "S_RX_PKT_ATTR_DRDY", 0, 1 },
1917 	{ "TP_DBG_ESIDE_IN2", 0x14C, 0 },
1949 	{ "S_RX_PKT_ATTR_DRDY", 0, 1 },
1950 	{ "TP_DBG_ESIDE_IN3", 0x14D, 0 },
1982 	{ "S_RX_PKT_ATTR_DRDY", 0, 1 },
1983 	{ "TP_DBG_ESIDE_FRM", 0x14E, 0 },
1991 	{ "S_ERXSIZEERROR0", 0, 4 },
1992 	{ "TP_DBG_ESIDE_DRP", 0x14F, 0 },
1996 	{ "S_RXDROP0", 0, 8 },
1997 	{ "TP_DBG_ESIDE_TX", 0x150, 0 },
2000 	{ "S_ETXFULL", 0, 4 },
2001 	{ "TP_ESIDE_SVID_MASK", 0x151, 0 },
2002 	{ "TP_ESIDE_DVID_MASK", 0x152, 0 },
2003 	{ "TP_ESIDE_ALIGN_MASK", 0x153, 0 },
2007 	{ "S_SVID_ID_OFFSET", 0, 8 },
2008 	{ "TP_DBG_ESIDE_OP", 0x154, 0 },
2028 	{ "S_OPT_PARSER_OTK_STATE_CHANNEL3", 0, 2 },
2029 	{ "TP_DBG_ESIDE_OP_ALT", 0x155, 0 },
2041 	{ "S_OPT_PARSER_PSTATE_ERRNO_CHANNEL3", 0, 5 },
2042 	{ "TP_DBG_ESIDE_OP_BUSY", 0x156, 0 },
2046 	{ "S_OPT_PARSER_BUSY_VEC_CHANNEL0", 0, 8 },
2047 	{ "TP_DBG_ESIDE_OP_COOKIE", 0x157, 0 },
2051 	{ "S_OPT_PARSER_COOKIE_CHANNEL0", 0, 8 },
2057 	{ "TP_ESIDE_CONFIG", 0x160, 0 },
2064 	{ "RoCEv2UDPPort", 0, 16 },
2069 	{ "TP_DBG_CACHE_WR_ALL", 0x70, 0 },
2070 	{ "TP_DBG_CACHE_WR_HIT", 0x71, 0 },
2071 	{ "TP_DBG_CACHE_RD_ALL", 0x72, 0 },
2072 	{ "TP_DBG_CACHE_RD_HIT", 0x73, 0 },
2073 	{ "TP_DBG_CACHE_MC_REQ", 0x74, 0 },
2074 	{ "TP_DBG_CACHE_MC_RSP", 0x75, 0 },
2079 	{ "TP_MIB_DEBUG", 0x6F, 0 },
2087 	{ "S_LINENUM0", 0, 7 },
2092 	{ "TP_TX_DROP_CNT_CH0", 0x120, 0 },
2093 	{ "TP_TX_DROP_CNT_CH1", 0x121, 0 },
2094 	{ "TP_TX_DROP_CNT_CH2", 0x122, 0 },
2095 	{ "TP_TX_DROP_CNT_CH3", 0x123, 0 },
2100 	{ "TP_TX_DROP_CFG_CH0", 0x12B, 0 },
2104 	{ "S_PACKETDROPS", 0, 4 },
2105 	{ "TP_TX_DROP_CFG_CH1", 0x12C, 0 },
2109 	{ "S_PACKETDROPS", 0, 4 },
2114 	{ "TP_TX_DROP_MODE", 0x12F, 0 },
2118 	{ "S_TXDROPMODECH0", 0, 1 },
2119 	{ "TP_DBG_ESIDE_PKT0", 0x130, 0 },
2127 	{ "S_ERXPLDEOPCNT", 0, 4 },
2128 	{ "TP_DBG_ESIDE_PKT1", 0x131, 0 },
2136 	{ "S_ERXPLDEOPCNT", 0, 4 },
2137 	{ "TP_DBG_ESIDE_PKT2", 0x132, 0 },
2145 	{ "S_ERXPLDEOPCNT", 0, 4 },
2146 	{ "TP_DBG_ESIDE_PKT3", 0x133, 0 },
2154 	{ "S_ERXPLDEOPCNT", 0, 4 },
2155 	{ "TP_DBG_ESIDE_FIFO0", 0x134, 0 },
2187 	{ "S_ERXFULL0", 0, 1 },
2188 	{ "TP_DBG_ESIDE_FIFO1", 0x135, 0 },
2220 	{ "S_ERXFULL2", 0, 1 },
2221 	{ "TP_DBG_ESIDE_DISP0", 0x136, 0 },
2243 	{ "S_TXFULL", 0, 1 },
2244 	{ "TP_DBG_ESIDE_DISP1", 0x137, 0 },
2266 	{ "S_TXFULL", 0, 1 },
2267 	{ "TP_MAC_MATCH_MAP0", 0x138, 0 },
2272 	{ "S_MAPWRITE", 0, 1 },
2273 	{ "TP_MAC_MATCH_MAP1", 0x139, 0 },
2275 	{ "S_MAPVALUERD", 0, 9 },
2276 	{ "TP_DBG_ESIDE_DISP2", 0x13A, 0 },
2298 	{ "S_TXFULL", 0, 1 },
2299 	{ "TP_DBG_ESIDE_DISP3", 0x13B, 0 },
2321 	{ "S_TXFULL", 0, 1 },
2322 	{ "TP_DBG_ESIDE_HDR0", 0x13C, 0 },
2330 	{ "S_CPLEOPCNT", 0, 4 },
2331 	{ "TP_DBG_ESIDE_HDR1", 0x13D, 0 },
2339 	{ "S_CPLEOPCNT", 0, 4 },
2340 	{ "TP_DBG_ESIDE_HDR2", 0x13E, 0 },
2348 	{ "S_CPLEOPCNT", 0, 4 },
2349 	{ "TP_DBG_ESIDE_HDR3", 0x13F, 0 },
2357 	{ "S_CPLEOPCNT", 0, 4 },
2358 	{ "TP_VLAN_PRI_MAP", 0x140, 0 },
2371 	{ "S_FCOE", 0, 1 },
2372 	{ "TP_INGRESS_CONFIG", 0x141, 0 },
2382 	{ "S_IPV6_EXT_HDR_SKIP", 0, 8 },
2383 	{ "TP_TX_DROP_CFG_CH2", 0x142, 0 },
2387 	{ "S_PACKETDROPS", 0, 4 },
2388 	{ "TP_TX_DROP_CFG_CH3", 0x143, 0 },
2392 	{ "S_PACKETDROPS", 0, 4 },
2397 	{ "TP_INGRESS_CONFIG2", 0x145, 0 },
2402 	{ "S_TNL_PLD_FILTER_OFFSET", 0, 10 },
2403 	{ "TP_EHDR_CONFIG_LO", 0x146, 0 },
2407 	{ "S_TCPLIMIT", 0, 8 },
2408 	{ "TP_EHDR_CONFIG_HI", 0x147, 0 },
2412 	{ "S_TCPLIMIT", 0, 8 },
2413 	{ "TP_DBG_ESIDE_INT", 0x148, 0 },
2427 	{ "S_TCPOPTTXFULL", 0, 1 },
2428 	{ "TP_DBG_ESIDE_DEMUX", 0x149, 0 },
2436 	{ "S_ETCPOPDONE", 0, 4 },
2437 	{ "TP_DBG_ESIDE_IN0", 0x14A, 0 },
2469 	{ "S_RX_PKT_ATTR_DRDY", 0, 1 },
2470 	{ "TP_DBG_ESIDE_IN1", 0x14B, 0 },
2502 	{ "S_RX_PKT_ATTR_DRDY", 0, 1 },
2503 	{ "TP_DBG_ESIDE_IN2", 0x14C, 0 },
2535 	{ "S_RX_PKT_ATTR_DRDY", 0, 1 },
2536 	{ "TP_DBG_ESIDE_IN3", 0x14D, 0 },
2568 	{ "S_RX_PKT_ATTR_DRDY", 0, 1 },
2569 	{ "TP_DBG_ESIDE_FRM", 0x14E, 0 },
2577 	{ "S_ERXSIZEERROR0", 0, 4 },
2578 	{ "TP_DBG_ESIDE_DRP", 0x14F, 0 },
2582 	{ "S_RXDROP0", 0, 8 },
2583 	{ "TP_DBG_ESIDE_TX", 0x150, 0 },
2585 	{ "S_ETXFULL", 0, 4 },
2586 	{ "TP_ESIDE_SVID_MASK", 0x151, 0 },
2587 	{ "TP_ESIDE_DVID_MASK", 0x152, 0 },
2588 	{ "TP_ESIDE_ALIGN_MASK", 0x153, 0 },
2592 	{ "S_SVID_ID_OFFSET", 0, 8 },
2593 	{ "TP_DBG_ESIDE_OP", 0x154, 0 },
2613 	{ "S_OPT_PARSER_OTK_STATE_CHANNEL3", 0, 2 },
2614 	{ "TP_DBG_ESIDE_OP_ALT", 0x155, 0 },
2626 	{ "S_OPT_PARSER_PSTATE_ERRNO_CHANNEL3", 0, 5 },
2627 	{ "TP_DBG_ESIDE_OP_BUSY", 0x156, 0 },
2631 	{ "S_OPT_PARSER_BUSY_VEC_CHANNEL0", 0, 8 },
2632 	{ "TP_DBG_ESIDE_OP_COOKIE", 0x157, 0 },
2636 	{ "S_OPT_PARSER_COOKIE_CHANNEL0", 0, 8 },
2641 	{ "TP_DBG_CSIDE_RX0", 0x230, 0 },
2649 	{ "S_CRXCPLEOPCNT", 0, 4 },
2650 	{ "TP_DBG_CSIDE_RX1", 0x231, 0 },
2658 	{ "S_CRXCPLEOPCNT", 0, 4 },
2659 	{ "TP_DBG_CSIDE_RX2", 0x232, 0 },
2667 	{ "S_CRXCPLEOPCNT", 0, 4 },
2668 	{ "TP_DBG_CSIDE_RX3", 0x233, 0 },
2676 	{ "S_CRXCPLEOPCNT", 0, 4 },
2677 	{ "TP_DBG_CSIDE_TX0", 0x234, 0 },
2685 	{ "S_TXCPLEOPCNT", 0, 4 },
2686 	{ "TP_DBG_CSIDE_TX1", 0x235, 0 },
2694 	{ "S_TXCPLEOPCNT", 0, 4 },
2695 	{ "TP_DBG_CSIDE_TX2", 0x236, 0 },
2703 	{ "S_TXCPLEOPCNT", 0, 4 },
2704 	{ "TP_DBG_CSIDE_TX3", 0x237, 0 },
2712 	{ "S_TXCPLEOPCNT", 0, 4 },
2713 	{ "TP_DBG_CSIDE_FIFO0", 0x238, 0 },
2745 	{ "S_CPL5_TXFULL0", 0, 1 },
2746 	{ "TP_DBG_CSIDE_FIFO1", 0x239, 0 },
2778 	{ "S_CPL5_TXFULL2", 0, 1 },
2779 	{ "TP_DBG_CSIDE_DISP0", 0x23A, 0 },
2796 	{ "S_TXFULL2X", 0, 1 },
2797 	{ "TP_DBG_CSIDE_DISP1", 0x23B, 0 },
2814 	{ "S_TXFULL2X", 0, 1 },
2815 	{ "TP_DBG_CSIDE_DDP0", 0x23C, 0 },
2823 	{ "S_DDPMSGLATEST0", 0, 4 },
2824 	{ "TP_DBG_CSIDE_DDP1", 0x23D, 0 },
2832 	{ "S_DDPMSGLATEST0", 0, 4 },
2833 	{ "TP_DBG_CSIDE_FRM", 0x23E, 0 },
2840 	{ "S_CPRSERROR", 0, 4 },
2841 	{ "TP_DBG_CSIDE_INT", 0x23F, 0 },
2855 	{ "S_PLD2X_TXAFULL", 0, 4 },
2856 	{ "TP_CHDR_CONFIG", 0x240, 0 },
2860 	{ "S_CH0LOW", 0, 8 },
2861 	{ "TP_UTRN_CONFIG", 0x241, 0 },
2864 	{ "S_CH0FIFOLIMIT", 0, 8 },
2865 	{ "TP_CDSP_CONFIG", 0x242, 0 },
2875 	{ "S_WRITEZEROOP", 0, 4 },
2876 	{ "TP_CSPI_POWER", 0x243, 0 },
2884 	{ "S_SLEEPREQUTRN", 0, 1 },
2885 	{ "TP_TRC_CONFIG", 0x244, 0 },
2887 	{ "S_TRCCH", 0, 1 },
2888 	{ "TP_TAG_CONFIG", 0x245, 0 },
2890 	{ "S_VLANTYPE", 0, 16 },
2891 	{ "TP_DBG_CSIDE_PRS", 0x246, 0 },
2911 	{ "S_CPRSSTATE0", 0, 4 },
2912 	{ "TP_DBG_CSIDE_DEMUX", 0x247, 0 },
2920 	{ "S_CTXPKTCSUMDONE", 0, 4 },
2921 	{ "TP_DBG_CSIDE_ARBIT", 0x248, 0 },
2953 	{ "S_ERRVALID0", 0, 1 },
2958 	{ "TP_DBG_CSIDE_TRACE_CNT", 0x24a, 0 },
2963 	{ "TrcPktLen", 0, 8 },
2964 	{ "TP_DBG_CSIDE_TRACE_RSS", 0x24b, 0 },
2965 	{ "TP_VLN_CONFIG", 0x24c, 0 },
2967 	{ "EthTypeVlan", 0, 16 },
2972 	{ "TP_DBG_CSIDE_RX0", 0x230, 0 },
2980 	{ "S_CRXCPLEOPCNT", 0, 4 },
2981 	{ "TP_DBG_CSIDE_RX1", 0x231, 0 },
2989 	{ "S_CRXCPLEOPCNT", 0, 4 },
2990 	{ "TP_DBG_CSIDE_RX2", 0x232, 0 },
2998 	{ "S_CRXCPLEOPCNT", 0, 4 },
2999 	{ "TP_DBG_CSIDE_RX3", 0x233, 0 },
3007 	{ "S_CRXCPLEOPCNT", 0, 4 },
3008 	{ "TP_DBG_CSIDE_TX0", 0x234, 0 },
3016 	{ "S_TXCPLEOPCNT", 0, 4 },
3017 	{ "TP_DBG_CSIDE_TX1", 0x235, 0 },
3025 	{ "S_TXCPLEOPCNT", 0, 4 },
3026 	{ "TP_DBG_CSIDE_TX2", 0x236, 0 },
3034 	{ "S_TXCPLEOPCNT", 0, 4 },
3035 	{ "TP_DBG_CSIDE_TX3", 0x237, 0 },
3043 	{ "S_TXCPLEOPCNT", 0, 4 },
3044 	{ "TP_DBG_CSIDE_FIFO0", 0x238, 0 },
3076 	{ "S_CPL5_TXFULL0", 0, 1 },
3077 	{ "TP_DBG_CSIDE_FIFO1", 0x239, 0 },
3109 	{ "S_CPL5_TXFULL2", 0, 1 },
3110 	{ "TP_DBG_CSIDE_DISP0", 0x23A, 0 },
3127 	{ "S_TXFULL2X", 0, 1 },
3128 	{ "TP_DBG_CSIDE_DISP1", 0x23B, 0 },
3145 	{ "S_TXFULL2X", 0, 1 },
3146 	{ "TP_DBG_CSIDE_DDP0", 0x23C, 0 },
3154 	{ "S_DDPMSGLATEST0", 0, 4 },
3155 	{ "TP_DBG_CSIDE_DDP1", 0x23D, 0 },
3163 	{ "S_DDPMSGLATEST0", 0, 4 },
3164 	{ "TP_DBG_CSIDE_FRM", 0x23E, 0 },
3171 	{ "S_CPRSERROR", 0, 4 },
3172 	{ "TP_DBG_CSIDE_INT", 0x23F, 0 },
3186 	{ "S_PLD2X_TXAFULL", 0, 4 },
3187 	{ "TP_CHDR_CONFIG", 0x240, 0 },
3191 	{ "S_CH0LOW", 0, 8 },
3192 	{ "TP_UTRN_CONFIG", 0x241, 0 },
3195 	{ "S_CH0FIFOLIMIT", 0, 8 },
3196 	{ "TP_CDSP_CONFIG", 0x242, 0 },
3204 	{ "S_WRITEZEROOP", 0, 4 },
3205 	{ "TP_CSPI_POWER", 0x243, 0 },
3213 	{ "S_SLEEPREQUTRN", 0, 1 },
3214 	{ "TP_TRC_CONFIG", 0x244, 0 },
3216 	{ "S_TRCCH", 0, 1 },
3217 	{ "TP_TAG_CONFIG", 0x245, 0 },
3219 	{ "S_VLANTYPE", 0, 16 },
3220 	{ "TP_DBG_CSIDE_PRS", 0x246, 0 },
3240 	{ "S_CPRSSTATE0", 0, 4 },
3241 	{ "TP_DBG_CSIDE_DEMUX", 0x247, 0 },
3249 	{ "S_CTXPKTCSUMDONE", 0, 4 },
3250 	{ "TP_DBG_CSIDE_ARBIT", 0x248, 0 },
3282 	{ "S_ERRVALID0", 0, 1 },
3287 	{ "TP_FIFO_CONFIG", 0x8C0, 0 },
3295 	{ "S_STROBE0", 0, 1 },
3300 	{ "TP_FIFO_CONFIG", 0x8C0, 0 },
3308 	{ "S_STROBE0", 0, 1 },
3313 	{ "PCIE_PDEBUG_REG_0x0", 0x00, 0 },
3314 	{ "PCIE_PDEBUG_REG_0x1", 0x01, 0 },
3315 	{ "PCIE_PDEBUG_REG_0x2", 0X02, 0 },
3327 	{ "req_ctl_rd_ch0_wait_for_fifo_data", 0, 1 },
3328 	{ "PCIE_PDEBUG_REG_0x3", 0X03, 0 },
3340 	{ "req_ctl_rd_ch1_wait_for_fifo_data", 0, 1 },
3341 	{ "PCIE_PDEBUG_REG_0x4", 0X04, 0 },
3353 	{ "req_ctl_rd_ch2_wait_for_fifo_data", 0, 1},
3354 	{ "PCIE_PDEBUG_REG_0x5", 0x05, 0 },
3366 	{ "req_ctl_rd_ch3_wait_for_fifo_data", 0, 1 },
3367 	{ "PCIE_PDEBUG_REG_0x6", 0x06, 0 },
3379 	{ "req_ctl_rd_ch4_wait_for_fifo_data", 0, 1 },
3380 	{ "PCIE_PDEBUG_REG_0x7", 0x07, 0 },
3392 	{ "req_ctl_rd_ch5_wait_for_fifo_data", 0, 1 },
3393 	{ "PCIE_PDEBUG_REG_0x8", 0x08, 0 },
3405 	{ "req_ctl_rd_ch6_wait_for_fifo_data", 0, 1 },
3406 	{ "PCIE_PDEBUG_REG_0x9", 0x09, 0 },
3418 	{ "req_ctl_rd_ch7_wait_for_fifo_data", 0, 1 },
3419 	{ "PCIE_PDEBUG_REG_0xa", 0x0a, 0 },
3427 	{ "req_ctl_wr_ch0_wait_for_fifo_data", 0, 1 },
3428 	{ "PCIE_PDEBUG_REG_0xb", 0x0b, 0 },
3436 	{ "req_ctl_wr_ch1_wait_for_fifo_data", 0, 1 },
3437 	{ "PCIE_PDEBUG_REG_0xc", 0x0c, 0 },
3445 	{ "req_ctl_wr_ch2_wait_for_fifo_data", 0, 1 },
3446 	{ "PCIE_PDEBUG_REG_0xd", 0x0d, 0 },
3454 	{ "req_ctl_wr_ch3_wait_for_fifo_data", 0, 1 },
3455 	{ "PCIE_PDEBUG_REG_0xe", 0x0e, 0 },
3463 	{ "req_ctl_wr_ch4_wait_for_fifo_data", 0, 1 },
3464 	{ "PCIE_PDEBUG_REG_0xf", 0xf, 0 },
3465 	{ "PCIE_PDEBUG_REG_0x10", 0x10, 0 },
3471 	{ "pipe0_tx0_data_6_0", 0 , 7 },
3472 	{ "PCIE_PDEBUG_REG_0x11", 0x11, 0 },
3478 	{ "pipe0_tx0_data_14_8", 0, 7 },
3479 	{ "PCIE_PDEBUG_REG_0x12", 0x12, 0 },
3485 	{ "pipe0_tx4_data_6_0", 0, 7 },
3486 	{ "PCIE_PDEBUG_REG_0x13", 0x13, 0 },
3492 	{ "pipe0_tx4_data_14_8", 0, 7 },
3493 	{ "PCIE_PDEBUG_REG_0x14", 0x14, 0 },
3499 	{ "pipe0_rx0_valid2_14", 0, 7 },
3500 	{ "PCIE_PDEBUG_REG_0x15", 0x15, 0 },
3506 	{ "pipe0_rx0_valid2+15", 0, 7 },
3507 	{ "PCIE_PDEBUG_REG_0x16", 0x16, 0 },
3513 	{ "pipe0_rx4_valid2_16", 0, 7 },
3514 	{ "PCIE_PDEBUG_REG_0x17", 0x17, 0 },
3520 	{ "pipe0_rx4_valid2_17", 0, 7 },
3521 	{ "PCIE_PDEBUG_REG_0x18", 0x18, 0 },
3537 	{ "pipe0_rx0_status", 0, 3 },
3538 	{ "PCIE_PDEBUG_REG_0x19", 0x19, 0 },
3570 	{ "pipe0_rx0_elecidle", 0, 1 },
3571 	{ "PCIE_PDEBUG_REG_0x1a", 0x1a , 0 },
3584 	{ "phy_mac_phystatus", 0, 8 },
3585 	{ "PCIE_PDEBUG_REG_0x1b", 0x1b, 0 },
3609 	{ "pipe0_rx0_syncheader", 0, 2 },
3610 	{ "PCIE_PDEBUG_REG_0x1c", 0x1c, 0 },
3616 	{ "AI", 0, 8 },
3617 	{ "PCIE_PDEBUG_REG_0x1d", 0x1d, 0 },
3624 	{ "PIO_INTXClr", 0, 8 },
3625 	{ "PCIE_PDEBUG_REG_0x1e", 0x1e, 0 },
3632 	{ "PLI_ReqRdVld", 0, 1 },
3633 	{ "PCIE_PDEBUG_REG_0x1f", 0x1f, 0 },
3634 	{ "PLI_ReqVld", 0, 32 },
3635 	{ "PCIE_PDEBUG_REG_0x20", 0x20, 0 },
3636 	{"PLI_RspVld", 0, 32 },
3641 	{ "PCIE_PDEBUG_REG_0x21", 0x21, 0 },
3646 	{ "PLI_ReqRdVld", 0, 1 },
3647 	{ "PCIE_PDEBUG_REG_0x22", 0x22, 0 },
3660 	{ "GntDI", 0, 1 },
3661 	{ "PCIE_PDEBUG_REG_0x23", 0x23, 0 },
3670 	{ "DI_ReqWrEn3", 0, 1 },
3671 	{ "PCIE_PDEBUG_REG_0x24", 0x24, 0 },
3672 	{ "ven_msi_req_24", 0, 32 },
3673 	{ "PCIE_PDEBUG_REG_0x25", 0x25, 0 },
3674 	{ "ven_msi_req", 0, 32 },
3675 	{ "PCIE_PDEBUG_REG_0x26", 0x26, 0 },
3676 	{ "ven_msi_req", 0, 32 },
3677 	{ "PCIE_PDEBUG_REG_0x27", 0x27, 0 },
3683 	{ "GntSI", 0, 7 },
3684 	{ "PCIE_PDEBUG_REG_0x28", 0x28, 0 },
3700 	{ "ven_msi_req6", 0, 1 },
3701 	{ "PCIE_PDEBUG_REG_0x29", 0x29, 0 },
3711 	{ "TRGT1_ReqDataVld0", 0, 1 },
3712 	{ "PCIE_PDEBUG_REG_0x2a", 0x2a, 0 },
3713 	{ "TRGT1_ReqDataVld", 0, 32 },
3714 	{ "PCIE_PDEBUG_REG_0x2b", 0x2b, 0 },
3725 	{ "radm_trgt1_hv_2b", 0, 1 },
3726 	{ "PCIE_PDEBUG_REG_0x2c", 0x2c, 0 },
3743 	{ "radm_trgt1_ecrc_err_2c", 0, 1 },
3744 	{ "PCIE_PDEBUG_REG_0x2d", 0x2d, 0 },
3757 	{ "radm_trgt1_WrCnt", 0, 4 },
3758 	{ "PCIE_PDEBUG_REG_0x2e", 0x2e, 0 },
3769 	{ "ALIN_ReqDataVlda", 0, 1 },
3770 	{ "PCIE_PDEBUG_REG_0x2f", 0x2f, 0 },
3771 	{"ALIN_ReqDataVld", 0, 32 },
3772 	{ "PCIE_PDEBUG_REG_0x30", 0x30, 0 },
3783 	{ "ALIND_ReqWrDataVld5", 0, 1 },
3784 	{ "PCIE_PDEBUG_REG_0x31", 0x31, 0 },
3785 	{ "ALIND_ReqWrDataVld", 0, 32 },
3786 	{ "PCIE_PDEBUG_REG_0x32", 0x32, 0 },
3787 	{ "ALIND_ReqWrDataVld", 0, 32 },
3788 	{ "PCIE_PDEBUG_REG_0x33", 0x33, 0 },
3789 	{ "ALIND_ReqWrDataVld", 0, 32 },
3790 	{ "PCIE_PDEBUG_REG_0x34", 0x34, 0 },
3791 	{ "ALIND_ReqWrDataVld", 0, 32 },
3792 	{ "PCIE_PDEBUG_REG_0x35", 0x35, 0 },
3809 	{ "MPIO_WrVld4", 0, 4 },
3810 	{ "PCIE_PDEBUG_REG_0x36", 0x36, 0 },
3811 	{ "MPIO_WrVld", 0, 32 },
3812 	{ "PCIE_PDEBUG_REG_0x37", 0x37, 0},
3813 	{ "MPIO_WrVld", 0, 32 },
3814 	{ "PCIE_PDEBUG_REG_0x38", 0x38, 0 },
3815 	{ "MPIO_WrVld", 0, 32 },
3816 	{ "PCIE_PDEBUG_REG_0x39", 0x39, 0 },
3817 	{ "MPIO_WrVld", 0, 32 },
3818 	{ "PCIE_PDEBUG_REG_0x3a", 0x3a, 0 },
3823 	{ "client0_tlp_byte_len", 0, 13 },
3824 	{ "PCIE_PDEBUG_REG_0x3b", 0x3b, 0 },
3838 	{ "client0_tlp_tid", 0, 8 },
3839 	{ "PCIE_PDEBUG_REG_0x3c", 0x3c, 0 },
3851 	{ "client0_tlp_hv", 0, 7 },
3852 	{ "PCIE_PDEBUG_REG_0x3D", 0x3d, 0 },
3853 	{ "pdebug_0x3D", 0, 32 },
3854 	{ "PCIE_PDEBUG_REG_0x3E", 0x3e, 0 },
3855 	{ "pdebug_0x3E", 0, 32 },
3856 	{ "PCIE_PDEBUG_REG_0x3F", 0x3f, 0 },
3857 	{ "pdebug_0x3F", 0, 32 },
3858 	{ "PCIE_PDEBUG_REG_0x40", 0x40, 0 },
3859 	{ "pdebug_0x40", 0, 32 },
3864 	{ "PCIE_PDEBUG_REG_0x41", 0x41, 0 },
3865 	{ "pdebug_0x41", 0, 32 },
3866 	{ "PCIE_PDEBUG_REG_0x42", 0x42, 0 },
3867 	{ "pdebug_0x42", 0, 32 },
3868 	{ "PCIE_PDEBUG_REG_0x43", 0x43, 0 },
3869 	{ "pdebug_0x43", 0, 32 },
3870 	{ "PCIE_PDEBUG_REG_0x44", 0x44, 0 },
3871 	{ "pdebug_0x44", 0, 32 },
3872 	{ "PCIE_PDEBUG_REG_0x45", 0x45, 0 },
3873 	{ "pdebug_0x45", 0, 32 },
3874 	{ "PCIE_PDEBUG_REG_0x46", 0x46, 0 },
3875 	{ "pdebug_0x46", 0, 32 },
3876 	{ "PCIE_PDEBUG_REG_0x47", 0x47, 0 },
3877 	{ "pdebug_0x47", 0, 32 },
3878 	{ "PCIE_PDEBUG_REG_0x48", 0x48, 0 },
3879 	{ "pdebug_0x48", 0, 32 },
3880 	{ "PCIE_PDEBUG_REG_0x49", 0x49, 0 },
3881 	{ "pdebug_0x49", 0, 32 },
3882 	{ "PCIE_PDEBUG_REG_0x4a", 0x4a, 0 },
3883 	{ "pdebug_0x4A", 0, 32 },
3884 	{ "PCIE_PDEBUG_REG_0x4b", 0x4b, 0 },
3885 	{ "pdebug_0xaB", 0, 32 },
3886 	{ "PCIE_PDEBUG_REG_0x4c", 0x4c, 0 },
3887 	{ "pdebug_0x4C", 0, 32 },
3888 	{ "PCIE_PDEBUG_REG_0x4d", 0x4d, 0 },
3889 	{ "pdebug_0x4D", 0, 32 },
3890 	{ "PCIE_PDEBUG_REG_0x4e", 0x4e, 0 },
3891 	{ "pdebug_0x4E", 0, 32 },
3892 	{ "PCIE_PDEBUG_REG_0x4f", 0x4f, 0 },
3893 	{ "pdebug_0x4F", 0, 32 },
3894 	{ "PCIE_PDEBUG_REG_0x50", 0x50, 0 },
3895 	{ "pdebug_0x50", 0, 32 },
3900 	{ "PCIE_CDEBUG_REG_0x0", 0x00, 0 },
3901 	{ "PCIE_CDEBUG_REG_0x1", 0x01, 0 },
3902 	{ "PCIE_CDEBUG_REG_0x2", 0x02, 0 },
3914 	{ "D_WrReqAFull", 0, 4 },
3915 	{ "PCIE_CDEBUG_REG_0x3", 0x03, 0 },
3925 	{ "C_ReqAFull", 0, 3 },
3926 	{ "PCIE_CDEBUG_REG_0x4", 0x04, 0 },
3934 	{ "H_ReqAFull", 0, 1 },
3935 	{ "PCIE_CDEBUG_REG_0x5", 0x05, 0 },
3940 	{ "ER_ReqVld5", 0, 1 },
3941 	{ "PCIE_CDEBUG_REG_0x6", 0x06, 0 },
3946 	{ "PL_BAR2_ReqVld4", 0, 1},
3947 	{ "PCIE_CDEBUG_REG_0x7", 0x07, 0 },
3948 	{"PL_BAR2_ReqVld_7", 0, 32 },
3949 	{ "PCIE_CDEBUG_REG_0x8", 0x08, 0 },
3950 	{"PL_BAR2_ReqVld_8", 0, 32 },
3951 	{ "PCIE_CDEBUG_REG_0x9", 0x09, 0 },
3952 	{"PL_BAR2_ReqVld_9", 0, 32 },
3953 	{ "PCIE_CDEBUG_REG_0xa", 0x0a, 0 },
3961 	{ "VPD_ReqVld6", 0, 1 },
3962 	{ "PCIE_CDEBUG_REG_0xb", 0x0b, 0 },
3972 	{ "MA_ReqAddrVld7", 0, 1 },
3973 	{ "PCIE_CDEBUG_REG_0xc", 0x0c, 0 },
3974 	{ "MA_ReqAddrVld_c", 0, 32 },
3975 	{ "PCIE_CDEBUG_REG_0xd", 0x0d, 0 },
3976 	{ "MA_ReqAddrVld_d", 0, 32 },
3977 	{ "PCIE_CDEBUG_REG_0xe", 0x0e, 0 },
3978 	{ "MA_ReqAddrVld_e", 0, 32 },
3979 	{ "PCIE_CDEBUG_REG_0xf", 0x0f, 0 },
3980 	{ "MA_ReqAddrVld_f", 0, 32 },
3981 	{ "PCIE_CDEBUG_REG_0x10", 0x10, 0 },
3982 	{ "MA_ReqAddrVld_10", 0, 32 },
3983 	{ "PCIE_CDEBUG_REG_0x11", 0x11, 0 },
3984 	{ "MA_ReqAddrVld_11", 0, 32 },
3985 	{ "PCIE_CDEBUG_REG_0x12", 0x12, 0 },
3986 	{ "MA_ReqAddrVld_12", 0, 32 },
3987 	{ "PCIE_CDEBUG_REG_0x13", 0x13, 0 },
3988 	{ "MA_ReqAddrVld_13", 0, 32 },
3989 	{ "PCIE_CDEBUG_REG_0x14", 0x14, 0 },
3990 	{ "MA_ReqAddrVld_14", 0, 32 },
3991 	{ "PCIE_CDEBUG_REG_0x15", 0x15, 0 },
4002 	{ "PLM_ReqVldb", 0, 1 },
4003 	{ "PCIE_CDEBUG_REG_0x16", 0x16, 0 },
4004 	{ "PLM_RspVld", 0, 32 },
4005 	{ "PCIE_CDEBUG_REG_0x17", 0x17, 0 },
4006 	{ "cdebug_0x17", 0, 32 },
4007 	{ "PCIE_CDEBUG_REG_0x18", 0x18, 0 },
4008 	{ "cdebug_0x18", 0, 32 },
4009 	{ "PCIE_CDEBUG_REG_0x19", 0x19, 0 },
4010 	{ "cdebug_0x19", 0, 32 },
4011 	{ "PCIE_CDEBUG_REG_0x1A", 0x1a, 0 },
4012 	{ "cdebug_0x1A", 0, 32 },
4013 	{ "PCIE_CDEBUG_REG_0x1B", 0x1b, 0 },
4014 	{ "cdebug_0x1B", 0, 32 },
4015 	{ "PCIE_CDEBUG_REG_0x1C", 0x1c, 0 },
4016 	{ "cdebug_0x1C", 0, 32 },
4017 	{ "PCIE_CDEBUG_REG_0x1D", 0x1d, 0 },
4018 	{ "cdebug_0x1D", 0, 32 },
4019 	{ "PCIE_CDEBUG_REG_0x1E", 0x1e, 0 },
4020 	{ "cdebug_0x1E", 0, 32 },
4021 	{ "PCIE_CDEBUG_REG_0x1F", 0x1f, 0 },
4022 	{ "cdebug_0x1F", 0, 32 },
4023 	{ "PCIE_CDEBUG_REG_0x20", 0x20, 0 },
4024 	{ "cdebug_0x20", 0, 32 },
4029 	{ "PCIE_CDEBUG_REG_0x21", 0x21, 0 },
4030 	{ "cdebug_0x21", 0, 32 },
4031 	{ "PCIE_CDEBUG_REG_0x22", 0x22, 0 },
4032 	{ "cdebug_0x22", 0, 32 },
4033 	{ "PCIE_CDEBUG_REG_0x23", 0x23, 0 },
4034 	{ "cdebug_0x23", 0, 32 },
4035 	{ "PCIE_CDEBUG_REG_0x24", 0x24, 0 },
4036 	{ "cdebug_0x24", 0, 32 },
4037 	{ "PCIE_CDEBUG_REG_0x25", 0x25, 0 },
4038 	{ "cdebug_0x25", 0, 32 },
4039 	{ "PCIE_CDEBUG_REG_0x26", 0x26, 0 },
4040 	{ "cdebug_0x26", 0, 32 },
4041 	{ "PCIE_CDEBUG_REG_0x27", 0x27, 0 },
4042 	{ "cdebug_0x27", 0, 32 },
4043 	{ "PCIE_CDEBUG_REG_0x28", 0x28, 0 },
4044 	{ "cdebug_0x28", 0, 32 },
4045 	{ "PCIE_CDEBUG_REG_0x29", 0x29, 0 },
4046 	{ "cdebug_0x29", 0, 32 },
4047 	{ "PCIE_CDEBUG_REG_0x2a", 0x2a, 0 },
4048 	{ "cdebug_0x2A", 0, 32 },
4049 	{ "PCIE_CDEBUG_REG_0x2b", 0x2b, 0 },
4050 	{ "cdebug_0x2B", 0, 32 },
4051 	{ "PCIE_CDEBUG_REG_0x2c", 0x2c, 0 },
4052 	{ "cdebug_0x2C", 0, 32 },
4053 	{ "PCIE_CDEBUG_REG_0x2d", 0x2d, 0 },
4054 	{ "cdebug_0x2D", 0, 32 },
4055 	{ "PCIE_CDEBUG_REG_0x2e", 0x2e, 0 },
4056 	{ "cdebug_0x2E", 0, 32 },
4057 	{ "PCIE_CDEBUG_REG_0x2f", 0x2f, 0 },
4058 	{ "cdebug_0x2F", 0, 32 },
4059 	{ "PCIE_CDEBUG_REG_0x30", 0x30, 0 },
4060 	{ "cdebug_0x30", 0, 32 },
4061 	{ "PCIE_CDEBUG_REG_0x31", 0x31, 0 },
4062 	{ "cdebug_0x31", 0, 32 },
4063 	{ "PCIE_CDEBUG_REG_0x32", 0x32, 0 },
4064 	{ "cdebug_0x32", 0, 32 },
4065 	{ "PCIE_CDEBUG_REG_0x33", 0x33, 0 },
4066 	{ "cdebug_0x33", 0, 32 },
4067 	{ "PCIE_CDEBUG_REG_0x34", 0x34, 0 },
4068 	{ "cdebug_0x34", 0, 32 },
4069 	{ "PCIE_CDEBUG_REG_0x35", 0x35, 0 },
4070 	{ "cdebug_0x35", 0, 32 },
4071 	{ "PCIE_CDEBUG_REG_0x36", 0x36, 0 },
4072 	{ "cdebug_0x36", 0, 32 },
4073 	{ "PCIE_CDEBUG_REG_0x37", 0x37, 0 },
4074 	{ "cdebug_0x37", 0, 32 },
4079 	{ "PM_TX_ISPI_DBG_4B_DATA0", 0x10000, 0 },
4080 	{ "ispi_dbg_data", 0, 32 },
4081 	{ "PM_RX_ISPI_DBG_4B_DATA1", 0x10001, 0 },
4082 	{ "ispi_dbg_data", 0, 32 },
4083 	{ "PM_RX_ISPI_DBG_4B_DATA2", 0x10002, 0 },
4084 	{ "ispi_dbg_data", 0, 32 },
4085 	{ "PM_RX_ISPI_DBG_4B_DATA3", 0x10003, 0 },
4086 	{ "ispi_dbg_data", 0, 32 },
4087 	{ "PM_RX_ISPI_DBG_4B_DATA4", 0x10004, 0 },
4088 	{ "ispi_dbg_data", 0, 32 },
4089 	{ "PM_RX_ISPI_DBG_4B_DATA5", 0x10005, 0 },
4090 	{ "ispi_dbg_data", 0, 32 },
4091 	{ "PM_RX_ISPI_DBG_4B_DATA6", 0x10006, 0 },
4092 	{ "ispi_dbg_data", 0, 32 },
4093 	{ "PM_RX_ISPI_DBG_4B_DATA7", 0x10007, 0 },
4094 	{ "ispi_dbg_data", 0, 32 },
4095 	{ "PM_RX_ISPI_DBG_4B_DATA8", 0x10008, 0 },
4096 	{ "ispi_dbg_data", 0, 32 },
4097 	{ "PM_RX_OSPI_DBG_4B_DATA0", 0x10009, 0 },
4098 	{ "ospi_dbg_data", 0, 32 },
4099 	{ "PM_RX_OSPI_DBG_4B_DATA1", 0x1000a, 0 },
4100 	{ "ospi_dbg_data", 0, 32 },
4101 	{ "PM_RX_OSPI_DBG_4B_DATA2", 0x1000b, 0 },
4102 	{ "ospi_dbg_data", 0, 32 },
4103 	{ "PM_RX_OSPI_DBG_4B_DATA3", 0x1000c, 0 },
4104 	{ "ospi_dbg_data", 0, 32 },
4105 	{ "PM_RX_OSPI_DBG_4B_DATA4", 0x1000d, 0 },
4106 	{ "ospi_dbg_data", 0, 32 },
4107 	{ "PM_RX_OSPI_DBG_4B_DATA5", 0x1000e, 0 },
4108 	{ "ospi_dbg_data", 0, 32 },
4109 	{ "PM_RX_OSPI_DBG_4B_DATA6", 0x1000f, 0 },
4110 	{ "ospi_dbg_data", 0, 32 },
4111 	{ "PM_RX_OSPI_DBG_4B_DATA7", 0x10010, 0 },
4112 	{ "ospi_dbg_data", 0, 32 },
4113 	{ "PM_RX_OSPI_DBG_4B_DATA8", 0x10011, 0 },
4114 	{ "ospi_dbg_data", 0, 32 },
4115 	{ "PM_RX_OSPI_DBG_4B_DATA9", 0x10012, 0 },
4116 	{ "ospi_dbg_data", 0, 32 },
4117 	{ "PM_RX_DBG_STAT_MSB", 0x10013, 0 },
4118 	{ "stat_msb", 0, 32 },
4119 	{ "PM_RX_DBG_STAT_LSB", 0x10014, 0 },
4120 	{ "stat_lsb", 0, 32 },
4121 	{ "PM_RX_DBG_RSVD_FLIT_CNT", 0x10015, 0 },
4125 	{ "ospi_rsvd_flit", 0, 4 },
4126 	{ "PM_RX_SDC_EN", 0x10016, 0 },
4127 	{ "sdc_en", 0, 1 },
4128 	{ "PM_RX_INOUT_FIFO_DBG_CHNL_SEL", 0x10017, 0 },
4132 	{ "chnl_0_sel", 0, 1 },
4133 	{ "PM_RX_INOUT_FIFO_DBG_WR", 0x10018, 0 },
4137 	{ "i_fifo_read", 0, 1 },
4138 	{ "PM_RX_INPUT_FIFO_STR_FWD_EN", 0x10019, 0 },
4139 	{ "ispi_str_fwd_en", 0, 1 },
4140 	{ "PM_RX_PRFTCH_ACROSS_BNDLE_EN", 0x1001a, 0 },
4141 	{ "prftch_across_bndle_en", 0, 1 },
4142 	{ "PM_RX_PRFTCH_WRR_ENABLE", 0x1001b, 0 },
4143 	{ "prftch_wrr_enable", 0, 1 },
4144 	{ "PM_RX_PRFTCH_WRR_MAX_DEFICIT_CNT", 0x1001c, 0 },
4146 	{ "chnl0_max_deficit_cnt", 0, 16 },
4147 	{ "PM_RX_FEATURE_EN", 0x1001d, 0 },
4148 	{ "pio_ch_deficit_ctl_en", 0, 1 },
4149 	{ "PM_RX_CH0_OSPI_DEFICIT_THRSHLD", 0x1001e, 0 },
4150 	{ "CH0_OSPI_DEFICIT_THRSHLD", 0, 12 },
4151 	{ "PM_RX_CH1_OSPI_DEFICIT_THRSHLD", 0x1001f, 0 },
4152 	{ "CH1_OSPI_DEFICIT_THRSHLD", 0, 12 },
4153 	{ "PM_RX_INT_CAUSE_MASK_HALT", 0x10020, 0 },
4154 	{ "INT_CAUSE_MASK", 0, 32 },
4159 	{ "PM_RX_DBG_STAT0", 0x10021, 0 },
4171 	{ "rx_pcmd_len", 0, 16 },
4172 	{ "PM_RX_DBG_STAT1", 0x10022, 0 },
4178 	{ "rx_PCMD0_bypass", 0, 1 },
4179 	{ "PM_RX_DBG_STAT2", 0x10023, 0 },
4185 	{ "rx_PCMD1_bypass", 0, 1 },
4186 	{ "PM_RX_DBG_STAT3", 0x10024, 0 },
4193 	{ "rx_sdc_drdy", 0, 1 },
4194 	{ "PM_RX_DBG_STAT4", 0x10025, 0 },
4204 	{ "rx_pcmd_res_rdy", 0, 2 },
4205 	{ "PM_RX_DBG_STAT5", 0x10026, 0 },
4217 	{ "rx_C_TxAFull", 0, 2 },
4218 	{ "PM_RX_DBG_STAT6", 0x10027, 0 },
4223 	{ "rx_M_ReqDataRdy", 0, 1 },
4224 	{ "PM_RX_DBG_STAT7", 0x10028, 0 },
4226 	{ "rx_pcmd0_free_cnt", 0, 7 },
4227 	{ "PM_RX_DBG_STAT8", 0x10029, 0 },
4235 	{ "rx_In_Sop_Cnt0", 0, 4 },
4236 	{ "PM_RX_DBG_STAT9", 0x1002a, 0 },
4244 	{ "rx_Out_Sop_Cnt0", 0, 4 },
4245 	{ "PM_RX_DBG_STAT10", 0x1002b, 0 },
4248 	{ "rx_ch0_deficit", 0, 12 },
4249 	{ "PM_RX_DBG_STAT11", 0x1002c, 0 },
4254 	{ "rx_bundle_len0", 0, 12 },
4259 	{ "PM_TX_ISPI_DBG_4B_DATA0", 0x10000, 0 },
4260 	{ "ispi_dbg_data", 0, 32 },
4261 	{ "PM_TX_ISPI_DBG_4B_DATA1", 0x10001, 0 },
4262 	{ "ispi_dbg_data", 0, 32 },
4263 	{ "PM_TX_ISPI_DBG_4B_DATA2", 0x10002, 0 },
4264 	{ "ispi_dbg_data", 0, 32 },
4265 	{ "PM_TX_ISPI_DBG_4B_DATA3", 0x10003, 0 },
4266 	{ "ispi_dbg_data", 0, 32 },
4267 	{ "PM_TX_ISPI_DBG_4B_DATA4", 0x10004, 0 },
4268 	{ "ispi_dbg_data", 0, 32 },
4269 	{ "PM_TX_ISPI_DBG_4B_DATA5", 0x10005, 0 },
4270 	{ "ispi_dbg_data", 0, 32 },
4271 	{ "PM_TX_ISPI_DBG_4B_DATA6", 0x10006, 0 },
4272 	{ "ispi_dbg_data", 0, 32 },
4273 	{ "PM_TX_ISPI_DBG_4B_DATA7", 0x10007, 0 },
4274 	{ "ispi_dbg_data", 0, 32 },
4275 	{ "PM_TX_ISPI_DBG_4B_DATA8", 0x10008, 0 },
4276 	{ "ispi_dbg_data", 0, 32 },
4277 	{ "PM_TX_OSPI_DBG_4B_DATA0", 0x10009, 0 },
4278 	{ "ospi_dbg_data", 0, 32 },
4279 	{ "PM_TX_OSPI_DBG_4B_DATA1", 0x1000a, 0 },
4280 	{ "ospi_dbg_data", 0, 32 },
4281 	{ "PM_TX_OSPI_DBG_4B_DATA2", 0x1000b, 0 },
4282 	{ "ospi_dbg_data", 0, 32 },
4283 	{ "PM_TX_OSPI_DBG_4B_DATA3", 0x1000c, 0 },
4284 	{ "ospi_dbg_data", 0, 32 },
4285 	{ "PM_TX_OSPI_DBG_4B_DATA4", 0x1000d, 0 },
4286 	{ "ospi_dbg_data", 0, 32 },
4287 	{ "PM_TX_OSPI_DBG_4B_DATA5", 0x1000e, 0 },
4288 	{ "ospi_dbg_data", 0, 32 },
4289 	{ "PM_TX_OSPI_DBG_4B_DATA6", 0x1000f, 0 },
4290 	{ "ospi_dbg_data", 0, 32 },
4291 	{ "PM_TX_OSPI_DBG_4B_DATA7", 0x10010, 0 },
4292 	{ "ospi_dbg_data", 0, 32 },
4293 	{ "PM_TX_OSPI_DBG_4B_DATA8", 0x10011, 0 },
4294 	{ "ospi_dbg_data", 0, 32 },
4295 	{ "PM_TX_OSPI_DBG_4B_DATA9", 0x10012, 0 },
4296 	{ "ospi_dbg_data", 0, 32 },
4297 	{ "PM_TX_OSPI_DBG_4B_DATA10", 0x10013, 0 },
4298 	{ "ospi_dbg_data", 0, 32 },
4299 	{ "PM_TX_OSPI_DBG_4B_DATA11", 0x10014, 0 },
4300 	{ "ospi_dbg_data", 0, 32 },
4301 	{ "PM_TX_OSPI_DBG_4B_DATA12", 0x10015, 0 },
4302 	{ "ospi_dbg_data", 0, 32 },
4303 	{ "PM_TX_OSPI_DBG_4B_DATA13", 0x10016, 0 },
4304 	{ "ospi_dbg_data", 0, 32 },
4305 	{ "PM_TX_OSPI_DBG_4B_DATA14", 0x10017, 0 },
4306 	{ "ospi_dbg_data", 0, 32 },
4307 	{ "PM_TX_OSPI_DBG_4B_DATA15", 0x10018, 0 },
4308 	{ "ospi_dbg_data", 0, 32 },
4309 	{ "PM_TX_OSPI_DBG_4B_DATA16", 0x10019, 0 },
4310 	{ "ospi_dbg_data", 0, 32 },
4311 	{ "PM_TX_DBG_STAT_MSB", 0x1001a, 0 },
4312 	{ "stat_msb", 0, 32 },
4313 	{ "PM_TX_DBG_STAT_LSB", 0x1001b, 0 },
4314 	{ "stat_lsb", 0, 32 },
4315 	{ "PM_TX_DBG_RSVD_FLIT_CNT", 0x1001c, 0 },
4319 	{ "ospi_rsvd_flit", 0, 4 },
4320 	{ "PM_TX_SDC_EN", 0x1001d, 0 },
4321 	{ "sdc_en", 0, 1 },
4322 	{ "PM_TX_INOUT_FIFO_DBG_CHNL_SEL", 0x1001e, 0 },
4326 	{ "chnl_0_sel", 0, 1 },
4327 	{ "PM_TX_INOUT_FIFO_DBG_WR", 0x1001f, 0 },
4331 	{ "i_fifo_read", 0, 1 },
4332 	{ "PM_TX_INPUT_FIFO_STR_FWD_EN", 0x10020, 0 },
4333 	{ "ispi_str_fwd_en", 0, 1 },
4338 	{ "PCIE_DEVID_VENID", 0x00, 0 },
4339 	{ "VendorID", 0, 16 },
4341 	{ "PCIE_STAT_CMD", 0x04, 0 },
4342 	{ "IOEnable", 0, 1 },
4362 	{ "PCIE_CCODE_REVID", 0x08, 0 },
4363 	{ "RevisionID", 0, 8, },
4365 	{ "PCIE_BIST_HDR_TMR_CLS", 0xc, 0 },
4366 	{ "CacheLineSize", 0, 8 },
4370 	{ "PCIE_BAR0", 0x10, 0 },
4371 	{ "MemSpaceInd", 0, 1 },
4375 	{ "PCIE_BAR1", 0x14, 0 },
4376 	{ "PCIE_BAR2", 0x18, 0 },
4377 	{ "MemSpaceInd", 0, 1 },
4381 	{ "PCIE_BAR3", 0x1c, 0 },
4382 	{ "PCIE_BAR4", 0x20, 0 },
4383 	{ "MemSpaceInd", 0, 1 },
4387 	{ "PCIE_BAR5", 0x24, 0 },
4388 	{ "PCIE_CIS", 0x28, 0 },
4389 	{ "PCIE_SSID_SSVENID", 0x2c, 0 },
4390 	{ "SSVenID", 0, 16 },
4392 	{ "PCIE_EXPROM", 0x30, 0 },
4393 	{ "ExpROMEn", 0, 1 },
4396 	{ "PCIE_CAP_PTR", 0x34, 0 },
4397 	{ "CapPtr", 0, 8 },
4399 	{ "PCIE_INT_LINE_PIN", 0x3c, 0 },
4400 	{ "IntLine", 0, 8 },
4403 	{ "PCIE_PM_CAP", 0x40, 0 },
4404 	{ "PMCapID", 0, 8 },
4414 	{ "PCIE_MSI_CAP", 0x50, 0 },
4415 	{ "MSICapID", 0, 8 },
4423 	{ "PCIE_MSI_ADDR", 0x54, 0 },
4424 	{ "Rsvd", 0, 2 },
4426 	{ "PCIE_MSI_UPR_ADDR", 0x58, 0 },
4427 	{ "MsgUprAddr", 0, 32 },
4428 	{ "PCIE_MSI_DATA", 0x5c, 0 },
4429 	{ "MsgData", 0, 16 },
4431 	{ "PCIE_MSI_MASK", 0x60, 0 },
4432 	{ "MSIMask", 0, 32 },
4433 	{ "PCIE_MSI_PND", 0x64, 0 },
4434 	{ "MSIPnd", 0, 32 },
4435 	{ "PCIE_PCIE_CAP", 0x70, 0 },
4436 	{ "PCIECapID", 0, 8 },
4443 	{ "PCIE_DEV_CAP", 0x74, 0 },
4444 	{ "MaxPyldSzSup", 0, 3 },
4456 	{ "PCIE_DEV_STAT_CNTL", 0x78, 0 },
4457 	{ "CorErrRptEn", 0, 1 },
4476 	{ "PCIE_LINK_CAP", 0x7c, 0 },
4477 	{ "MaxLinkSpeed", 0, 4 },
4489 	{ "PCIE_LINK_STAT_CNTL", 0x80, 0 },
4490 	{ "ASPMCtl", 0, 2 },
4510 	{ "PCIE_DEV_CAP2", 0x94, 0 },
4511 	{ "CplTORangesSup", 0, 4 },
4527 	{ "PCIE_DEV_STAT_CNTL2", 0x98, 0 },
4528 	{ "CplTOValue", 0, 4 },
4540 	{ "PCIE_LINK_CAP2", 0x9c, 0 },
4541 	{ "Rsvd1", 0, 1 },
4545 	{ "PCIE_LINK_STAT_CNTL2", 0xa0, 0 },
4546 	{ "TarLnkSpeed", 0, 4 },
4561 	{ "PCIE_MSIX_CAP", 0xb0, 0 },
4562 	{ "MSIXCapID", 0, 8 },
4568 	{ "PCIE_MSIX_TBL_OFST_BIR", 0xb4, 0 },
4569 	{ "TblBIR", 0, 3 },
4571 	{ "PCIE_MSIX_PBA_OFST_BIR", 0xb8, 0 },
4572 	{ "PBABIR", 0, 3 },
4574 	{ "PCIE_VPD_CAP", 0xd0, 0 },
4575 	{ "VPDCapID", 0, 8 },
4579 	{ "PCIE_VPD_DATA", 0xd4, 0 },
4580 	{ "Data", 0, 32 },
4581 	{ "PCIE_AER_CAP", 0x100, 0 },
4582 	{ "AERCapID", 0, 16 },
4585 	{ "PCIE_AER_UNCOR_ERR_STAT", 0x104, 0 },
4586 	{ "Undefined", 0, 1 },
4606 	{ "PCIE_AER_UNCOR_ERR_MASK", 0x108, 0 },
4607 	{ "Rsvd1", 0, 4 },
4626 	{ "PCIE_AER_UNCOR_ERR_SEV", 0x10c, 0 },
4627 	{ "Rsvd1", 0, 4 },
4646 	{ "PCIE_AER_COR_ERR_STAT", 0x110, 0 },
4647 	{ "RcvrErr", 0, 1 },
4658 	{ "PCIE_AER_COR_ERR_MASK", 0x114, 0 },
4659 	{ "RcvrErr", 0, 1 },
4670 	{ "PCIE_AER_CAP_CNTL", 0x118, 0 },
4671 	{ "FirstErrPtr", 0, 5 },
4680 	{ "CIE_AER_HDR_LOG1", 0x11c, 0 },
4681 	{ "Hdr1DW", 0, 32 },
4682 	{ "CIE_AER_HDR_LOG2", 0x120, 0 },
4683 	{ "Hdr2DW", 0, 32 },
4684 	{ "CIE_AER_HDR_LOG3", 0x124, 0 },
4685 	{ "Hdr3DW", 0, 32 },
4686 	{ "CIE_AER_HDR_LOG4", 0x128, 0 },
4687 	{ "Hdr4DW", 0, 32 },
4688 	{ "PCIE_MFVC_CAP", 0x140, 0 },
4689 	{ "MFVCCapID", 0, 16 },
4692 	{ "PCIE_MFVC_PORT_VC_CAP1", 0x144, 0 },
4693 	{ "ExtVCCount", 0, 3 },
4700 	{ "PCIE_MFVC_PORT_VC_CAP2", 0x148, 0 },
4701 	{ "LoadVCArbTbl", 0, 1 },
4706 	{ "PCIE_MFVC_VC0_RES_CAP", 0x150, 0 },
4707 	{ "PortArbCap", 0, 8 },
4713 	{ "PCIE_MFVC_VC0_RES_CNTL", 0x154, 0 },
4714 	{ "TCVCMapBit0", 0, 1 },
4723 	{ "PCIE_MFVC_VC0_RES_STAT", 0x158, 0 },
4724 	{ "Rsvd1", 0, 16 },
4728 	{ "PCIE_MFVC_VC1_RES_CAP", 0x15c, 0 },
4729 	{ "PortArbCap", 0, 8 },
4735 	{ "PCIE_MFVC_VC1_RES_CNTL", 0x160, 0 },
4736 	{ "TCVCMap", 0, 8 },
4744 	{ "PCIE_MFVC_VC1_RES_STAT", 0x164, 0 },
4745 	{ "Rsvd1", 0, 16 },
4749 	{ "PCIE_DSN_CAP", 0x170, 0 },
4750 	{ "DSNCapID", 0, 16 },
4753 	{ "PCIE_DSN_DW1", 0x174, 0 },
4754 	{ "DSN1Dw", 0, 32 },
4755 	{ "PCIE_DSN_DW2", 0x178, 0 },
4756 	{ "DSN2Dw", 0, 32 },
4757 	{ "PCIE_PB_CAP_HDR", 0x180, 0 },
4758 	{ "PBCapID", 0, 16 },
4761 	{ "PCIE_PB_DATA_SEL", 0x184, 0 },
4762 	{ "DataSelReg", 0, 8 },
4764 	{ "PCIE_PB_DATA_REG", 0x188, 0 },
4765 	{ "BasePower", 0, 8 },
4772 	{ "PCIE_PB_CAP_REG", 0x18c, 0 },
4773 	{ "SysAlloc", 0, 1 },
4775 	{ "PCIE_ARI_CAP_HDR", 0x190, 0 },
4776 	{ "ARICapID", 0, 16 },
4779 	{ "PCIE_ARI_CAP_CNTL", 0x194, 0 },
4780 	{ "MFVCFnGrpCap", 0, 1 },
4789 	{ "PCIE_SEC_PCIE_EXTENDED_CAP_HDR", 0x1a0, 0 },
4790 	{ "PCIeExtCapID", 0, 16 },
4793 	{ "PCIE_LINK_CNTL3", 0x1a4, 0 },
4794 	{ "PerfEql", 0, 1 },
4797 	{ "PCIE_LANE_ERR_STAT", 0x1a8, 0 },
4798 	{ "LaneErrStat", 0, 8 },
4800 	{ "PCIE_LANE_EQL_CNTL0", 0x1ac, 0 },
4801 	{ "Ln0DnPrtXmtrPrst", 0, 4 },
4809 	{ "PCIE_LANE_EQL_CNTL1", 0x1b0, 0 },
4810 	{ "Ln2DnPrtXmtrPrst", 0, 4 },
4818 	{ "PCIE_LANE_EQL_CNTL2", 0x1b4, 0 },
4819 	{ "Ln4DnPrtXmtrPrst", 0, 4 },
4827 	{"PCIE_LANE_EQL_CNTL3", 0x1b8, 0 },
4828 	{ "Ln6DnPrtXmtrPrst", 0, 4 },
4836 	{ "PCIE_SR_CAP_HDR", 0x1c0, 0 },
4837 	{ "SRIOVCapID", 0, 16 },
4840 	{ "PCIE_SR_CAP Register", 0x1c4, 0 },
4841 	{ "VFMigCap", 0, 1 },
4845 	{ "PCIE_SR_STAT_CNTL", 0x1c8, 0 },
4846 	{ "VFEn", 0, 1 },
4854 	{ "PCIE_SR_INIT_TOT_VFS", 0x1cc, 0 },
4855 	{ "InitVFs", 0, 16 },
4857 	{ "PCIE_SR_NUMVFS_FUNCDEPLINK", 0x1d0, 0 },
4858 	{ "NumVFs", 0, 16 },
4860 	{ "PCIE_SR_VF_OFST_STRIDE", 0x1d4 },
4861 	{ "FirstVFOfst", 0, 16 },
4863 	{ "PCIE_SR_VF_DEVID", 0x1d8, 0 },
4864 	{ "Rsvd", 0, 16 },
4866 	{ "PCIE_SR_SUPP_PAGE_SIZES", 0x1dc, 0 },
4867 	{ "SuppPageSzs", 0, 32 },
4868 	{ "PCIE_SR_SYS_PAGE_SIZE", 0x1e0 },
4869 	{ "SysPageSz", 0, 32 },
4870 	{ "PCIE_SR_VFBAR0", 0x1e4, 0 },
4871 	{ "MemSpaceInd", 0, 1 },
4875 	{ "PCIE_SR_VFBAR1", 0x1e8, 0 },
4876 	{ "MemSpaceInd", 0, 1 },
4880 	{ "PCIE_SR_VFBAR2", 0x1ec, 0 },
4881 	{ "MemSpaceInd", 0, 1 },
4885 	{ "PCIE_SR_VFBAR3", 0x1f0, 0 },
4886 	{ "MemSpaceInd", 0, 1 },
4890 	{ "PCIE_SR_VFBAR4", 0x1f4, 0 },
4891 	{ "MemSpaceInd", 0, 1 },
4895 	{ "PCIE_SR_VFBAR5", 0x1f8, 0 },
4896 	{ "MemSpaceInd", 0, 1 },
4900 	{ "PCIE_SR_MIG_STATE_ARRAY_OFST", 0x1fc, 0 },
4901 	{ "Rsvd", 0, 32 },
4902 	{ "PCIE_TPH_CAP_HDR", 0x200, 0 },
4903 	{ "TPHCap", 0, 16 },
4906 	{ "PCIE_TPH_REQ_CAP", 0x204, 0 },
4907 	{ "NoSTModeSup", 0, 1 },
4913 	{ "PCIE_TPH_REQ_CNTL", 0x208, 0 },
4914 	{ "STModeSel", 0, 3 },
4921 	{ "PM_TX_FEATURE_EN", 0x10021, 0 },
4924 	{ "prftch_across_bndle_en", 0, 1 },
4925 	{ "PM_TX_T5_PM_TX_INT_ENABLE", 0x10022, 0 },
4933 	{ "sdc_err_en", 0, 1 },
4934 	{ "PM_TX_PRFTCH_WRR_WAIT_CNT_THRSHLD0", 0x10023, 0 },
4935 	{ "pio_wrr_wait_cnt_thrshld0", 0, 32 },
4936 	{ "PM_TX_PRFTCH_WRR_WAIT_CNT_THRSHLD1", 0x10024, 0 },
4937 	{ "pio_wrr_wait_cnt_thrshld1", 0, 32 },
4938 	{ "PM_TX_PRFTCH_WRR_WAIT_CNT_THRSHLD2", 0x10025, 0 },
4939 	{ "pio_wrr_wait_cnt_thrshld2", 0, 32 },
4940 	{ "PM_TX_PRFTCH_WRR_WAIT_CNT_THRSHLD3", 0x10026, 0 },
4941 	{ "pio_wrr_wait_cnt_thrshld3", 0, 32 },
4942 	{ "PM_TX_CH0_OSPI_DEFICIT_THRSHLD", 0x10027, 0 },
4943 	{ "CH0_OSPI_DEFICIT_THRSHLD", 0, 12 },
4944 	{ "PM_TX_CH1_OSPI_DEFICIT_THRSHLD", 0x10028, 0 },
4945 	{ "CH1_OSPI_DEFICIT_THRSHLD", 0, 12 },
4946 	{ "PM_TX_CH2_OSPI_DEFICIT_THRSHLD", 0x10029, 0 },
4947 	{ "CH2_OSPI_DEFICIT_THRSHLD", 0, 12 },
4948 	{ "PM_TX_CH3_OSPI_DEFICIT_THRSHLD", 0x1002a, 0 },
4949 	{ "CH3_OSPI_DEFICIT_THRSHLD", 0, 12 },
4950 	{ "PM_TX_INT_CAUSE_MASK_HALT", 0x1002b, 0 },
4951 	{ "INT_CAUSE_MASK", 0, 32 },
4952 	{ "PM_TX_DBG_STAT0", 0x1002c, 0 },
4964 	{ "cur_pcmd_len", 0, 16 },
4965 	{ "PM_TX_DBG_STAT1", 0x1002d, 0 },
4972 	{ "Bypass0", 0, 1 },
4973 	{ "PM_TX_DBG_STAT2", 0x1002e, 0 },
4980 	{ "Bypass1", 0, 1 },
4981 	{ "PM_TX_DBG_STAT3", 0x1002f, 0 },
4988 	{ "Bypass2", 0, 1 },
4989 	{ "PM_TX_DBG_STAT4", 0x10030, 0 },
4996 	{ "Bypass3", 0, 1 },
4997 	{ "PM_TX_DBG_STAT5", 0x10031, 0 },
5007 	{ "sdc_drdy", 0, 1 },
5008 	{ "PM_TX_DBG_STAT6", 0x10032, 0 },
5020 	{ "oefifo_full0", 0, 1 },
5021 	{ "PM_TX_DBG_STAT7", 0x10033, 0 },
5035 	{ "E_TxFull0", 0, 1 },
5036 	{ "PM_TX_DBG_STAT8", 0x10034, 0 },
5043 	{ "M_ReqDataRdy", 0, 1 },
5044 	{ "PM_TX_DBG_STAT9", 0x10035, 0 },
5046 	{ "pcmd_free_cnt3", 0, 10 },
5047 	{ "PM_TX_DBG_STAT10", 0x10036, 0 },
5055 	{ "In_Sop_Cnt0", 0, 4 },
5056 	{ "PM_TX_DBG_STAT11", 0x10037, 0 },
5064 	{ "Out_Sop_Cnt0", 0, 4 },
5065 	{ "PM_TX_DBG_STAT12", 0x10038, 0 },
5066 	{ "dbg_stat12", 0, 32 },
5067 	{ "PM_TX_DBG_STAT13", 0x10039, 0 },
5072 	{ "ch0_deficit", 0, 12 },
5073 	{ "PM_TX_DBG_STAT14", 0x1003a, 0 },
5077 	{ "ch2_deficit", 0, 12 },
5078 	{ "PM_TX_DBG_STAT15", 0x1003b, 0 },
5082 	{ "bundle_len0", 0, 12 },
5083 	{ "PM_TX_DBG_STAT16", 0x1003c, 0 },
5087 	{ "bundle_len2", 0, 12 },
5092 	{ "DCA_ST:", 181, 191, 0, 0 },
5093 	{ "StatusPgNS:", 180, 180, 0, 0 },
5094 	{ "StatusPgRO:", 179, 179, 0, 0 },
5095 	{ "FetchNS:", 178, 178, 0, 0 },
5096 	{ "FetchRO:", 177, 177, 0, 0 },
5097 	{ "Valid:", 176, 176, 0, 0 },
5098 	{ "ReschedulePending_1:", 175, 175, 0, 0 },
5099 	{ "PCIeDataChannel:", 174, 174, 0, 0 },
5100 	{ "StatusPgTPHintEn:", 173, 173, 0, 0 },
5101 	{ "StatusPgTPHint:", 171, 172, 0, 0 },
5102 	{ "FetchTPHintEn:", 170, 170, 0, 0 },
5103 	{ "FetchTPHint:", 168, 169, 0, 0 },
5104 	{ "FCThreshOverride:", 167, 167, 0, 0 },
5105 	{ "WRLength:", 162, 166, 0, 0 },
5107 	{ "ReschedulePending:", 160, 160, 0, 0 },
5108 	{ "TimerIx:", 157, 159, 0, 0 },
5110 	{ "FLMPacking:", 155, 155, 0, 0 },
5111 	{ "FetchBurstMax:", 153, 154, 0, 0 },
5112 	{ "uPToken:", 133, 152, 0, 0 },
5113 	{ "uPTokenEn:", 132, 132, 0, 0 },
5114 	{ "UserModeIO:", 131, 131, 0, 0 },
5115 	{ "uPFLCredits:", 123, 130, 0, 0 },
5116 	{ "uPFLCreditEn:", 122, 122, 0, 0 },
5117 	{ "FID:", 111, 121, 0, 0 },
5118 	{ "HostFCMode:", 109, 110, 0, 0 },
5119 	{ "HostFCOwner:", 108, 108, 0, 0 },
5120 	{ "CIDXFlushThresh:", 105, 107, 0, 1 },
5121 	{ "CIDX:", 89, 104, 0, 0 },
5122 	{ "PIDX:", 73, 88, 0, 0 },
5123 	{ "BaseAddress:", 18, 72, 9, 0 },
5124 	{ "QueueSize:", 2, 17, 0, 0 },
5125 	{ "QueueType:", 1, 1, 0, 0 },
5126 	{ "CachePriority:", 0, 0, 0 },
5131 	{ "DCA_ST:", 181, 191, 0, 0 },
5132 	{ "StatusPgNS:", 180, 180, 0, 0 },
5133 	{ "StatusPgRO:", 179, 179, 0, 0 },
5134 	{ "FetchNS:", 178, 178, 0, 0 },
5135 	{ "FetchRO:", 177, 177, 0, 0 },
5136 	{ "Valid:", 176, 176, 0, 0 },
5137 	{ "PCIeDataChannel:", 174, 175, 0, 0 },
5138 	{ "StatusPgTPHintEn:", 173, 173, 0, 0 },
5139 	{ "StatusPgTPHint:", 171, 172, 0, 0 },
5140 	{ "FetchTPHintEn:", 170, 170, 0, 0 },
5141 	{ "FetchTPHint:", 168, 169, 0, 0 },
5142 	{ "FCThreshOverride:", 167, 167, 0, 0 },
5143 	{ "WRLength:", 162, 166, 0, 0 },
5145 	{ "ReschedulePending:", 160, 160, 0, 0 },
5146 	{ "OnChipQueue:", 159, 159, 0, 0 },
5147 	{ "FetchSizeMode:", 158, 158, 0, 0 },
5149 	{ "FLMPacking:", 155, 155, 0, 0 },
5150 	{ "FetchBurstMax:", 153, 154, 0, 0 },
5151 	{ "uPToken:", 133, 152, 0, 0 },
5152 	{ "uPTokenEn:", 132, 132, 0, 0 },
5153 	{ "UserModeIO:", 131, 131, 0, 0 },
5154 	{ "uPFLCredits:", 123, 130, 0, 0 },
5155 	{ "uPFLCreditEn:", 122, 122, 0, 0 },
5156 	{ "FID:", 111, 121, 0, 0 },
5157 	{ "HostFCMode:", 109, 110, 0, 0 },
5158 	{ "HostFCOwner:", 108, 108, 0, 0 },
5159 	{ "CIDXFlushThresh:", 105, 107, 0, 1 },
5160 	{ "CIDX:", 89, 104, 0, 0 },
5161 	{ "PIDX:", 73, 88, 0, 0 },
5162 	{ "BaseAddress:", 18, 72, 9, 0 },
5163 	{ "QueueSize:", 2, 17, 0, 0 },
5164 	{ "QueueType:", 1, 1, 0, 0 },
5165 	{ "CachePriority:", 0, 0, 0 },
5196 	{ "BaseAddress:", 48, 102, 9, 0 },
5199 	{ "QueueSize:", 4, 15, 4, 0 },
5202 	{ "CachePriority:", 0, 0 },
5229 	{ "BaseAddress:", 48, 102, 9, 0 },
5232 	{ "QueueSize:", 4, 15, 4, 0 },
5235 	{ "CachePriority:", 0, 0 },
5245 	{ "CngChMap:", 0, 15, 0, 0 },
5268 	{ "PIDX:", 0, 7 },
5288 	{ "PIDX:", 0, 7 },
5293 	{ "HMAT6_DEBUG_FSM_0", 0xa000, 0 },
5301 	{ "rd_fsm", 0, 2 },
5302 	{ "HMAT6_DEBUG_FSM_1", 0xa001, 0 },
5306 	{ "pio_fsm", 0, 5 },
5307 	{ "HMAT6_DEBUG_PCIE_INTF", 0xa002, 0 },
5329 	{ "pcie_trrerr", 0, 1 },
5330 	{ "HMAT6_DEBUG_PCIE_ADDR_INTERNAL_LO", 0xa003, 0 },
5331 	{ "pcie_addr_lo", 0, 32 },
5332 	{ "HMAT6_DEBUG_PCIE_ADDR_INTERNAL_HI", 0xa004, 0 },
5333 	{ "pcie_addr_hi", 0, 32 },
5334 	{ "HMAT6_DEBUG_PCIE_REQ_DATA_EXTERNAL", 0xa005, 0 },
5337 	{ "ReqData0", 0, 21 },
5338 	{ "HMAT6_DEBUG_PCIE_RSP_DATA_EXTERNAL", 0xa006, 0 },
5342 	{ "RspData0", 0, 8 },
5343 	{ "HMAT6_DEBUG_MA_SLV_CTL", 0xa007, 0 },
5353 	{ "mas_tlb_err", 0, 1 },
5354 	{ "HMAT6_DEBUG_MA_SLV_ADDR_INTERNAL", 0xa008, 0 },
5355 	{ "ma_addr", 0, 32 },
5356 	{ "HMAT6_DEBUG_TLB_HIT_ENTRY", 0xa009, 0 },
5357 	{ "tlb_hit_entry", 0, 32 },
5358 	{ "HMAT6_DEBUG_TLB_HIT_CNT", 0xa00a, 0 },
5359 	{ "tlb_hit_cnt", 0, 32 },
5360 	{ "HMAT6_DEBUG_TLB_MISS_CNT", 0xa00b, 0 },
5361 	{ "tlb_miss_cnt", 0, 32 },
5362 	{ "HMAT6_DEBUG_PAGE_TBL_LKP_CTL", 0xa00c, 0 },
5365 	{ "lkp_rsp_vld", 0, 1 },
5366 	{ "HMAT6_DEBUG_PAGE_TBL_LKP_REQ_ADDR", 0xa00d, 0 },
5367 	{ "lkp_req_addr", 0, 32 },
5368 	{ "HMAT6_DEBUG_PAGE_TBL_LKP_RSP_0", 0xa00e, 0 },
5369 	{ "lkp_rsp_0", 0, 32, },
5370 	{ "HMAT6_DEBUG_PAGE_TBL_LKP_RSP_1", 0xa00f, 0 },
5371 	{ "lkp_rsp_1", 0, 32 },
5372 	{ "HMAT6_DEBUG_PAGE_TBL_LKP_RSP_2", 0xa010, 0 },
5373 	{ "lkp_rsp_2", 0, 32 },
5374 	{ "HMAT6_DEBUG_PAGE_TBL_LKP_RSP_3", 0xa011, 0 },
5375 	{ "lkp_rsp_3", 0, 32 },
5376 	{ "HMAT6_DEBUG_PAGE_TBL_LKP_RSP_4", 0xa012, 0 },
5377 	{ "lkp_rsp_4", 0, 32 },
5378 	{ "HMAT6_DEBUG_PAGE_TBL_LKP_RSP_5", 0xa013, 0 },
5379 	{ "lkp_rsp_5", 0, 32 },
5380 	{ "HMAT6_DEBUG_PAGE_TBL_LKP_RSP_6", 0xa014, 0 },
5381 	{ "lkp_rsp_6", 0, 32 },
5382 	{ "HMAT6_DEBUG_PAGE_TBL_LKP_RSP_7", 0xa015, 0 },
5383 	{ "lkp_rsp_7", 0, 32 },
5384 	{ "HMAT6_DEBUG_PHYS_DESC_INTERNAL_LO", 0xa016, 0 },
5385 	{ "paddr_lo", 0, 32 },
5386 	{ "HMAT6_DEBUG_PCIE_RD_REQ_CNT_LO", 0xa017, 0 },
5387 	{ "rd_req_cnt_lo", 0, 32 },
5388 	{ "HMAT6_DEBUG_PCIE_RD_REQ_CNT_HI", 0xa018, 0 },
5389 	{ "rd_req_cnt_hi", 0, 32 },
5390 	{ "HMAT6_DEBUG_PCIE_WR_REQ_CNT_LO", 0xa019, 0 },
5391 	{ "wr_req_cnt_lo", 0, 32 },
5392 	{ "HMAT6_DEBUG_PCIE_WR_REQ_CNT_HI", 0xa01a, 0 },
5393 	{ "wr_req_cnt_hi", 0, 32 },
5394 	{ "HMAT6_DEBUG_PCIE_RD_DATA_CYC_CNT_LO", 0xa01b, 0 },
5395 	{ "rd_data_cnt_lo", 0, 32 },
5396 	{ "HMAT6_DEBUG_PCIE_RD_DATA_CYC_CNT_HI", 0xa01c, 0 },
5397 	{ "rd_data_cnt_hi", 0, 32 },
5398 	{ "HMAT6_DEBUG_PCIE_WR_DATA_CYC_CNT_LO", 0xa01d, 0 },
5399 	{ "wr_data_cnt_lo", 0, 32 },
5400 	{ "HMAT6_DEBUG_PCIE_WR_DATA_CYC_CNT_HI", 0xa01e, 0 },
5401 	{ "wr_data_cnt_hi", 0, 32 },
5402 	{ "HMAT6_DEBUG_PCIE_SOP_EOP_CNT", 0xa01f, 0 },
5405 	{ "rd_eop_cnt", 0, 8 },
5410 	{ "MA_SGE_THREAD_0_CLIENT_INTERFACE_EXTERNAL", 0xa000, 0 },
5420 	{ "RdData0", 0, 4 },
5421 	{ "MA_SGE_THREAD_1_CLIENT_INTERFACE_EXTERNAL", 0xa001, 0 },
5431 	{ "RdData1", 0, 4 },
5432 	{ "MA_ULP_TX_CLIENT_INTERFACE_EXTERNAL", 0xa002, 0 },
5442 	{ "RdData2", 0, 4 },
5443 	{ "MA_ULP_RX_CLIENT_INTERFACE_EXTERNAL", 0xa003, 0 },
5453 	{ "RdData3", 0, 4 },
5454 	{ "MA_ULP_TX_RX_CLIENT_INTERFACE_EXTERNAL", 0xa004, 0 },
5464 	{ "RdData4", 0, 4 },
5465 	{ "MA_TP_THREAD_0_CLIENT_INTERFACE_EXTERNAL", 0xa005, 0 },
5475 	{ "RdData5", 0, 4 },
5476 	{ "MA_TP_THREAD_1_CLIENT_INTERFACE_EXTERNAL", 0xa006, 0 },
5486 	{ "RdData6", 0, 4 },
5487 	{ "MA_LE_CLIENT_INTERFACE_EXTERNAL", 0xa007, 0 },
5497 	{ "RdData7", 0, 4 },
5498 	{ "MA_CIM_CLIENT_INTERFACE_EXTERNAL", 0xa008, 0 },
5508 	{ "RdData8", 0, 4 },
5509 	{ "MA_PCIE_CLIENT_INTERFACE_EXTERNAL", 0xa009, 0 },
5519 	{ "RdData9", 0, 4 },
5520 	{ "MA_PM_TX_CLIENT_INTERFACE_EXTERNAL", 0xa00a, 0 },
5530 	{ "RdData10", 0, 4 },
5531 	{ "MA_PM_RX_CLIENT_INTERFACE_EXTERNAL", 0xa00b, 0 },
5541 	{ "RdData11", 0, 4 },
5542 	{ "MA_HMA_CLIENT_INTERFACE_EXTERNAL", 0xa00c, 0 },
5552 	{ "RdData12", 0, 4 },
5553 	{ "MA_TARGET_0_ARBITER_INTERFACE_EXTERNAL_REG0", 0xa00d, 0 },
5585 	{ "dm0_ci7_rdata_vld", 0, 1 },
5586 	{ "MA_TARGET_1_ARBITER_INTERFACE_EXTERNAL_REG0", 0xa00e, 0 },
5618 	{ "dm1_ci7_rdata_vld", 0, 1 },
5619 	{ "MA_TARGET_2_ARBITER_INTERFACE_EXTERNAL_REG0", 0xa00f, 0 },
5651 	{ "dm2_ci7_rdata_vld", 0, 1 },
5652 	{ "MA_TARGET_3_ARBITER_INTERFACE_EXTERNAL_REG0", 0xa010, 0 },
5684 	{ "dm3_ci7_rdata_vld", 0, 1 },
5685 	{ "MA_MA_DEBUG_SIGNATURE_LTL_END", 0xa011, 0 },
5686 	{ "MA_MA_DEBUG_SIGNATURE_BIG_END_INVERSE", 0xa012, 0 },
5687 	{ "MA_TARGET_0_ARBITER_INTERFACE_EXTERNAL_REG1", 0xa013, 0 },
5708 	{ "RSVD", 0, 12 },
5709 	{ "MA_TARGET_1_ARBITER_INTERFACE_EXTERNAL_REG1", 0xa014, 0 },
5730 	{ "RSVD", 0, 12 },
5731 	{ "MA_TARGET_2_ARBITER_INTERFACE_EXTERNAL_REG1", 0xa015, 0 },
5752 	{ "RSVD", 0, 12 },
5753 	{ "MA_TARGET_3_ARBITER_INTERFACE_EXTERNAL_REG1", 0xa016, 0 },
5774 	{"RSVD", 0, 12 },
5778 	{ "MA_SGE_THREAD_0_CLIENT_INTERFACE_INTERNAL_REG0", 0xa400, 0 },
5786 	{ "RSVD", 0, 1 },
5787 	{ "MA_SGE_THREAD_1_CLIENT_INTERFACE_INTERNAL_REG0", 0xa401, 0 },
5795 	{ "RSVD", 0, 1 },
5796 	{ "MA_ULP_TX_CLIENT_INTERFACE_INTERNAL_REG0", 0xa402, 0 },
5804 	{ "RSVD", 0, 1 },
5805 	{ "MA_ULP_RX_CLIENT_INTERFACE_INTERNAL_REG0", 0xa403, 0 },
5813 	{ "RSVD", 0, 1 },
5814 	{ "MA_ULP_TX_RX_CLIENT_INTERFACE_INTERNAL_REG0", 0xa404, 0 },
5822 	{ "RSVD", 0, 1 },
5823 	{ "MA_TP_THREAD_0_CLIENT_INTERFACE_INTERNAL_REG0", 0xa405, 0 },
5831 	{ "RSVD", 0, 1 },
5832 	{ "MA_TP_THREAD_1_CLIENT_INTERFACE_INTERNAL_REG0", 0xa406, 0 },
5840 	{ "RSVD", 0, 1 },
5841 	{ "MA_LE_CLIENT_INTERFACE_INTERNAL_REG0", 0xa407, 0 },
5849 	{ "RSVD", 0, 1 },
5850 	{ "MA_CIM_CLIENT_INTERFACE_INTERNAL_REG0", 0xa408, 0 },
5858 	{ "RSVD", 0, 1 },
5859 	{ "MA_PCIE_CLIENT_INTERFACE_INTERNAL_REG0", 0xa409, 0 },
5867 	{ "RSVD", 0, 1 },
5868 	{ "MA_PM_TX_CLIENT_INTERFACE_INTERNAL_REG0", 0xa40a, 0 },
5876 	{ "RSVD", 0, 1 },
5877 	{ "MA_PM_RX_CLIENT_INTERFACE_INTERNAL_REG0", 0xa40b, 0 },
5885 	{ "RSVD", 0, 1 },
5886 	{ "MA_HMA_CLIENT_INTERFACE_INTERNAL_REG0", 0xa40c, 0 },
5894 	{ "RSVD", 0, 1 },
5895 	{ "MA_TARGET_0_ARBITER_INTERFACE_INTERNAL_REG0", 0xa40d, 0 },
5902 	{ "Wr_Data_512b_FIFO_Cnt_tgt0", 0, 8 },
5903 	{ "MA_TARGET_1_ARBITER_INTERFACE_INTERNAL_REG0", 0xa40e, 0 },
5910 	{ "Wr_Data_512b_FIFO_Cnt_tgt1", 0, 8 },
5911 	{"MA_TARGET_2_ARBITER_INTERFACE_INTERNAL_REG0", 0xa40f, 0 },
5918 	{ "Wr_Data_512b_FIFO_Cnt_tgt2", 0, 8 },
5919 	{ "MA_TARGET_3_ARBITER_INTERFACE_INTERNAL_REG0", 0xa410, 0 },
5926 	{ "Wr_Data_512b_FIFO_Cnt_tgt3", 0, 8 },
5927 	{ "MA_SGE_THREAD_0_CLNT_EXP_RD_CYC_CNT", 0xa412, 0 },
5928 	{ "MA_SGE_THREAD_1_CLNT_EXP_RD_CYC_CNT", 0xa413, 0 },
5929 	{ "MA_ULP_TX_CLNT_EXP_RD_CYC_CNT", 0xa414, 0 },
5930 	{ "MA_ULP_RX_CLNT_EXP_RD_CYC_CNT", 0xa415, 0 },
5931 	{ "MA_ULP_TX_RX_CLNT_EXP_RD_CYC_CNT", 0xa416, 0 },
5932 	{ "MA_TP_THREAD_0_CLNT_EXP_RD_CYC_CNT", 0xa417, 0 },
5933 	{ "MA_TP_THREAD_1_CLNT_EXP_RD_CYC_CNT", 0xa418, 0 },
5934 	{ "MA_LE_CLNT_EXP_RD_CYC_CNT", 0xa419, 0 },
5935 	{ "MA_CIM_CLNT_EXP_RD_CYC_CNT", 0xa41a, 0 },
5936 	{ "MA_PCIE_CLNT_EXP_RD_CYC_CNT", 0xa41b, 0 },
5937 	{ "MA_PM_TX_CLNT_EXP_RD_CYC_CNT", 0xa41c, 0 },
5938 	{ "MA_PM_RX_CLNT_EXP_RD_CYC_CNT", 0xa41d, 0 },
5939 	{ "MA_HMA_CLNT_EXP_RD_CYC_CNT", 0xa41e, 0 },
5944 	{ "MA_EDRAM0_WRDATA_CNT1", 0xa800, 0 },
5945 	{ "MA_EDRAM0_WRDATA_CNT0", 0xa801, 0 },
5946 	{ "MA_EDRAM1_WRDATA_CNT1", 0xa802, 0 },
5947 	{ "MA_EDRAM1_WRDATA_CNT0", 0xa803, 0 },
5948 	{ "MA_EXT_MEMORY0_WRDATA_CNT1", 0xa804, 0 },
5949 	{ "MA_EXT_MEMORY0_WRDATA_CNT0", 0xa805, 0 },
5950 	{ "MA_HOST_MEMORY_WRDATA_CNT1", 0xa806, 0 },
5951 	{ "MA_HOST_MEMORY_WRDATA_CNT0", 0xa807, 0 },
5952 	{ "MA_EXT_MEMORY1_WRDATA_CNT1", 0xa808, 0 },
5953 	{ "MA_EXT_MEMORY1_WRDATA_CNT0", 0xa809, 0 },
5954 	{ "MA_EDRAM0_RDDATA_CNT1", 0xa80a, 0 },
5955 	{ "MA_EDRAM0_RDDATA_CNT0", 0xa80b, 0 },
5956 	{ "MA_EDRAM1_RDDATA_CNT1", 0xa80c, 0 },
5957 	{ "MA_EDRAM1_RDDATA_CNT0", 0xa80d, 0 },
5958 	{ "MA_EXT_MEMORY0_RDDATA_CNT1", 0xa80e, 0 },
5959 	{ "MA_EXT_MEMORY0_RDDATA_CNT0", 0xa80f, 0 },
5960 	{ "MA_HOST_MEMORY_RDDATA_CNT1", 0xa810, 0 },
5961 	{ "MA_HOST_MEMORY_RDDATA_CNT0", 0xa811, 0 },
5962 	{ "MA_EXT_MEMORY1_RDDATA_CNT1", 0xa812, 0 },
5963 	{ "MA_EXT_MEMORY1_RDDATA_CNT0", 0xa813, 0 },
5968 	{ "MA_SGE_THREAD_0_CLIENT_INTERFACE_INTERNAL_REG1", 0xe400, 0 },
5978 	{ "RSVD", 0, 11 },
5979 	{ "MA_SGE_THREAD_1_CLIENT_INTERFACE_INTERNAL_REG1", 0xe420, 0 },
5989 	{ "RSVD", 0, 11 },
5990 	{ "MA_ULP_TX_CLIENT_INTERFACE_INTERNAL_REG1", 0xe440, 0 },
6000 	{ "RSVD", 0, 11 },
6001 	{ "MA_ULP_RX_CLIENT_INTERFACE_INTERNAL_REG1", 0xe460, 0 },
6011 	{ "RSVD", 0, 11 },
6012 	{ "MA_ULP_TX_RX_CLIENT_INTERFACE_INTERNAL_REG1", 0xe480, 0 },
6022 	{ "RSVD", 0, 11 },
6023 	{ "MA_TP_THREAD_0_CLIENT_INTERFACE_INTERNAL_REG1", 0xe4a0, 0 },
6033 	{ "RSVD", 0, 11 },
6034 	{ "MA_TP_THREAD_1_CLIENT_INTERFACE_INTERNAL_REG1", 0xe4c0, 0 },
6044 	{ "RSVD", 0, 11 },
6045 	{ "MA_LE_CLIENT_INTERFACE_INTERNAL_REG1", 0xe4e0, 0 },
6055 	{ "RSVD", 0, 11 },
6056 	{ "MA_CIM_CLIENT_INTERFACE_INTERNAL_REG1", 0xe500, 0 },
6066 	{ "RSVD", 0, 11 },
6067 	{ "MA_PCIE_CLIENT_INTERFACE_INTERNAL_REG1", 0xe520, 0 },
6077 	{ "RSVD", 0, 11 },
6078 	{ "MA_PM_TX_CLIENT_INTERFACE_INTERNAL_REG1", 0xe540, 0 },
6088 	{ "RSVD", 0, 11 },
6089 	{ "MA_PM_RX_CLIENT_INTERFACE_INTERNAL_REG1", 0xe560, 0 },
6099 	{ "RSVD", 0, 11 },
6100 	{ "MA_HMA_CLIENT_INTERFACE_INTERNAL_REG1", 0xe580, 0 },
6110 	{ "RSVD", 0, 11 },
6111 	{ "MA_TARGET_0_ARBITER_INTERFACE_INTERNAL_REG1", 0xe5a0, 0 },
6114 	{ "Rd_Data_FIFO_Cnt0", 0, 8 },
6115 	{ "MA_TARGET_1_ARBITER_INTERFACE_INTERNAL_REG1", 0xe5c0, 0 },
6118 	{ "Rd_Data_FIFO_Cnt1", 0, 8 },
6119 	{ "MA_TARGET_2_ARBITER_INTERFACE_INTERNAL_REG1", 0xe5e0, 0 },
6122 	{ "Rd_Data_FIFO_Cnt2", 0, 8 },
6123 	{ "MA_TARGET_3_ARBITER_INTERFACE_INTERNAL_REG1", 0xe600, 0 },
6126 	{ "Rd_Data_FIFO_Cnt3", 0, 8 },
6131 	{ "MA_SGE_THREAD_0_CLNT_EXP_WR_CYC_CNT", 0xe640, 0 },
6132 	{ "MA_SGE_THREAD_1_CLNT_EXP_WR_CYC_CNT", 0xe660, 0 },
6133 	{ "MA_ULP_TX_CLNT_EXP_WR_CYC_CNT", 0xe680, 0 },
6134 	{ "MA_ULP_RX_CLNT_EXP_WR_CYC_CNT", 0xe6a0, 0 },
6135 	{ "MA_ULP_TX_RX_CLNT_EXP_WR_CYC_CNT", 0xe6c0, 0 },
6136 	{ "MA_TP_THREAD_0_CLNT_EXP_WR_CYC_CNT", 0xe6e0, 0 },
6137 	{ "MA_TP_THREAD_1_CLNT_EXP_WR_CYC_CNT", 0xe700, 0 },
6138 	{ "MA_LE_CLNT_EXP_WR_CYC_CNT", 0xe720, 0 },
6139 	{ "MA_CIM_CLNT_EXP_WR_CYC_CNT", 0xe740, 0 },
6140 	{ "MA_PCIE_CLNT_EXP_WR_CYC_CNT", 0xe760, 0 },
6141 	{ "MA_PM_TX_CLNT_EXP_WR_CYC_CNT", 0xe780, 0 },
6142 	{ "MA_PM_RX_CLNT_EXP_WR_CYC_CNT", 0xe7a0, 0 },
6143 	{ "MA_HMA_CLNT_EXP_WR_CYC_CNT", 0xe7c0, 0 },
6190 	{"CIM_CTL_CONFIG", 0x2000, 0},
6203 	{"PrefEn", 0, 1},
6204 	{"CIM_CTL_PREFADDR", 0x2004, 0},
6205 	{"PrefAddr", 0, 32},
6206 	{"CIM_CTL_ALLOCADDR", 0x2008, 0},
6207 	{"IbqGen0", 0, 32},
6208 	{"CIM_CTL_INVLDTADDR", 0x200c, 0},
6209 	{"InvldtAddr", 0, 32},
6210 	{"CIM_CTL_STATIC_PREFADDR0", 0x2010, 0},
6211 	{"StaticPrefAddr", 0, 32},
6212 	{"CIM_CTL_STATIC_PREFADDR1", 0x2014, 0},
6213 	{"StaticPrefAddr", 0, 32},
6214 	{"CIM_CTL_STATIC_PREFADDR2", 0x2018, 0},
6215 	{"StaticPrefAddr", 0, 32},
6216 	{"CIM_CTL_STATIC_PREFADDR3", 0x201c, 0},
6217 	{"StaticPrefAddr", 0, 32},
6218 	{"CIM_CTL_STATIC_PREFADDR4", 0x2020, 0},
6219 	{"StaticPrefAddr", 0, 32},
6220 	{"CIM_CTL_STATIC_PREFADDR5", 0x2024, 0},
6221 	{"StaticPrefAddr", 0, 32},
6222 	{"CIM_CTL_STATIC_PREFADDR6", 0x2028, 0},
6223 	{"StaticPrefAddr", 0, 32},
6224 	{"CIM_CTL_STATIC_PREFADDR7", 0x202c, 0},
6225 	{"StaticPrefAddr", 0, 32},
6226 	{"CIM_CTL_STATIC_PREFADDR8", 0x2030, 0},
6227 	{"StaticPrefAddr", 0, 32},
6228 	{"CIM_CTL_STATIC_PREFADDR9", 0x2034, 0},
6229 	{"StaticPrefAddr", 0, 32},
6230 	{"CIM_CTL_STATIC_PREFADDR10", 0x2038, 0},
6231 	{"StaticPrefAddr", 0, 32},
6232 	{"CIM_CTL_STATIC_PREFADDR11", 0x203c, 0},
6233 	{"StaticPrefAddr", 0, 32},
6234 	{"CIM_CTL_STATIC_PREFADDR12", 0x2040, 0},
6235 	{"StaticPrefAddr", 0, 32},
6236 	{"CIM_CTL_STATIC_PREFADDR13", 0x2044, 0},
6237 	{"StaticPrefAddr", 0, 32},
6238 	{"CIM_CTL_STATIC_PREFADDR14", 0x2048, 0},
6239 	{"StaticPrefAddr", 0, 32},
6240 	{"CIM_CTL_STATIC_PREFADDR15", 0x204c, 0},
6241 	{"StaticPrefAddr", 0, 32},
6242 	{"CIM_CTL_STATIC_ALLOCADDR0", 0x2050, 0},
6243 	{"StaticAllocAddr", 0, 32},
6244 	{"CIM_CTL_STATIC_ALLOCADDR1", 0x2054, 0},
6245 	{"StaticAllocAddr", 0, 32},
6246 	{"CIM_CTL_STATIC_ALLOCADDR2", 0x2058, 0},
6247 	{"StaticAllocAddr", 0, 32},
6248 	{"CIM_CTL_STATIC_ALLOCADDR3", 0x205c, 0},
6249 	{"StaticAllocAddr", 0, 32},
6250 	{"CIM_CTL_STATIC_ALLOCADDR4", 0x2060, 0},
6251 	{"StaticAllocAddr", 0, 32},
6252 	{"CIM_CTL_STATIC_ALLOCADDR5", 0x2064, 0},
6253 	{"StaticAllocAddr", 0, 32},
6254 	{"CIM_CTL_STATIC_ALLOCADDR6", 0x2068, 0},
6255 	{"StaticAllocAddr", 0, 32},
6256 	{"CIM_CTL_STATIC_ALLOCADDR7", 0x206c, 0},
6257 	{"StaticAllocAddr", 0, 32},
6258 	{"CIM_CTL_STATIC_ALLOCADDR8", 0x2070, 0},
6259 	{"StaticAllocAddr", 0, 32},
6260 	{"CIM_CTL_STATIC_ALLOCADDR9", 0x2074, 0},
6261 	{"StaticAllocAddr", 0, 32},
6262 	{"CIM_CTL_STATIC_ALLOCADDR10", 0x2078, 0},
6263 	{"StaticAllocAddr", 0, 32},
6264 	{"CIM_CTL_STATIC_ALLOCADDR11", 0x207c, 0},
6265 	{"StaticAllocAddr", 0, 32},
6270 	{"CIM_CTL_CONFIG", 0x2000, 0},
6281 	{"PrefEn", 0, 1},
6282 	{"CIM_CTL_PREFADDR", 0x2004, 0},
6283 	{"PrefAddr", 0, 32},
6284 	{"CIM_CTL_ALLOCADDR", 0x2008, 0},
6285 	{"IbqGen0", 0, 32},
6286 	{"CIM_CTL_INVLDTADDR", 0x200c, 0},
6287 	{"InvldtAddr", 0, 32},
6288 	{"CIM_CTL_STATIC_PREFADDR0", 0x2010, 0},
6289 	{"StaticPrefAddr", 0, 32},
6290 	{"CIM_CTL_STATIC_PREFADDR1", 0x2014, 0},
6291 	{"StaticPrefAddr", 0, 32},
6292 	{"CIM_CTL_STATIC_PREFADDR2", 0x2018, 0},
6293 	{"StaticPrefAddr", 0, 32},
6294 	{"CIM_CTL_STATIC_PREFADDR3", 0x201c, 0},
6295 	{"StaticPrefAddr", 0, 32},
6296 	{"CIM_CTL_STATIC_PREFADDR4", 0x2020, 0},
6297 	{"StaticPrefAddr", 0, 32},
6298 	{"CIM_CTL_STATIC_PREFADDR5", 0x2024, 0},
6299 	{"StaticPrefAddr", 0, 32},
6300 	{"CIM_CTL_STATIC_PREFADDR6", 0x2028, 0},
6301 	{"StaticPrefAddr", 0, 32},
6302 	{"CIM_CTL_STATIC_PREFADDR7", 0x202c, 0},
6303 	{"StaticPrefAddr", 0, 32},
6304 	{"CIM_CTL_STATIC_PREFADDR8", 0x2030, 0},
6305 	{"StaticPrefAddr", 0, 32},
6306 	{"CIM_CTL_STATIC_PREFADDR9", 0x2034, 0},
6307 	{"StaticPrefAddr", 0, 32},
6308 	{"CIM_CTL_STATIC_PREFADDR10", 0x2038, 0},
6309 	{"StaticPrefAddr", 0, 32},
6310 	{"CIM_CTL_STATIC_PREFADDR11", 0x203c, 0},
6311 	{"StaticPrefAddr", 0, 32},
6312 	{"CIM_CTL_STATIC_PREFADDR12", 0x2040, 0},
6313 	{"StaticPrefAddr", 0, 32},
6314 	{"CIM_CTL_STATIC_PREFADDR13", 0x2044, 0},
6315 	{"StaticPrefAddr", 0, 32},
6316 	{"CIM_CTL_STATIC_PREFADDR14", 0x2048, 0},
6317 	{"StaticPrefAddr", 0, 32},
6318 	{"CIM_CTL_STATIC_PREFADDR15", 0x204c, 0},
6319 	{"StaticPrefAddr", 0, 32},
6320 	{"CIM_CTL_STATIC_ALLOCADDR0", 0x2050, 0},
6321 	{"StaticAllocAddr", 0, 32},
6322 	{"CIM_CTL_STATIC_ALLOCADDR1", 0x2054, 0},
6323 	{"StaticAllocAddr", 0, 32},
6324 	{"CIM_CTL_STATIC_ALLOCADDR2", 0x2058, 0},
6325 	{"StaticAllocAddr", 0, 32},
6326 	{"CIM_CTL_STATIC_ALLOCADDR3", 0x205c, 0},
6327 	{"StaticAllocAddr", 0, 32},
6328 	{"CIM_CTL_STATIC_ALLOCADDR4", 0x2060, 0},
6329 	{"StaticAllocAddr", 0, 32},
6330 	{"CIM_CTL_STATIC_ALLOCADDR5", 0x2064, 0},
6331 	{"StaticAllocAddr", 0, 32},
6332 	{"CIM_CTL_STATIC_ALLOCADDR6", 0x2068, 0},
6333 	{"StaticAllocAddr", 0, 32},
6334 	{"CIM_CTL_STATIC_ALLOCADDR7", 0x206c, 0},
6335 	{"StaticAllocAddr", 0, 32},
6336 	{"CIM_CTL_STATIC_ALLOCADDR8", 0x2070, 0},
6337 	{"StaticAllocAddr", 0, 32},
6338 	{"CIM_CTL_STATIC_ALLOCADDR9", 0x2074, 0},
6339 	{"StaticAllocAddr", 0, 32},
6340 	{"CIM_CTL_STATIC_ALLOCADDR10", 0x2078, 0},
6341 	{"StaticAllocAddr", 0, 32},
6342 	{"CIM_CTL_STATIC_ALLOCADDR11", 0x207c, 0},
6343 	{"StaticAllocAddr", 0, 32},
6348 	{"CIM_CTL_0_TSCH_CHANNEL_TSCH_CHNLN_CTL", 0x4900, 0},
6352 	{"CIM_CTL_1_TSCH_CHANNEL_TSCH_CHNLN_CTL", 0x4a20, 0},
6356 	{"CIM_CTL_2_TSCH_CHANNEL_TSCH_CHNLN_CTL", 0x4b40, 0},
6360 	{"CIM_CTL_3_TSCH_CHANNEL_TSCH_CHNLN_CTL", 0x4c60, 0},
6368 	{"CIM_CTL_0_TSCH_CHANNEL_TSCH_CHNLN_CLASS_RATECTL", 0x4904, 0},
6369 	{"TSC0RATECTL", 0, 1},
6385 	{"CIM_CTL_1_TSCH_CHANNEL_TSCH_CHNLN_CLASS_RATECTL", 0x4a24, 0},
6386 	{"TSC0RATECTL", 0, 1},
6402 	{"CIM_CTL_2_TSCH_CHANNEL_TSCH_CHNLN_CLASS_RATECTL", 0x4b44, 0},
6403 	{"TSC0RATECTL", 0, 1},
6419 	{"CIM_CTL_3_TSCH_CHANNEL_TSCH_CHNLN_CLASS_RATECTL", 0x4c64, 0},
6420 	{"TSC0RATECTL", 0, 1},
6440 	{"CIM_CTL_0_TSCH_CHANNEL_TSCH_CHNLN_CLASS_ENABLE_A", 0x4908, 0},
6472 	{"TSC0RATEEN", 0, 1},
6473 	{"CIM_CTL_1_TSCH_CHANNEL_TSCH_CHNLN_CLASS_ENABLE_A", 0x4a28, 0},
6505 	{"TSC0RATEEN", 0, 1},
6506 	{"CIM_CTL_2_TSCH_CHANNEL_TSCH_CHNLN_CLASS_ENABLE_A", 0x4b48, 0},
6538 	{"TSC0RATEEN", 0, 1},
6539 	{"CIM_CTL_3_TSCH_CHANNEL_TSCH_CHNLN_CLASS_ENABLE_A", 0x4c68, 0},
6571 	{"TSC0RATEEN", 0, 1},
6576 	{"CIM_CTL_0_TSCH_CHANNEL_TSCH_CHNLN_RATE_LIMITER", 0x4910, 0},
6579 	{"TSCHNLRATEL", 0, 30},
6580 	{"CIM_CTL_1_TSCH_CHANNEL_TSCH_CHNLN_RATE_LIMITER", 0x4a30, 0},
6583 	{"TSCHNLRATEL", 0, 30},
6584 	{"CIM_CTL_2_TSCH_CHANNEL_TSCH_CHNLN_RATE_LIMITER", 0x4b50, 0},
6587 	{"TSCHNLRATEL", 0, 30},
6588 	{"CIM_CTL_3_TSCH_CHANNEL_TSCH_CHNLN_RATE_LIMITER", 0x4c70, 0},
6591 	{"TSCHNLRATEL", 0, 30},
6596 	{"CIM_CTL_0_TSCH_CHANNEL_TSCH_CHNLN_RATE_PROPERTIES", 0x4914, 0},
6599 	{"TSCHNLRINCR", 0, 14},
6600 	{"CIM_CTL_1_TSCH_CHANNEL_TSCH_CHNLN_RATE_PROPERTIES", 0x4a34, 0},
6603 	{"TSCHNLRINCR", 0, 14},
6604 	{"CIM_CTL_2_TSCH_CHANNEL_TSCH_CHNLN_RATE_PROPERTIES", 0x4b54, 0},
6607 	{"TSCHNLRINCR", 0, 14},
6608 	{"CIM_CTL_3_TSCH_CHANNEL_TSCH_CHNLN_RATE_PROPERTIES", 0x4c74, 0},
6611 	{"TSCHNLRINCR", 0, 14},
6616 	{"CIM_CTL_0_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_LIMITER", 0x4920, 0},
6619 	{"TSCCLRATEL", 0, 24},
6620 	{"CIM_CTL_1_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_LIMITER", 0x4930, 0},
6623 	{"TSCCLRATEL", 0, 24},
6624 	{"CIM_CTL_2_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_LIMITER", 0x4940, 0},
6627 	{"TSCCLRATEL", 0, 24},
6628 	{"CIM_CTL_3_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_LIMITER", 0x4950, 0},
6631 	{"TSCCLRATEL", 0, 24},
6632 	{"CIM_CTL_4_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_LIMITER", 0x4960, 0},
6635 	{"TSCCLRATEL", 0, 24},
6636 	{"CIM_CTL_5_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_LIMITER", 0x4970, 0},
6639 	{"TSCCLRATEL", 0, 24},
6640 	{"CIM_CTL_6_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_LIMITER", 0x4980, 0},
6643 	{"TSCCLRATEL", 0, 24},
6644 	{"CIM_CTL_7_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_LIMITER", 0x4990, 0},
6647 	{"TSCCLRATEL", 0, 24},
6648 	{"CIM_CTL_8_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_LIMITER", 0x49a0, 0},
6651 	{"TSCCLRATEL", 0, 24},
6652 	{"CIM_CTL_9_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_LIMITER", 0x49b0, 0},
6655 	{"TSCCLRATEL", 0, 24},
6656 	{"CIM_CTL_10_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_LIMITER", 0x49c0, 0},
6659 	{"TSCCLRATEL", 0, 24},
6660 	{"CIM_CTL_11_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_LIMITER", 0x49d0, 0},
6663 	{"TSCCLRATEL", 0, 24},
6664 	{"CIM_CTL_12_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_LIMITER", 0x49e0, 0},
6667 	{"TSCCLRATEL", 0, 24},
6668 	{"CIM_CTL_13_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_LIMITER", 0x49f0, 0},
6671 	{"TSCCLRATEL", 0, 24},
6672 	{"CIM_CTL_14_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_LIMITER", 0x4a00, 0},
6675 	{"TSCCLRATEL", 0, 24},
6676 	{"CIM_CTL_15_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_LIMITER", 0x4a10, 0},
6679 	{"TSCCLRATEL", 0, 24},
6684 	{"CIM_CTL_0_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_PROPERTIES", 0x4924, 0},
6687 	{"TSCCLRINCR", 0, 14},
6688 	{"CIM_CTL_1_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_PROPERTIES", 0x4934, 0},
6691 	{"TSCCLRINCR", 0, 14},
6692 	{"CIM_CTL_2_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_PROPERTIES", 0x4944, 0},
6695 	{"TSCCLRINCR", 0, 14},
6696 	{"CIM_CTL_3_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_PROPERTIES", 0x4954, 0},
6699 	{"TSCCLRINCR", 0, 14},
6700 	{"CIM_CTL_4_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_PROPERTIES", 0x4964, 0},
6703 	{"TSCCLRINCR", 0, 14},
6704 	{"CIM_CTL_5_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_PROPERTIES", 0x4974, 0},
6707 	{"TSCCLRINCR", 0, 14},
6708 	{"CIM_CTL_6_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_PROPERTIES", 0x4984, 0},
6711 	{"TSCCLRINCR", 0, 14},
6712 	{"CIM_CTL_7_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_PROPERTIES", 0x4994, 0},
6715 	{"TSCCLRINCR", 0, 14},
6716 	{"CIM_CTL_8_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_PROPERTIES", 0x49a4, 0},
6719 	{"TSCCLRINCR", 0, 14},
6720 	{"CIM_CTL_9_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_PROPERTIES", 0x49b4, 0},
6723 	{"TSCCLRINCR", 0, 14},
6724 	{"CIM_CTL_10_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_PROPERTIES", 0x49c4, 0},
6727 	{"TSCCLRINCR", 0, 14},
6728 	{"CIM_CTL_11_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_PROPERTIES", 0x49d4, 0},
6731 	{"TSCCLRINCR", 0, 14},
6732 	{"CIM_CTL_12_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_PROPERTIES", 0x49e4, 0},
6735 	{"TSCCLRINCR", 0, 14},
6736 	{"CIM_CTL_13_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_PROPERTIES", 0x49f4, 0},
6739 	{"TSCCLRINCR", 0, 14},
6740 	{"CIM_CTL_14_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_PROPERTIES", 0x4a04, 0},
6743 	{"TSCCLRINCR", 0, 14},
6744 	{"CIM_CTL_15_TSCH_CLASS_TSCH_CHNLN_CLASSM_RATE_PROPERTIES", 0x4a14, 0},
6747 	{"TSCCLRINCR", 0, 14},
6752 	{"CIM_CTL_0_TSCH_CLASS_TSCH_CHNLN_CLASSM_WRR", 0x4928, 0},
6755 	{"TSCCLWRR", 0, 26},
6756 	{"CIM_CTL_1_TSCH_CLASS_TSCH_CHNLN_CLASSM_WRR", 0x4938, 0},
6759 	{"TSCCLWRR", 0, 26},
6760 	{"CIM_CTL_2_TSCH_CLASS_TSCH_CHNLN_CLASSM_WRR", 0x4948, 0},
6763 	{"TSCCLWRR", 0, 26},
6764 	{"CIM_CTL_3_TSCH_CLASS_TSCH_CHNLN_CLASSM_WRR", 0x4958, 0},
6767 	{"TSCCLWRR", 0, 26},
6768 	{"CIM_CTL_4_TSCH_CLASS_TSCH_CHNLN_CLASSM_WRR", 0x4968, 0},
6771 	{"TSCCLWRR", 0, 26},
6772 	{"CIM_CTL_5_TSCH_CLASS_TSCH_CHNLN_CLASSM_WRR", 0x4978, 0},
6775 	{"TSCCLWRR", 0, 26},
6776 	{"CIM_CTL_6_TSCH_CLASS_TSCH_CHNLN_CLASSM_WRR", 0x4988, 0},
6779 	{"TSCCLWRR", 0, 26},
6780 	{"CIM_CTL_7_TSCH_CLASS_TSCH_CHNLN_CLASSM_WRR", 0x4998, 0},
6783 	{"TSCCLWRR", 0, 26},
6784 	{"CIM_CTL_8_TSCH_CLASS_TSCH_CHNLN_CLASSM_WRR", 0x49a8, 0},
6787 	{"TSCCLWRR", 0, 26},
6788 	{"CIM_CTL_9_TSCH_CLASS_TSCH_CHNLN_CLASSM_WRR", 0x49b8, 0},
6791 	{"TSCCLWRR", 0, 26},
6792 	{"CIM_CTL_10_TSCH_CLASS_TSCH_CHNLN_CLASSM_WRR", 0x49c8, 0},
6795 	{"TSCCLWRR", 0, 26},
6796 	{"CIM_CTL_11_TSCH_CLASS_TSCH_CHNLN_CLASSM_WRR", 0x49d8, 0},
6799 	{"TSCCLWRR", 0, 26},
6800 	{"CIM_CTL_12_TSCH_CLASS_TSCH_CHNLN_CLASSM_WRR", 0x49e8, 0},
6803 	{"TSCCLWRR", 0, 26},
6804 	{"CIM_CTL_13_TSCH_CLASS_TSCH_CHNLN_CLASSM_WRR", 0x49f8, 0},
6807 	{"TSCCLWRR", 0, 26},
6808 	{"CIM_CTL_14_TSCH_CLASS_TSCH_CHNLN_CLASSM_WRR", 0x4a08, 0},
6811 	{"TSCCLWRR", 0, 26},
6812 	{"CIM_CTL_15_TSCH_CLASS_TSCH_CHNLN_CLASSM_WRR", 0x4a18, 0},
6815 	{"TSCCLWRR", 0, 26},
6820 	{"CIM_CTL_0_TSCH_CLASS_TSCH_CHNLN_CLASSM_WEIGHT", 0x492c, 0},
6823 	{"TSCCLWEIGHT", 0, 16},
6824 	{"CIM_CTL_1_TSCH_CLASS_TSCH_CHNLN_CLASSM_WEIGHT", 0x493c, 0},
6827 	{"TSCCLWEIGHT", 0, 16},
6828 	{"CIM_CTL_2_TSCH_CLASS_TSCH_CHNLN_CLASSM_WEIGHT", 0x494c, 0},
6831 	{"TSCCLWEIGHT", 0, 16},
6832 	{"CIM_CTL_3_TSCH_CLASS_TSCH_CHNLN_CLASSM_WEIGHT", 0x495c, 0},
6835 	{"TSCCLWEIGHT", 0, 16},
6836 	{"CIM_CTL_4_TSCH_CLASS_TSCH_CHNLN_CLASSM_WEIGHT", 0x496c, 0},
6839 	{"TSCCLWEIGHT", 0, 16},
6840 	{"CIM_CTL_5_TSCH_CLASS_TSCH_CHNLN_CLASSM_WEIGHT", 0x497c, 0},
6843 	{"TSCCLWEIGHT", 0, 16},
6844 	{"CIM_CTL_6_TSCH_CLASS_TSCH_CHNLN_CLASSM_WEIGHT", 0x498c, 0},
6847 	{"TSCCLWEIGHT", 0, 16},
6848 	{"CIM_CTL_7_TSCH_CLASS_TSCH_CHNLN_CLASSM_WEIGHT", 0x499c, 0},
6851 	{"TSCCLWEIGHT", 0, 16},
6852 	{"CIM_CTL_8_TSCH_CLASS_TSCH_CHNLN_CLASSM_WEIGHT", 0x49ac, 0},
6855 	{"TSCCLWEIGHT", 0, 16},
6856 	{"CIM_CTL_9_TSCH_CLASS_TSCH_CHNLN_CLASSM_WEIGHT", 0x49bc, 0},
6859 	{"TSCCLWEIGHT", 0, 16},
6860 	{"CIM_CTL_10_TSCH_CLASS_TSCH_CHNLN_CLASSM_WEIGHT", 0x49cc, 0},
6863 	{"TSCCLWEIGHT", 0, 16},
6864 	{"CIM_CTL_11_TSCH_CLASS_TSCH_CHNLN_CLASSM_WEIGHT", 0x49dc, 0},
6867 	{"TSCCLWEIGHT", 0, 16},
6868 	{"CIM_CTL_12_TSCH_CLASS_TSCH_CHNLN_CLASSM_WEIGHT", 0x49ec, 0},
6871 	{"TSCCLWEIGHT", 0, 16},
6872 	{"CIM_CTL_13_TSCH_CLASS_TSCH_CHNLN_CLASSM_WEIGHT", 0x49fc, 0},
6875 	{"TSCCLWEIGHT", 0, 16},
6876 	{"CIM_CTL_14_TSCH_CLASS_TSCH_CHNLN_CLASSM_WEIGHT", 0x4a0c, 0},
6879 	{"TSCCLWEIGHT", 0, 16},
6880 	{"CIM_CTL_15_TSCH_CLASS_TSCH_CHNLN_CLASSM_WEIGHT", 0x4a1c, 0},
6883 	{"TSCCLWEIGHT", 0, 16},
6888 	{"CIM_CTL_STATIC_ALLOCADDR12", 0x2080, 0},
6889 	{"StaticAllocAddr", 0, 32},
6890 	{"CIM_CTL_STATIC_ALLOCADDR13", 0x2084, 0},
6891 	{"StaticAllocAddr", 0, 32},
6892 	{"CIM_CTL_STATIC_ALLOCADDR14", 0x2088, 0},
6893 	{"StaticAllocAddr", 0, 32},
6894 	{"CIM_CTL_STATIC_ALLOCADDR15", 0x208c, 0},
6895 	{"StaticAllocAddr", 0, 32},
6896 	{"CIM_CTL_FIFO_CNT", 0x2090, 0},
6897 	{"CtlFifoCnt", 0, 4},
6898 	{"CIM_CTL_GLB_TIMER", 0x2094, 0},
6899 	{"GlblTimer", 0, 32},
6900 	{"CIM_CTL_TIMER0", 0x2098, 0},
6901 	{"Timer0", 0, 32},
6902 	{"CIM_CTL_TIMER1", 0x209c, 0},
6903 	{"Timer1", 0, 32},
6904 	{"CIM_CTL_GEN0", 0x20a0, 0},
6905 	{"Gen0", 0, 32},
6906 	{"CIM_CTL_GEN1", 0x20a4, 0},
6907 	{"Gen1", 0, 32},
6908 	{"CIM_CTL_GEN2", 0x20a8, 0},
6909 	{"Gen2", 0, 32},
6910 	{"CIM_CTL_GEN3", 0x20ac, 0},
6911 	{"Gen3", 0, 32},
6912 	{"CIM_CTL_GLB_TIMER_TICK", 0x20b0, 0},
6913 	{"GlblTTick", 0, 16},
6914 	{"CIM_CTL_GEN_TIMER0_CTL", 0x20b4, 0},
6920 	{"GenTimerStrt", 0, 1},
6921 	{"CIM_CTL_GEN_TIMER0", 0x20b8, 0},
6922 	{"GenTimer0", 0, 32},
6923 	{"CIM_CTL_GEN_TIMER1_CTL", 0x20bc, 0},
6929 	{"GenTimerStrt", 0, 1},
6930 	{"CIM_CTL_GEN_TIMER1", 0x20c0, 0},
6931 	{"GenTimer0", 0, 32},
6932 	{"CIM_CTL_GEN_TIMER2_CTL", 0x20c4, 0},
6938 	{"GenTimerStrt", 0, 1},
6939 	{"CIM_CTL_GEN_TIMER2", 0x20c8, 0},
6940 	{"GenTimer0", 0, 32},
6941 	{"CIM_CTL_GEN_TIMER3_CTL", 0x20cc, 0},
6947 	{"GenTimerStrt", 0, 1},
6948 	{"CIM_CTL_GEN_TIMER3", 0x20d0, 0},
6949 	{"GenTimer0", 0, 32},
6950 	{"CIM_CTL_0_MAILBOX_VF_STATUS", 0x20e0, 0},
6951 	{"MBVFStatus", 0, 32},
6952 	{"CIM_CTL_1_MAILBOX_VF_STATUS", 0x20e4, 0},
6953 	{"MBVFStatus", 0, 32},
6954 	{"CIM_CTL_2_MAILBOX_VF_STATUS", 0x20e8, 0},
6955 	{"MBVFStatus", 0, 32},
6956 	{"CIM_CTL_3_MAILBOX_VF_STATUS", 0x20ec, 0},
6957 	{"MBVFStatus", 0, 32},
6958 	{"CIM_CTL_4_MAILBOX_VF_STATUS", 0x20f0, 0},
6959 	{"MBVFStatus", 0, 32},
6960 	{"CIM_CTL_5_MAILBOX_VF_STATUS", 0x20f4, 0},
6961 	{"MBVFStatus", 0, 32},
6962 	{"CIM_CTL_6_MAILBOX_VF_STATUS", 0x20f8, 0},
6963 	{"MBVFStatus", 0, 32},
6964 	{"CIM_CTL_7_MAILBOX_VF_STATUS", 0x20fc, 0},
6965 	{"MBVFStatus", 0, 32},
6970 	{"CIM_CTL_STATIC_ALLOCADDR12", 0x2080, 0},
6971 	{"StaticAllocAddr", 0, 32},
6972 	{"CIM_CTL_STATIC_ALLOCADDR13", 0x2084, 0},
6973 	{"StaticAllocAddr", 0, 32},
6974 	{"CIM_CTL_STATIC_ALLOCADDR14", 0x2088, 0},
6975 	{"StaticAllocAddr", 0, 32},
6976 	{"CIM_CTL_STATIC_ALLOCADDR15", 0x208c, 0},
6977 	{"StaticAllocAddr", 0, 32},
6978 	{"CIM_CTL_FIFO_CNT", 0x2090, 0},
6979 	{"CtlFifoCnt", 0, 4},
6980 	{"CIM_CTL_GLB_TIMER", 0x2094, 0},
6981 	{"GlblTimer", 0, 32},
6982 	{"CIM_CTL_TIMER0", 0x2098, 0},
6983 	{"Timer0", 0, 32},
6984 	{"CIM_CTL_TIMER1", 0x209c, 0},
6985 	{"Timer1", 0, 32},
6986 	{"CIM_CTL_GEN0", 0x20a0, 0},
6987 	{"Gen0", 0, 32},
6988 	{"CIM_CTL_GEN1", 0x20a4, 0},
6989 	{"Gen1", 0, 32},
6990 	{"CIM_CTL_GEN2", 0x20a8, 0},
6991 	{"Gen2", 0, 32},
6992 	{"CIM_CTL_GEN3", 0x20ac, 0},
6993 	{"Gen3", 0, 32},
6994 	{"CIM_CTL_GLB_TIMER_TICK", 0x20b0, 0},
6995 	{"GlblTTick", 0, 16},
6996 	{"CIM_CTL_GEN_TIMER0_CTL", 0x20b4, 0},
7002 	{"GenTimerStrt", 0, 1},
7003 	{"CIM_CTL_GEN_TIMER0", 0x20b8, 0},
7004 	{"GenTimer0", 0, 32},
7005 	{"CIM_CTL_GEN_TIMER1_CTL", 0x20bc, 0},
7011 	{"GenTimerStrt", 0, 1},
7012 	{"CIM_CTL_GEN_TIMER1", 0x20c0, 0},
7013 	{"GenTimer0", 0, 32},
7014 	{"CIM_CTL_GEN_TIMER2_CTL", 0x20c4, 0},
7020 	{"GenTimerStrt", 0, 1},
7021 	{"CIM_CTL_GEN_TIMER2", 0x20c8, 0},
7022 	{"GenTimer0", 0, 32},
7023 	{"CIM_CTL_GEN_TIMER3_CTL", 0x20cc, 0},
7029 	{"GenTimerStrt", 0, 1},
7030 	{"CIM_CTL_GEN_TIMER3", 0x20d0, 0},
7031 	{"GenTimer0", 0, 32},
7032 	{"CIM_CTL_0_MAILBOX_VF_STATUS", 0x20e0, 0},
7033 	{"MBVFStatus", 0, 32},
7034 	{"CIM_CTL_1_MAILBOX_VF_STATUS", 0x20e4, 0},
7035 	{"MBVFStatus", 0, 32},
7036 	{"CIM_CTL_2_MAILBOX_VF_STATUS", 0x20e8, 0},
7037 	{"MBVFStatus", 0, 32},
7038 	{"CIM_CTL_3_MAILBOX_VF_STATUS", 0x20ec, 0},
7039 	{"MBVFStatus", 0, 32},
7044 	{"UP_IBQ_CONFIG", 0x0, 0},
7047 	{"IbqEn", 0, 1},
7048 	{"UP_OBQ_CONFIG", 0x4, 0},
7051 	{"ObqEn", 0, 1},
7052 	{"UP_IBQ_GEN", 0x8, 0},
7058 	{"IbqEmpty", 0, 6},
7059 	{"UP_OBQ_GEN", 0xc, 0},
7061 	{"ObqFull", 0, 8},
7062 	{"UP_IBQ_0_RDADDR", 0x10, 0},
7064 	{"QueRdAddr", 0, 13},
7065 	{"UP_IBQ_0_WRADDR", 0x14, 0},
7067 	{"QueWrAddr", 0, 13},
7068 	{"UP_IBQ_0_STATUS", 0x18, 0},
7070 	{"QueRemFlits", 0, 11},
7071 	{"UP_IBQ_0_PKTCNT", 0x1c, 0},
7073 	{"QueSOPCnt", 0, 12},
7074 	{"UP_IBQ_1_RDADDR", 0x20, 0},
7076 	{"UP_IBQ_1_WRADDR", 0x24, 0},
7078 	{"UP_IBQ_1_STATUS", 0x28, 0},
7080 	{"QueRemFlits", 0, 11},
7081 	{"UP_IBQ_1_PKTCNT", 0x2c, 0},
7083 	{"QueSOPCnt", 0, 12},
7084 	{"UP_IBQ_2_RDADDR", 0x30, 0},
7086 	{"UP_IBQ_2_WRADDR", 0x34, 0},
7088 	{"UP_IBQ_2_STATUS", 0x38, 0},
7089 	{"QueRemFlits", 0, 11},
7090 	{"UP_IBQ_2_PKTCNT", 0x3c, 0},
7092 	{"QueSOPCnt", 0, 12},
7093 	{"UP_IBQ_3_RDADDR", 0x40, 0},
7095 	{"UP_IBQ_3_WRADDR", 0x44, 0},
7097 	{"UP_IBQ_3_STATUS", 0x48, 0},
7098 	{"QueRemFlits", 0, 11},
7099 	{"UP_IBQ_3_PKTCNT", 0x4c, 0},
7101 	{"QueSOPCnt", 0, 12},
7102 	{"UP_IBQ_4_RDADDR", 0x50, 0},
7104 	{"UP_IBQ_4_WRADDR", 0x54, 0},
7106 	{"UP_IBQ_4_STATUS", 0x58, 0},
7107 	{"QueRemFlits", 0, 11},
7108 	{"UP_IBQ_4_PKTCNT", 0x5c, 0},
7110 	{"QueSOPCnt", 0, 12},
7111 	{"UP_IBQ_5_RDADDR", 0x60, 0},
7113 	{"UP_IBQ_5_WRADDR", 0x64, 0},
7115 	{"UP_IBQ_5_STATUS", 0x68, 0},
7116 	{"QueRemFlits", 0, 11},
7117 	{"UP_IBQ_5_PKTCNT", 0x6c, 0},
7119 	{"QueSOPCnt", 0, 12},
7120 	{"UP_OBQ_0_RDADDR", 0x70, 0},
7122 	{"QueRdAddr", 0, 15},
7123 	{"UP_OBQ_0_WRADDR", 0x74, 0},
7125 	{"QueWrAddr", 0, 15},
7126 	{"UP_OBQ_0_STATUS", 0x78, 0},
7127 	{"QueRemFlits", 0, 11},
7128 	{"UP_OBQ_0_PKTCNT", 0x7c, 0},
7130 	{"QueSOPCnt", 0, 12},
7135 	{"UP_OBQ_1_RDADDR", 0x80, 0},
7137 	{"QueRdAddr", 0, 15},
7138 	{"UP_OBQ_1_WRADDR", 0x84, 0},
7140 	{"QueWrAddr", 0, 15},
7141 	{"UP_OBQ_1_STATUS", 0x88, 0},
7142 	{"QueRemFlits", 0, 11},
7143 	{"UP_OBQ_1_PKTCNT", 0x8c, 0},
7145 	{"QueSOPCnt", 0, 12},
7146 	{"UP_OBQ_2_RDADDR", 0x90, 0},
7148 	{"QueRdAddr", 0, 15},
7149 	{"UP_OBQ_2_WRADDR", 0x94, 0},
7151 	{"QueWrAddr", 0, 15},
7152 	{"UP_OBQ_2_STATUS", 0x98, 0},
7153 	{"QueRemFlits", 0, 11},
7154 	{"UP_OBQ_2_PKTCNT", 0x9c, 0},
7156 	{"QueSOPCnt", 0, 12},
7157 	{"UP_OBQ_3_RDADDR", 0xa0, 0},
7159 	{"QueRdAddr", 0, 15},
7160 	{"UP_OBQ_3_WRADDR", 0xa4, 0},
7162 	{"QueWrAddr", 0, 15},
7163 	{"UP_OBQ_3_STATUS", 0xa8, 0},
7164 	{"QueRemFlits", 0, 11},
7165 	{"UP_OBQ_3_PKTCNT", 0xac, 0},
7167 	{"QueSOPCnt", 0, 12},
7168 	{"UP_OBQ_4_RDADDR", 0xb0, 0},
7170 	{"QueRdAddr", 0, 15},
7171 	{"UP_OBQ_4_WRADDR", 0xb4, 0},
7173 	{"QueWrAddr", 0, 15},
7174 	{"UP_OBQ_4_STATUS", 0xb8, 0},
7175 	{"QueRemFlits", 0, 11},
7176 	{"UP_OBQ_4_PKTCNT", 0xbc, 0},
7178 	{"QueSOPCnt", 0, 12},
7179 	{"UP_OBQ_5_RDADDR", 0xc0, 0},
7181 	{"QueRdAddr", 0, 15},
7182 	{"UP_OBQ_5_WRADDR", 0xc4, 0},
7184 	{"QueWrAddr", 0, 15},
7185 	{"UP_OBQ_5_STATUS", 0xc8, 0},
7186 	{"QueRemFlits", 0, 11},
7187 	{"UP_OBQ_5_PKTCNT", 0xcc, 0},
7189 	{"QueSOPCnt", 0, 12},
7190 	{"UP_IBQ_0_CONFIG", 0xd0, 0},
7195 	{"QueBareAddr", 0, 1},
7196 	{"UP_IBQ_0_REALADDR", 0xd4, 0},
7200 	{"UP_IBQ_1_CONFIG", 0xd8, 0},
7205 	{"QueBareAddr", 0, 1},
7206 	{"UP_IBQ_1_REALADDR", 0xdc, 0},
7210 	{"UP_IBQ_2_CONFIG", 0xe0, 0},
7215 	{"QueBareAddr", 0, 1},
7216 	{"UP_IBQ_2_REALADDR", 0xe4, 0},
7220 	{"UP_IBQ_3_CONFIG", 0xe8, 0},
7225 	{"QueBareAddr", 0, 1},
7226 	{"UP_IBQ_3_REALADDR", 0xec, 0},
7230 	{"UP_IBQ_4_CONFIG", 0xf0, 0},
7235 	{"QueBareAddr", 0, 1},
7236 	{"UP_IBQ_4_REALADDR", 0xf4, 0},
7240 	{"UP_IBQ_5_CONFIG", 0xf8, 0},
7245 	{"QueBareAddr", 0, 1},
7246 	{"UP_IBQ_5_REALADDR", 0xfc, 0},
7254 	{"UP_OBQ_1_RDADDR", 0x80, 0},
7256 	{"QueRdAddr", 0, 15},
7257 	{"UP_OBQ_1_WRADDR", 0x84, 0},
7259 	{"QueWrAddr", 0, 15},
7260 	{"UP_OBQ_1_STATUS", 0x88, 0},
7261 	{"QueRemFlits", 0, 11},
7262 	{"UP_OBQ_1_PKTCNT", 0x8c, 0},
7264 	{"QueSOPCnt", 0, 12},
7265 	{"UP_OBQ_2_RDADDR", 0x90, 0},
7267 	{"QueRdAddr", 0, 15},
7268 	{"UP_OBQ_2_WRADDR", 0x94, 0},
7270 	{"QueWrAddr", 0, 15},
7271 	{"UP_OBQ_2_STATUS", 0x98, 0},
7272 	{"QueRemFlits", 0, 11},
7273 	{"UP_OBQ_2_PKTCNT", 0x9c, 0},
7275 	{"QueSOPCnt", 0, 12},
7276 	{"UP_OBQ_3_RDADDR", 0xa0, 0},
7278 	{"QueRdAddr", 0, 15},
7279 	{"UP_OBQ_3_WRADDR", 0xa4, 0},
7281 	{"QueWrAddr", 0, 15},
7282 	{"UP_OBQ_3_STATUS", 0xa8, 0},
7283 	{"QueRemFlits", 0, 11},
7284 	{"UP_OBQ_3_PKTCNT", 0xac, 0},
7286 	{"QueSOPCnt", 0, 12},
7287 	{"UP_OBQ_4_RDADDR", 0xb0, 0},
7289 	{"QueRdAddr", 0, 15},
7290 	{"UP_OBQ_4_WRADDR", 0xb4, 0},
7292 	{"QueWrAddr", 0, 15},
7293 	{"UP_OBQ_4_STATUS", 0xb8, 0},
7294 	{"QueRemFlits", 0, 11},
7295 	{"UP_OBQ_4_PKTCNT", 0xbc, 0},
7297 	{"QueSOPCnt", 0, 12},
7298 	{"UP_OBQ_5_RDADDR", 0xc0, 0},
7300 	{"QueRdAddr", 0, 15},
7301 	{"UP_OBQ_5_WRADDR", 0xc4, 0},
7303 	{"QueWrAddr", 0, 15},
7304 	{"UP_OBQ_5_STATUS", 0xc8, 0},
7305 	{"QueRemFlits", 0, 11},
7306 	{"UP_OBQ_5_PKTCNT", 0xcc, 0},
7308 	{"QueSOPCnt", 0, 12},
7309 	{"UP_IBQ_0_CONFIG", 0xd0, 0},
7313 	{"QueBareAddr", 0, 1},
7314 	{"UP_IBQ_0_REALADDR", 0xd4, 0},
7318 	{"UP_IBQ_1_CONFIG", 0xd8, 0},
7322 	{"QueBareAddr", 0, 1},
7323 	{"UP_IBQ_1_REALADDR", 0xdc, 0},
7327 	{"UP_IBQ_2_CONFIG", 0xe0, 0},
7331 	{"QueBareAddr", 0, 1},
7332 	{"UP_IBQ_2_REALADDR", 0xe4, 0},
7336 	{"UP_IBQ_3_CONFIG", 0xe8, 0},
7340 	{"QueBareAddr", 0, 1},
7341 	{"UP_IBQ_3_REALADDR", 0xec, 0},
7345 	{"UP_IBQ_4_CONFIG", 0xf0, 0},
7349 	{"QueBareAddr", 0, 1},
7350 	{"UP_IBQ_4_REALADDR", 0xf4, 0},
7354 	{"UP_IBQ_5_CONFIG", 0xf8, 0},
7358 	{"QueBareAddr", 0, 1},
7359 	{"UP_IBQ_5_REALADDR", 0xfc, 0},
7367 	{"UP_OBQ_0_CONFIG", 0x100, 0},
7371 	{"QueBareAddr", 0, 1},
7372 	{"UP_OBQ_0_REALADDR", 0x104, 0},
7374 	{"UP_OBQ_1_CONFIG", 0x108, 0},
7378 	{"QueBareAddr", 0, 1},
7379 	{"UP_OBQ_1_REALADDR", 0x10c, 0},
7381 	{"UP_OBQ_2_CONFIG", 0x110, 0},
7385 	{"QueBareAddr", 0, 1},
7386 	{"UP_OBQ_2_REALADDR", 0x114, 0},
7388 	{"UP_OBQ_3_CONFIG", 0x118, 0},
7392 	{"QueBareAddr", 0, 1},
7393 	{"UP_OBQ_3_REALADDR", 0x11c, 0},
7395 	{"UP_OBQ_4_CONFIG", 0x120, 0},
7399 	{"QueBareAddr", 0, 1},
7400 	{"UP_OBQ_4_REALADDR", 0x124, 0},
7402 	{"UP_OBQ_5_CONFIG", 0x128, 0},
7406 	{"QueBareAddr", 0, 1},
7407 	{"UP_OBQ_5_REALADDR", 0x12c, 0},
7409 	{"UP_MAILBOX_STATUS", 0x130, 0},
7413 	{"MBPFInt", 0, 8},
7414 	{"UP_UP_DBG_LA_CFG", 0x140, 0},
7423 	{"UpDbgLaEn", 0, 1},
7424 	{"UP_UP_DBG_LA_DATA", 0x144, 0},
7425 	{"UpDbgLaWrData", 0, 32},
7426 	{"UP_PIO_MST_CONFIG", 0x148, 0},
7434 	{"UP_UP_SELF_CONTROL", 0x14c, 0},
7435 	{"UpSelfReset", 0, 1},
7440 	{"UP_OBQ_0_CONFIG", 0x100, 0},
7444 	{"QueBareAddr", 0, 1},
7445 	{"UP_OBQ_0_REALADDR", 0x104, 0},
7447 	{"UP_OBQ_1_CONFIG", 0x108, 0},
7451 	{"QueBareAddr", 0, 1},
7452 	{"UP_OBQ_1_REALADDR", 0x10c, 0},
7454 	{"UP_OBQ_2_CONFIG", 0x110, 0},
7458 	{"QueBareAddr", 0, 1},
7459 	{"UP_OBQ_2_REALADDR", 0x114, 0},
7461 	{"UP_OBQ_3_CONFIG", 0x118, 0},
7465 	{"QueBareAddr", 0, 1},
7466 	{"UP_OBQ_3_REALADDR", 0x11c, 0},
7468 	{"UP_OBQ_4_CONFIG", 0x120, 0},
7472 	{"QueBareAddr", 0, 1},
7473 	{"UP_OBQ_4_REALADDR", 0x124, 0},
7475 	{"UP_OBQ_5_CONFIG", 0x128, 0},
7479 	{"QueBareAddr", 0, 1},
7480 	{"UP_OBQ_5_REALADDR", 0x12c, 0},
7482 	{"UP_MAILBOX_STATUS", 0x130, 0},
7486 	{"MBPFInt", 0, 8},
7487 	{"UP_UP_DBG_LA_CFG", 0x140, 0},
7496 	{"UpDbgLaEn", 0, 1},
7497 	{"UP_UP_DBG_LA_DATA", 0x144, 0},
7498 	{"UpDbgLaWrData", 0, 32},
7499 	{"UP_PIO_MST_CONFIG", 0x148, 0},
7507 	{"UpRID", 0, 8},
7508 	{"UP_UP_SELF_CONTROL", 0x14c, 0},
7509 	{"UpSelfReset", 0, 1},
7514 	{"UP_TSCH_CHANNEL0_TSCH_CHNLn_CLASS_RDY", 0x200, 0},
7515 	{"TSCHCHNLCRDY", 0, 32},
7516 	{"UP_TSCH_CHANNEL0_TSCH_CHNLn_CLASS_WATCH_RDY", 0x204, 0},
7518 	{"TSCHCHNLCWRDY", 0, 16},
7519 	{"UP_TSCH_CHANNEL0_TSCH_CHNLn_CLASS_WATCH_LIST", 0x208, 0},
7521 	{"TSCHCHNLCWATCH", 0, 16},
7522 	{"UP_TSCH_CHANNEL0_TSCH_CHNLn_CLASS_TAKE", 0x20c, 0},
7527 	{"TSCHCHNLCCNT", 0, 24},
7528 	{"UP_TSCH_CHANNEL1_TSCH_CHNLn_CLASS_RDY", 0x210, 0},
7529 	{"TSCHCHNLCRDY", 0, 32},
7530 	{"UP_TSCH_CHANNEL1_TSCH_CHNLn_CLASS_WATCH_RDY", 0x214, 0},
7532 	{"TSCHCHNLCWRDY", 0, 16},
7533 	{"UP_TSCH_CHANNEL1_TSCH_CHNLn_CLASS_WATCH_LIST", 0x218, 0},
7535 	{"TSCHCHNLCWATCH", 0, 16},
7536 	{"UP_TSCH_CHANNEL1_TSCH_CHNLn_CLASS_TAKE", 0x21c, 0},
7541 	{"TSCHCHNLCCNT", 0, 24},
7542 	{"UP_TSCH_CHANNEL2_TSCH_CHNLn_CLASS_RDY", 0x220, 0},
7543 	{"TSCHCHNLCRDY", 0, 32},
7544 	{"UP_TSCH_CHANNEL2_TSCH_CHNLn_CLASS_WATCH_RDY", 0x224, 0},
7546 	{"TSCHCHNLCWRDY", 0, 16},
7547 	{"UP_TSCH_CHANNEL2_TSCH_CHNLn_CLASS_WATCH_LIST", 0x228, 0},
7549 	{"TSCHCHNLCWATCH", 0, 16},
7550 	{"UP_TSCH_CHANNEL2_TSCH_CHNLn_CLASS_TAKE", 0x22c, 0},
7555 	{"TSCHCHNLCCNT", 0, 24},
7556 	{"UP_TSCH_CHANNEL3_TSCH_CHNLn_CLASS_RDY", 0x230, 0},
7557 	{"TSCHCHNLCRDY", 0, 32},
7558 	{"UP_TSCH_CHANNEL3_TSCH_CHNLn_CLASS_WATCH_RDY", 0x234, 0},
7560 	{"TSCHCHNLCWRDY", 0, 16},
7561 	{"UP_TSCH_CHANNEL3_TSCH_CHNLn_CLASS_WATCH_LIST", 0x238, 0},
7563 	{"TSCHCHNLCWATCH", 0, 16},
7564 	{"UP_TSCH_CHANNEL3_TSCH_CHNLn_CLASS_TAKE", 0x23c, 0},
7569 	{"TSCHCHNLCCNT", 0, 24},
7574 	{"UP_TSCH_CHANNEL0_TSCH_CHNLn_CLASS_RDY", 0x200, 0},
7577 	{"TSCHCHNLCRDY", 0, 30},
7578 	{"UP_TSCH_CHANNEL0_TSCH_CHNLn_CLASS_WATCH_RDY", 0x204, 0},
7580 	{"TSCHCHNLCWRDY", 0, 16},
7581 	{"UP_TSCH_CHANNEL0_TSCH_CHNLn_CLASS_WATCH_LIST", 0x208, 0},
7583 	{"TSCHCHNLCWATCH", 0, 16},
7584 	{"UP_TSCH_CHANNEL0_TSCH_CHNLn_CLASS_TAKE", 0x20c, 0},
7586 	{"TSCHCHNLCCNT", 0, 24},
7587 	{"UP_TSCH_CHANNEL1_TSCH_CHNLn_CLASS_RDY", 0x210, 0},
7590 	{"TSCHCHNLCRDY", 0, 30},
7591 	{"UP_TSCH_CHANNEL1_TSCH_CHNLn_CLASS_WATCH_RDY", 0x214, 0},
7593 	{"TSCHCHNLCWRDY", 0, 16},
7594 	{"UP_TSCH_CHANNEL1_TSCH_CHNLn_CLASS_WATCH_LIST", 0x218, 0},
7596 	{"TSCHCHNLCWATCH", 0, 16},
7597 	{"UP_TSCH_CHANNEL1_TSCH_CHNLn_CLASS_TAKE", 0x21c, 0},
7599 	{"TSCHCHNLCCNT", 0, 24},
7600 	{"UP_TSCH_CHANNEL2_TSCH_CHNLn_CLASS_RDY", 0x220, 0},
7603 	{"TSCHCHNLCRDY", 0, 30},
7604 	{"UP_TSCH_CHANNEL2_TSCH_CHNLn_CLASS_WATCH_RDY", 0x224, 0},
7606 	{"TSCHCHNLCWRDY", 0, 16},
7607 	{"UP_TSCH_CHANNEL2_TSCH_CHNLn_CLASS_WATCH_LIST", 0x228, 0},
7609 	{"TSCHCHNLCWATCH", 0, 16},
7610 	{"UP_TSCH_CHANNEL2_TSCH_CHNLn_CLASS_TAKE", 0x22c, 0},
7612 	{"TSCHCHNLCCNT", 0, 24},
7613 	{"UP_TSCH_CHANNEL3_TSCH_CHNLn_CLASS_RDY", 0x230, 0},
7616 	{"TSCHCHNLCRDY", 0, 30},
7617 	{"UP_TSCH_CHANNEL3_TSCH_CHNLn_CLASS_WATCH_RDY", 0x234, 0},
7619 	{"TSCHCHNLCWRDY", 0, 16},
7620 	{"UP_TSCH_CHANNEL3_TSCH_CHNLn_CLASS_WATCH_LIST", 0x238, 0},
7622 	{"TSCHCHNLCWATCH", 0, 16},
7623 	{"UP_TSCH_CHANNEL3_TSCH_CHNLn_CLASS_TAKE", 0x23c, 0},
7625 	{"TSCHCHNLCCNT", 0, 24},
7631 	{"UP_UpLaDbgPcChkData_0", 0x240, 0},
7632 	{"UpLaPcData", 0, 32},
7633 	{"UP_UpLaDbgPcChkMask_0", 0x244, 0},
7634 	{"UpLaPcMask", 0, 32},
7639 	{"UP_UpLaDbgPcChkData_1", 0x250, 0},
7640 	{"UpLaPcData", 0, 32},
7641 	{"UP_UpLaDbgPcChkMask_1", 0x254, 0},
7642 	{"UpLaPcMask", 0, 32},
7647 	{"UP_UpLaDbgPcChkData_2", 0x260, 0},
7648 	{"UpLaPcData", 0, 32},
7649 	{"UP_UpLaDbgPcChkMask_2", 0x264, 0},
7650 	{"UpLaPcMask", 0, 32},
7655 	{"UP_UpLaDbgPcChkData_3", 0x270, 0},
7656 	{"UpLaPcData", 0, 32},
7657 	{"UP_UpLaDbgPcChkMask_3", 0x274, 0},
7658 	{"UpLaPcMask", 0, 32},
7663 	{"UP_IBQ_0_SHADOW_RDADDR", 0x280, 0},
7665 	{"QueRdAddr", 0, 13},
7666 	{"UP_IBQ_0_SHADOW_WRADDR", 0x284, 0},
7668 	{"QueWrAddr", 0, 13},
7669 	{"UP_IBQ_0_SHADOW_STATUS", 0x288, 0},
7671 	{"QueRemFlits", 0, 11},
7672 	{"UP_IBQ_0_SHADOW_PKTCNT", 0x28c, 0},
7674 	{"QueSOPCnt", 0, 12},
7675 	{"UP_IBQ_1_SHADOW_RDADDR", 0x290, 0},
7677 	{"UP_IBQ_1_SHADOW_WRADDR", 0x294, 0},
7679 	{"UP_IBQ_1_SHADOW_STATUS", 0x298, 0},
7681 	{"QueRemFlits", 0, 11},
7682 	{"UP_IBQ_1_SHADOW_PKTCNT", 0x29c, 0},
7684 	{"QueSOPCnt", 0, 12},
7685 	{"UP_IBQ_2_SHADOW_RDADDR", 0x2a0, 0},
7687 	{"UP_IBQ_2_SHADOW_WRADDR", 0x2a4, 0},
7689 	{"UP_IBQ_2_SHADOW_STATUS", 0x2a8, 0},
7690 	{"QueRemFlits", 0, 11},
7691 	{"UP_IBQ_2_SHADOW_PKTCNT", 0x2ac, 0},
7693 	{"QueSOPCnt", 0, 12},
7694 	{"UP_IBQ_3_SHADOW_RDADDR", 0x2b0, 0},
7696 	{"UP_IBQ_3_SHADOW_WRADDR", 0x2b4, 0},
7698 	{"UP_IBQ_3_SHADOW_STATUS", 0x2b8, 0},
7699 	{"QueRemFlits", 0, 11},
7700 	{"UP_IBQ_3_SHADOW_PKTCNT", 0x2bc, 0},
7702 	{"QueSOPCnt", 0, 12},
7703 	{"UP_IBQ_4_SHADOW_RDADDR", 0x2c0, 0},
7705 	{"UP_IBQ_4_SHADOW_WRADDR", 0x2c4, 0},
7707 	{"UP_IBQ_4_SHADOW_STATUS", 0x2c8, 0},
7708 	{"QueRemFlits", 0, 11},
7709 	{"UP_IBQ_4_SHADOW_PKTCNT", 0x2cc, 0},
7711 	{"QueSOPCnt", 0, 12},
7712 	{"UP_IBQ_5_SHADOW_RDADDR", 0x2d0, 0},
7714 	{"UP_IBQ_5_SHADOW_WRADDR", 0x2d4, 0},
7716 	{"UP_IBQ_5_SHADOW_STATUS", 0x2d8, 0},
7717 	{"QueRemFlits", 0, 11},
7718 	{"UP_IBQ_5_SHADOW_PKTCNT", 0x2dc, 0},
7720 	{"QueSOPCnt", 0, 12},
7721 	{"UP_OBQ_0_SHADOW_RDADDR", 0x2e0, 0},
7723 	{"QueRdAddr", 0, 15},
7724 	{"UP_OBQ_0_SHADOW_WRADDR", 0x2e4, 0},
7726 	{"QueWrAddr", 0, 15},
7727 	{"UP_OBQ_0_SHADOW_STATUS", 0x2e8, 0},
7728 	{"QueRemFlits", 0, 11},
7729 	{"UP_OBQ_0_SHADOW_PKTCNT", 0x2ec, 0},
7731 	{"QueSOPCnt", 0, 12},
7732 	{"UP_OBQ_1_SHADOW_RDADDR", 0x2f0, 0},
7734 	{"QueRdAddr", 0, 15},
7735 	{"UP_OBQ_1_SHADOW_WRADDR", 0x2f4, 0},
7737 	{"QueWrAddr", 0, 15},
7738 	{"UP_OBQ_1_SHADOW_STATUS", 0x2f8, 0},
7739 	{"QueRemFlits", 0, 11},
7740 	{"UP_OBQ_1_SHADOW_PKTCNT", 0x2fc, 0},
7742 	{"QueSOPCnt", 0, 12},
7747 	{"UP_OBQ_2_SHADOW_RDADDR", 0x300, 0},
7749 	{"QueRdAddr", 0, 15},
7750 	{"UP_OBQ_2_SHADOW_WRADDR", 0x304, 0},
7752 	{"QueWrAddr", 0, 15},
7753 	{"UP_OBQ_2_SHADOW_STATUS", 0x308, 0},
7754 	{"QueRemFlits", 0, 11},
7755 	{"UP_OBQ_2_SHADOW_PKTCNT", 0x30c, 0},
7757 	{"QueSOPCnt", 0, 12},
7758 	{"UP_OBQ_3_SHADOW_RDADDR", 0x310, 0},
7760 	{"QueRdAddr", 0, 15},
7761 	{"UP_OBQ_3_SHADOW_WRADDR", 0x314, 0},
7763 	{"QueWrAddr", 0, 15},
7764 	{"UP_OBQ_3_SHADOW_STATUS", 0x318, 0},
7765 	{"QueRemFlits", 0, 11},
7766 	{"UP_OBQ_3_SHADOW_PKTCNT", 0x31c, 0},
7768 	{"QueSOPCnt", 0, 12},
7769 	{"UP_OBQ_4_SHADOW_RDADDR", 0x320, 0},
7771 	{"QueRdAddr", 0, 15},
7772 	{"UP_OBQ_4_SHADOW_WRADDR", 0x324, 0},
7774 	{"QueWrAddr", 0, 15},
7775 	{"UP_OBQ_4_SHADOW_STATUS", 0x328, 0},
7776 	{"QueRemFlits", 0, 11},
7777 	{"UP_OBQ_4_SHADOW_PKTCNT", 0x32c, 0},
7779 	{"QueSOPCnt", 0, 12},
7780 	{"UP_OBQ_5_SHADOW_RDADDR", 0x330, 0},
7782 	{"QueRdAddr", 0, 15},
7783 	{"UP_OBQ_5_SHADOW_WRADDR", 0x334, 0},
7785 	{"QueWrAddr", 0, 15},
7786 	{"UP_OBQ_5_SHADOW_STATUS", 0x338, 0},
7787 	{"QueRemFlits", 0, 11},
7788 	{"UP_OBQ_5_SHADOW_PKTCNT", 0x33c, 0},
7790 	{"QueSOPCnt", 0, 12},
7791 	{"UP_OBQ_6_SHADOW_RDADDR", 0x340, 0},
7793 	{"QueRdAddr", 0, 15},
7794 	{"UP_OBQ_6_SHADOW_WRADDR", 0x344, 0},
7796 	{"QueWrAddr", 0, 15},
7797 	{"UP_OBQ_6_SHADOW_STATUS", 0x348, 0},
7798 	{"QueRemFlits", 0, 11},
7799 	{"UP_OBQ_6_SHADOW_PKTCNT", 0x34c, 0},
7801 	{"QueSOPCnt", 0, 12},
7802 	{"UP_OBQ_7_SHADOW_RDADDR", 0x350, 0},
7804 	{"QueRdAddr", 0, 15},
7805 	{"UP_OBQ_7_SHADOW_WRADDR", 0x354, 0},
7807 	{"QueWrAddr", 0, 15},
7808 	{"UP_OBQ_7_SHADOW_STATUS", 0x358, 0},
7809 	{"QueRemFlits", 0, 11},
7810 	{"UP_OBQ_7_SHADOW_PKTCNT", 0x35c, 0},
7812 	{"QueSOPCnt", 0, 12},
7813 	{"UP_IBQ_0_SHADOW_CONFIG", 0x360, 0},
7817 	{"QueBareAddr", 0, 1},
7818 	{"UP_IBQ_0_SHADOW_REALADDR", 0x364, 0},
7822 	{"UP_IBQ_1_SHADOW_CONFIG", 0x368, 0},
7826 	{"QueBareAddr", 0, 1},
7827 	{"UP_IBQ_1_SHADOW_REALADDR", 0x36c, 0},
7831 	{"UP_IBQ_2_SHADOW_CONFIG", 0x370, 0},
7835 	{"QueBareAddr", 0, 1},
7836 	{"UP_IBQ_2_SHADOW_REALADDR", 0x374, 0},
7840 	{"UP_IBQ_3_SHADOW_CONFIG", 0x378, 0},
7844 	{"QueBareAddr", 0, 1},
7845 	{"UP_IBQ_3_SHADOW_REALADDR", 0x37c, 0},
7853 	{"UP_IBQ_4_SHADOW_CONFIG", 0x380, 0},
7857 	{"QueBareAddr", 0, 1},
7858 	{"UP_IBQ_4_SHADOW_REALADDR", 0x384, 0},
7862 	{"UP_IBQ_5_SHADOW_CONFIG", 0x388, 0},
7866 	{"QueBareAddr", 0, 1},
7867 	{"UP_IBQ_5_SHADOW_REALADDR", 0x38c, 0},
7871 	{"UP_OBQ_0_SHADOW_CONFIG", 0x390, 0},
7875 	{"QueBareAddr", 0, 1},
7876 	{"UP_OBQ_0_SHADOW_REALADDR", 0x394, 0},
7878 	{"UP_OBQ_1_SHADOW_CONFIG", 0x398, 0},
7882 	{"QueBareAddr", 0, 1},
7883 	{"UP_OBQ_1_SHADOW_REALADDR", 0x39c, 0},
7885 	{"UP_OBQ_2_SHADOW_CONFIG", 0x3a0, 0},
7889 	{"QueBareAddr", 0, 1},
7890 	{"UP_OBQ_2_SHADOW_REALADDR", 0x3a4, 0},
7892 	{"UP_OBQ_3_SHADOW_CONFIG", 0x3a8, 0},
7896 	{"QueBareAddr", 0, 1},
7897 	{"UP_OBQ_3_SHADOW_REALADDR", 0x3ac, 0},
7899 	{"UP_OBQ_4_SHADOW_CONFIG", 0x3b0, 0},
7903 	{"QueBareAddr", 0, 1},
7904 	{"UP_OBQ_4_SHADOW_REALADDR", 0x3b4, 0},
7906 	{"UP_OBQ_5_SHADOW_CONFIG", 0x3b8, 0},
7910 	{"QueBareAddr", 0, 1},
7911 	{"UP_OBQ_5_SHADOW_REALADDR", 0x3bc, 0},
7913 	{"UP_OBQ_6_SHADOW_CONFIG", 0x3c0, 0},
7917 	{"QueBareAddr", 0, 1},
7918 	{"UP_OBQ_6_SHADOW_REALADDR", 0x3c4, 0},
7920 	{"UP_OBQ_7_SHADOW_CONFIG", 0x3c8, 0},
7924 	{"QueBareAddr", 0, 1},
7925 	{"UP_OBQ_7_SHADOW_REALADDR", 0x3cc, 0},