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/linux/Documentation/devicetree/bindings/powerpc/fsl/
H A Ddiu.txt20 reg = <0x2c000 100>;
28 reg = <0x2100 0x100>;
29 interrupts = <64 0x8>;
/linux/arch/powerpc/boot/dts/fsl/
H A Db4si-post.dtsi37 alloc-ranges = <0 0 0x10000 0>;
42 alloc-ranges = <0 0 0x10000 0>;
47 alloc-ranges = <0 0 0x10000 0>;
54 interrupts = <25 2 0 0>;
57 /* controller at 0x200000 */
63 bus-range = <0x0 0xff>;
64 interrupts = <20 2 0 0>;
66 pcie@0 {
71 reg = <0 0 0 0 0>;
72 interrupts = <20 2 0 0>;
[all …]
H A Dt2081si-post.dtsi37 alloc-ranges = <0 0 0x10000 0>;
42 alloc-ranges = <0 0 0x10000 0>;
47 alloc-ranges = <0 0 0x10000 0>;
54 interrupts = <25 2 0 0>;
57 /* controller at 0x240000 */
59 compatible = "fsl,t2080-pcie", "fsl,qoriq-pcie-v3.0", "fsl,qoriq-pcie";
63 bus-range = <0x0 0xff>;
64 interrupts = <20 2 0 0>;
66 pcie@0 {
67 reg = <0 0 0 0 0>;
[all …]
H A Dt4240si-post.dtsi37 alloc-ranges = <0 0 0x10000 0>;
42 alloc-ranges = <0 0 0x10000 0>;
47 alloc-ranges = <0 0 0x10000 0>;
54 interrupts = <25 2 0 0>;
57 /* controller at 0x240000 */
59 compatible = "fsl,t4240-pcie", "fsl,qoriq-pcie-v3.0";
63 bus-range = <0x0 0xff>;
64 interrupts = <20 2 0 0>;
65 pcie@0 {
70 reg = <0 0 0 0 0>;
[all …]
/linux/drivers/gpu/drm/msm/disp/dpu1/catalog/
H A Ddpu_9_1_sar2130p.h12 .max_mixer_blendstages = 0xb,
23 .base = 0, .len = 0x494,
25 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
32 .base = 0x15000, .len = 0x290,
36 .base = 0x16000, .len = 0x290,
40 .base = 0x17000, .len = 0x290,
44 .base = 0x18000, .len = 0x290,
48 .base = 0x19000, .len = 0x290,
52 .base = 0x1a000, .len = 0x290,
60 .base = 0x4000, .len = 0x344,
[all …]
H A Ddpu_9_0_sm8550.h12 .max_mixer_blendstages = 0xb,
23 .base = 0, .len = 0x494,
25 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
32 .base = 0x15000, .len = 0x290,
36 .base = 0x16000, .len = 0x290,
40 .base = 0x17000, .len = 0x290,
44 .base = 0x18000, .len = 0x290,
48 .base = 0x19000, .len = 0x290,
52 .base = 0x1a000, .len = 0x290,
60 .base = 0x4000, .len = 0x344,
[all …]
H A Ddpu_9_2_x1e80100.h11 .max_mixer_blendstages = 0xb,
22 .base = 0, .len = 0x494,
24 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
31 .base = 0x15000, .len = 0x290,
35 .base = 0x16000, .len = 0x290,
39 .base = 0x17000, .len = 0x290,
43 .base = 0x18000, .len = 0x290,
47 .base = 0x19000, .len = 0x290,
51 .base = 0x1a000, .len = 0x290,
59 .base = 0x4000, .len = 0x344,
[all …]
/linux/include/linux/soundwire/
H A Dsdw_intel.h15 #define SDW_SHIM_BASE 0x2C000
16 #define SDW_ALH_BASE 0x2C800
17 #define SDW_SHIM_BASE_ACE 0x38000
18 #define SDW_ALH_BASE_ACE 0x24000
19 #define SDW_LINK_BASE 0x30000
20 #define SDW_LINK_SIZE 0x10000
24 #define SDW_SHIM_LCAP 0x0
25 #define SDW_SHIM_LCAP_LCOUNT_MASK GENMASK(2, 0)
29 #define SDW_SHIM_LCTL 0x4
31 #define SDW_SHIM_LCTL_SPA BIT(0)
[all …]
/linux/drivers/clk/qcom/
H A Dgcc-sdx55.c33 { 249600000, 2000000000, 0 },
37 .offset = 0x0,
42 .enable_reg = 0x6d000,
43 .enable_mask = BIT(0),
56 { 0x0, 1 },
57 { 0x1, 2 },
58 { 0x3, 4 },
59 { 0x7, 8 },
64 .offset = 0x0,
81 .offset = 0x76000,
[all …]
H A Dnegcc-nord.c46 .offset = 0x0,
49 .enable_reg = 0x0,
50 .enable_mask = BIT(0),
63 { 0x1, 2 },
68 .offset = 0x0,
85 .offset = 0x2000,
88 .enable_reg = 0x0,
102 { P_BI_TCXO, 0 },
112 { P_BI_TCXO, 0 },
124 { P_BI_TCXO, 0 },
[all …]
H A Dgcc-ipq5424.c55 .offset = 0x20000,
58 .enable_reg = 0xb000,
59 .enable_mask = BIT(0),
83 .offset = 0x20000,
97 .offset = 0x21000,
100 .enable_reg = 0xb000,
112 { 0x1, 2 },
117 .offset = 0x21000,
132 .offset = 0x22000,
135 .enable_reg = 0xb000,
[all …]
H A Dgcc-msm8916.c45 .l_reg = 0x21004,
46 .m_reg = 0x21008,
47 .n_reg = 0x2100c,
48 .config_reg = 0x21010,
49 .mode_reg = 0x21000,
50 .status_reg = 0x2101c,
63 .enable_reg = 0x45000,
64 .enable_mask = BIT(0),
76 .l_reg = 0x20004,
77 .m_reg = 0x20008,
[all …]
H A Dgcc-msm8996.c49 .offset = 0x00000,
52 .enable_reg = 0x52000,
53 .enable_mask = BIT(0),
79 .offset = 0x00000,
94 .enable_reg = 0x5200c,
95 .enable_mask = BIT(0),
111 .enable_reg = 0x5200c,
126 .offset = 0x77000,
129 .enable_reg = 0x52000,
143 .offset = 0x77000,
[all …]
H A Dgcc-ipq5332.c52 .offset = 0x20000,
55 .enable_reg = 0xb000,
56 .enable_mask = BIT(0),
79 .offset = 0x20000,
92 .offset = 0x21000,
95 .enable_reg = 0xb000,
107 .offset = 0x21000,
120 .offset = 0x22000,
123 .enable_reg = 0xb000,
135 .offset = 0x22000,
[all …]
H A Dgcc-msm8998.c27 #define GCC_MMSS_MISC 0x0902C
28 #define GCC_GPU_MISC 0x71028
31 { 250000000, 2000000000, 0 },
36 .offset = 0x0,
41 .enable_reg = 0x52000,
42 .enable_mask = BIT(0),
55 .offset = 0x0,
68 .offset = 0x0,
81 .offset = 0x0,
94 .offset = 0x0,
[all …]
H A Dgcc-ipq5018.c61 .offset = 0x21000,
64 .enable_reg = 0x0b000,
65 .enable_mask = BIT(0),
76 .offset = 0x4a000,
79 .enable_reg = 0x0b000,
91 .offset = 0x24000,
94 .enable_reg = 0x0b000,
106 .offset = 0x25000,
109 .enable_reg = 0x0b000,
121 .offset = 0x21000,
[all …]
H A Dgcc-ipq9650.c51 .offset = 0x20000,
54 .enable_reg = 0xb000,
55 .enable_mask = BIT(0),
79 .offset = 0x20000,
92 .offset = 0x21000,
95 .enable_reg = 0xb000,
107 { 0x1, 2 },
112 .offset = 0x21000,
129 .offset = 0x22000,
132 .enable_reg = 0xb000,
[all …]
/linux/drivers/rapidio/devices/
H A Dtsi721.h13 DBG_NONE = 0,
14 DBG_INIT = BIT(0), /* driver init */
26 DBG_ALL = ~0,
36 } while (0)
53 #define DEFAULT_HOPCOUNT 0xff
54 #define DEFAULT_DESTID 0xff
57 #define PCI_DEVICE_ID_TSI721 0x80ab
59 #define BAR_0 0
67 #define TSI721_MAINT_WIN 0 /* Window for outbound maintenance requests */
68 #define IDB_QUEUE 0 /* Inbound Doorbell Queue to use */
[all …]
/linux/drivers/interconnect/qcom/
H A Dmilos.c142 .port_offsets = { 0xc000 },
144 .urg_fwd = 0,
159 .port_offsets = { 0xf200 },
161 .urg_fwd = 0,
176 .port_offsets = { 0x10000 },
178 .urg_fwd = 0,
193 .port_offsets = { 0x14000 },
195 .urg_fwd = 0,
210 .port_offsets = { 0x12000 },
212 .urg_fwd = 0,
[all …]
H A Dkaanapali.c458 .port_offsets = { 0x14e000 },
459 .prio = 0,
461 .prio_fwd_disable = 0,
473 .port_offsets = { 0x145000 },
475 .urg_fwd = 0,
516 .port_offsets = { 0x13d000 },
518 .urg_fwd = 0,
531 .port_offsets = { 0x13f000 },
533 .urg_fwd = 0,
555 .port_offsets = { 0x31000, 0xb1000 },
[all …]
H A Dsm8650.c159 .port_offsets = { 0xc000 },
161 .urg_fwd = 0,
162 .prio_fwd_disable = 0,
176 .port_offsets = { 0xd000 },
178 .urg_fwd = 0,
179 .prio_fwd_disable = 0,
201 .port_offsets = { 0xe000 },
203 .urg_fwd = 0,
204 .prio_fwd_disable = 0,
218 .port_offsets = { 0xf000 },
[all …]
H A Dglymur.c652 .port_offsets = { 0x33000 },
653 .prio = 0,
655 .prio_fwd_disable = 0,
694 .port_offsets = { 0x933000 },
696 .urg_fwd = 0,
709 .port_offsets = { 0x51f000 },
711 .urg_fwd = 0,
724 .port_offsets = { 0x51f080 },
726 .urg_fwd = 0,
748 .port_offsets = { 0x934000 },
[all …]
H A Dsc8280xp.c220 .port_offsets = { 0x5000 },
233 .port_offsets = { 0x6000 },
246 .port_offsets = { 0xc000 },
267 .port_offsets = { 0x8000 },
281 .port_offsets = { 0xd000 },
294 .port_offsets = { 0x7000 },
307 .port_offsets = { 0x9000 },
320 .port_offsets = { 0xb000 },
333 .port_offsets = { 0xa000 },
346 .port_offsets = { 0xe000 },
[all …]
/linux/tools/perf/util/
H A Dmachine.c63 machine->pid) < 0) in machine__set_mmap_name()
66 return machine->mmap_name ? 0 : -ENOMEM;
74 thread__set_comm(thread, comm, 0);
81 memset(machine, 0, sizeof(*machine)); in machine__init()
95 machine->id_hdr_size = 0; in machine__init()
98 machine->kernel_start = 0; in machine__init()
122 err = 0; in machine__init()
140 if (machine__init(machine, "", HOST_KERNEL_ID) != 0) { in __machine__new_host()
145 if (kernel_maps && machine__create_kernel_maps(machine) < 0) { in __machine__new_host()
170 memset(&event, 0, sizeo in machine__init_live()
[all...]
/linux/arch/arm64/boot/dts/qcom/
H A Dsm8650.dtsi42 #clock-cells = <0>;
47 #clock-cells = <0>;
52 #clock-cells = <0>;
61 #clock-cells = <0>;
71 #size-cells = <0>;
73 cpu0: cpu@0 {
76 reg = <0 0>;
83 clocks = <&cpufreq_hw 0>;
93 qcom,freq-domain = <&cpufreq_hw 0>;
127 reg = <0 0x100>;
[all …]

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