Lines Matching +full:0 +full:x2c000
53 .offset = 0x20000,
56 .enable_reg = 0xb000,
57 .enable_mask = BIT(0),
80 .offset = 0x20000,
93 .offset = 0x21000,
96 .enable_reg = 0xb000,
108 .offset = 0x21000,
121 .offset = 0x22000,
124 .enable_reg = 0xb000,
136 .offset = 0x22000,
149 { P_XO, 0 },
153 { P_XO, 0 },
165 { P_XO, 0 },
175 { P_XO, 0 },
187 { P_XO, 0 },
201 { P_XO, 0 },
215 { P_XO, 0 },
229 { P_XO, 0 },
245 { P_XO, 0 },
257 { P_XO, 0 },
279 { P_XO, 0 },
293 { P_XO, 0 },
305 { P_XO, 0 },
319 F(24000000, P_XO, 1, 0, 0),
320 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
325 .cmd_rcgr = 0x1c004,
326 .mnd_width = 0,
339 F(480000000, P_GPLL4_OUT_AUX, 2.5, 0, 0),
340 F(533333333, P_GPLL0_OUT_MAIN, 1.5, 0, 0),
346 F(4800000, P_XO, 5, 0, 0),
347 F(9600000, P_XO, 2.5, 0, 0),
349 F(24000000, P_XO, 1, 0, 0),
351 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
356 .cmd_rcgr = 0x2004,
370 .cmd_rcgr = 0x3004,
384 .cmd_rcgr = 0x4004,
401 F(24000000, P_XO, 1, 0, 0),
411 F(64000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0),
416 .cmd_rcgr = 0x202c,
430 .cmd_rcgr = 0x302c,
444 .cmd_rcgr = 0x402c,
458 F(24000000, P_XO, 1, 0, 0),
459 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
464 .cmd_rcgr = 0x8004,
478 .cmd_rcgr = 0x9004,
492 F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0),
497 .cmd_rcgr = 0x27004,
498 .mnd_width = 0,
511 F(24000000, P_XO, 1, 0, 0),
516 .cmd_rcgr = 0x17088,
517 .mnd_width = 0,
530 F(240000000, P_GPLL4_OUT_MAIN, 5, 0, 0),
535 .cmd_rcgr = 0x29018,
536 .mnd_width = 0,
549 .cmd_rcgr = 0x2907c,
562 .halt_reg = 0x2907c,
564 .enable_reg = 0x2907c,
578 .cmd_rcgr = 0x2a004,
579 .mnd_width = 0,
592 .cmd_rcgr = 0x2a078,
605 .halt_reg = 0x2a078,
607 .enable_reg = 0x2a078,
621 F(266666667, P_GPLL4_OUT_MAIN, 4.5, 0, 0),
626 .cmd_rcgr = 0x28018,
627 .mnd_width = 0,
640 .cmd_rcgr = 0x28084,
641 .mnd_width = 0,
654 .cmd_rcgr = 0x28078,
655 .mnd_width = 0,
668 .halt_reg = 0x28078,
670 .enable_reg = 0x28078,
684 F(2000000, P_XO, 12, 0, 0),
689 .cmd_rcgr = 0x28004,
703 .reg = 0x28064,
717 .reg = 0x29064,
731 .reg = 0x2a064,
745 F(24000000, P_XO, 1, 0, 0),
746 F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),
747 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
752 .cmd_rcgr = 0x31004,
753 .mnd_width = 0,
766 .cmd_rcgr = 0x25004,
767 .mnd_width = 0,
780 F(240000000, P_GPLL4_OUT_MAIN, 5, 0, 0),
785 .cmd_rcgr = 0x2d004,
786 .mnd_width = 0,
799 F(600000000, P_GPLL4_OUT_MAIN, 2, 0, 0),
804 .cmd_rcgr = 0x2d01c,
805 .mnd_width = 0,
879 F(24000000, P_XO, 1, 0, 0),
880 F(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),
881 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
882 F(320000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
887 .cmd_rcgr = 0x32004,
888 .mnd_width = 0,
903 F(24000000, P_XO, 1, 0, 0),
905 F(96000000, P_GPLL2_OUT_MAIN, 12, 0, 0),
906 F(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0),
907 F(192000000, P_GPLL2_OUT_MAIN, 6, 0, 0),
908 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
913 .cmd_rcgr = 0x33004,
927 F(32000, P_SLEEP_CLK, 1, 0, 0),
932 .cmd_rcgr = 0x3400c,
933 .mnd_width = 0,
946 F(24000000, P_XO, 1, 0, 0),
947 F(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0),
948 F(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
949 F(266666667, P_GPLL4_OUT_MAIN, 4.5, 0, 0),
954 .cmd_rcgr = 0x2e004,
955 .mnd_width = 0,
981 .cmd_rcgr = 0x16004,
982 .mnd_width = 0,
995 .cmd_rcgr = 0x2c018,
1014 .cmd_rcgr = 0x2c07c,
1028 .cmd_rcgr = 0x2c004,
1047 .cmd_rcgr = 0x2c02c,
1061 .reg = 0x2c074,
1075 .cmd_rcgr = 0x25030,
1076 .mnd_width = 0,
1089 .cmd_rcgr = 0x34004,
1090 .mnd_width = 0,
1116 .reg = 0x2d028,
1117 .shift = 0,
1130 .reg = 0x2c040,
1131 .shift = 0,
1145 .halt_reg = 0x1c00c,
1148 .enable_reg = 0x1c00c,
1149 .enable_mask = BIT(0),
1163 .halt_reg = 0x34024,
1166 .enable_reg = 0x34024,
1167 .enable_mask = BIT(0),
1181 .halt_reg = 0x1008,
1184 .enable_reg = 0xb004,
1199 .halt_reg = 0x2024,
1202 .enable_reg = 0x2024,
1203 .enable_mask = BIT(0),
1217 .halt_reg = 0x2020,
1220 .enable_reg = 0x2020,
1221 .enable_mask = BIT(0),
1235 .halt_reg = 0x3024,
1238 .enable_reg = 0x3024,
1239 .enable_mask = BIT(0),
1253 .halt_reg = 0x3020,
1256 .enable_reg = 0x3020,
1257 .enable_mask = BIT(0),
1271 .halt_reg = 0x4024,
1274 .enable_reg = 0x4024,
1275 .enable_mask = BIT(0),
1289 .halt_reg = 0x4020,
1292 .enable_reg = 0x4020,
1293 .enable_mask = BIT(0),
1307 .halt_reg = 0x1010,
1310 .enable_reg = 0xb004,
1325 .halt_reg = 0x2040,
1328 .enable_reg = 0x2040,
1329 .enable_mask = BIT(0),
1343 .halt_reg = 0x3040,
1346 .enable_reg = 0x3040,
1347 .enable_mask = BIT(0),
1361 .halt_reg = 0x4054,
1364 .enable_reg = 0x4054,
1365 .enable_mask = BIT(0),
1379 .halt_reg = 0x25074,
1382 .enable_reg = 0x25074,
1383 .enable_mask = BIT(0),
1397 .halt_reg = 0x25068,
1400 .enable_reg = 0x25068,
1401 .enable_mask = BIT(0),
1415 .halt_reg = 0x25070,
1418 .enable_reg = 0x25070,
1419 .enable_mask = BIT(0),
1433 .halt_reg = 0x3a004,
1436 .enable_reg = 0x3a004,
1437 .enable_mask = BIT(0),
1451 .halt_reg = 0x3a00c,
1454 .enable_reg = 0x3a00c,
1455 .enable_mask = BIT(0),
1469 .halt_reg = 0x3a008,
1472 .enable_reg = 0x3a008,
1473 .enable_mask = BIT(0),
1487 .halt_reg = 0x8018,
1490 .enable_reg = 0x8018,
1491 .enable_mask = BIT(0),
1505 .halt_reg = 0x9018,
1508 .enable_reg = 0x9018,
1509 .enable_mask = BIT(0),
1523 .halt_reg = 0x27018,
1526 .enable_reg = 0x27018,
1527 .enable_mask = BIT(0),
1541 .halt_reg = 0x27014,
1544 .enable_reg = 0x27014,
1545 .enable_mask = BIT(0),
1559 .halt_reg = 0x12004,
1562 .enable_reg = 0x12004,
1563 .enable_mask = BIT(0),
1577 .halt_reg = 0x1200c,
1580 .enable_reg = 0x1200c,
1581 .enable_mask = BIT(0),
1595 .halt_reg = 0x17018,
1598 .enable_reg = 0x17018,
1599 .enable_mask = BIT(0),
1613 .halt_reg = 0x17034,
1616 .enable_reg = 0x17034,
1617 .enable_mask = BIT(0),
1631 .halt_reg = 0x1702c,
1634 .enable_reg = 0x1702c,
1635 .enable_mask = BIT(0),
1649 .halt_reg = 0x17014,
1652 .enable_reg = 0x17014,
1653 .enable_mask = BIT(0),
1667 .halt_reg = 0x17030,
1670 .enable_reg = 0x17030,
1671 .enable_mask = BIT(0),
1685 .halt_reg = 0x1701c,
1688 .enable_reg = 0x1701c,
1689 .enable_mask = BIT(0),
1703 .halt_reg = 0x1707c,
1706 .enable_reg = 0x1707c,
1707 .enable_mask = BIT(0),
1721 .halt_reg = 0x17028,
1724 .enable_reg = 0x17028,
1725 .enable_mask = BIT(0),
1739 .halt_reg = 0x17020,
1742 .enable_reg = 0x17020,
1743 .enable_mask = BIT(0),
1757 .halt_reg = 0x17074,
1760 .enable_reg = 0x17074,
1761 .enable_mask = BIT(0),
1775 .halt_reg = 0x29030,
1778 .enable_reg = 0x29030,
1779 .enable_mask = BIT(0),
1793 .halt_reg = 0x29070,
1796 .enable_reg = 0x29070,
1797 .enable_mask = BIT(0),
1811 .halt_reg = 0x29038,
1814 .enable_reg = 0x29038,
1815 .enable_mask = BIT(0),
1829 .halt_reg = 0x29048,
1832 .enable_reg = 0x29048,
1833 .enable_mask = BIT(0),
1847 .halt_reg = 0x29040,
1850 .enable_reg = 0x29040,
1851 .enable_mask = BIT(0),
1865 .halt_reg = 0x29068,
1868 .enable_reg = 0x29068,
1869 .enable_mask = BIT(0),
1883 .halt_reg = 0x2a00c,
1886 .enable_reg = 0x2a00c,
1887 .enable_mask = BIT(0),
1901 .halt_reg = 0x2a070,
1904 .enable_reg = 0x2a070,
1905 .enable_mask = BIT(0),
1919 .halt_reg = 0x2a014,
1922 .enable_reg = 0x2a014,
1923 .enable_mask = BIT(0),
1937 .halt_reg = 0x2a024,
1940 .enable_reg = 0x2a024,
1941 .enable_mask = BIT(0),
1955 .halt_reg = 0x2a01c,
1958 .enable_reg = 0x2a01c,
1959 .enable_mask = BIT(0),
1973 .halt_reg = 0x2a068,
1976 .enable_reg = 0x2a068,
1977 .enable_mask = BIT(0),
1991 .halt_reg = 0x29078,
1994 .enable_reg = 0x29078,
1995 .enable_mask = BIT(0),
2009 .halt_reg = 0x28030,
2012 .enable_reg = 0x28030,
2013 .enable_mask = BIT(0),
2027 .halt_reg = 0x28070,
2030 .enable_reg = 0x28070,
2031 .enable_mask = BIT(0),
2045 .halt_reg = 0x28038,
2048 .enable_reg = 0x28038,
2049 .enable_mask = BIT(0),
2063 .halt_reg = 0x28048,
2066 .enable_reg = 0x28048,
2067 .enable_mask = BIT(0),
2081 .halt_reg = 0x28040,
2084 .enable_reg = 0x28040,
2085 .enable_mask = BIT(0),
2099 .halt_reg = 0x28080,
2102 .enable_reg = 0x28080,
2103 .enable_mask = BIT(0),
2117 .halt_reg = 0x28068,
2120 .enable_reg = 0x28068,
2121 .enable_mask = BIT(0),
2135 .halt_reg = 0x31024,
2138 .enable_reg = 0x31024,
2139 .enable_mask = BIT(0),
2153 .halt_reg = 0x31020,
2156 .enable_reg = 0x31020,
2157 .enable_mask = BIT(0),
2171 .halt_reg = 0x13024,
2174 .enable_reg = 0xb004,
2189 .halt_reg = 0x2d038,
2192 .enable_reg = 0x2d038,
2193 .enable_mask = BIT(0),
2207 .halt_reg = 0x2d06c,
2210 .enable_reg = 0x2d06c,
2211 .enable_mask = BIT(0),
2225 .halt_reg = 0x2d068,
2228 .enable_reg = 0x2d068,
2229 .enable_mask = BIT(0),
2243 .halt_reg = 0x2d05c,
2246 .enable_reg = 0xb004,
2261 .halt_reg = 0x2d064,
2264 .enable_reg = 0x2d064,
2265 .enable_mask = BIT(0),
2292 .halt_reg = 0x2d070,
2295 .enable_reg = 0x2d070,
2296 .enable_mask = BIT(0),
2310 .halt_reg = 0x32010,
2313 .enable_reg = 0x32010,
2314 .enable_mask = BIT(0),
2328 .halt_reg = 0x32014,
2331 .enable_reg = 0x32014,
2332 .enable_mask = BIT(0),
2346 .halt_reg = 0x3200c,
2349 .enable_reg = 0x3200c,
2350 .enable_mask = BIT(0),
2364 .halt_reg = 0x3201c,
2367 .enable_reg = 0x3201c,
2368 .enable_mask = BIT(0),
2382 .halt_reg = 0x33034,
2385 .enable_reg = 0x33034,
2386 .enable_mask = BIT(0),
2400 .halt_reg = 0x3302c,
2403 .enable_reg = 0x3302c,
2404 .enable_mask = BIT(0),
2418 .halt_reg = 0x2e028,
2421 .enable_reg = 0x2e028,
2422 .enable_mask = BIT(0),
2436 .halt_reg = 0x17090,
2439 .enable_reg = 0x17090,
2440 .enable_mask = BIT(0),
2454 .halt_reg = 0x17084,
2457 .enable_reg = 0x17084,
2458 .enable_mask = BIT(0),
2472 .halt_reg = 0x2e050,
2475 .enable_reg = 0x2e050,
2476 .enable_mask = BIT(0),
2490 .halt_reg = 0x2e0ac,
2493 .enable_reg = 0x2e0ac,
2494 .enable_mask = BIT(0),
2508 .halt_reg = 0x2e080,
2511 .enable_reg = 0x2e080,
2512 .enable_mask = BIT(0),
2526 .halt_reg = 0x2e04c,
2529 .enable_reg = 0x2e04c,
2530 .enable_mask = BIT(0),
2544 .halt_reg = 0x2e07c,
2547 .enable_reg = 0x2e07c,
2548 .enable_mask = BIT(0),
2562 .halt_reg = 0x2e048,
2565 .enable_reg = 0x2e048,
2566 .enable_mask = BIT(0),
2580 .halt_reg = 0x2e058,
2583 .enable_reg = 0x2e058,
2584 .enable_mask = BIT(0),
2598 .halt_reg = 0x2e038,
2601 .enable_reg = 0x2e038,
2602 .enable_mask = BIT(0),
2616 .halt_reg = 0x16010,
2619 .enable_reg = 0x16010,
2620 .enable_mask = BIT(0),
2634 .halt_reg = 0x1600c,
2637 .enable_reg = 0x1600c,
2638 .enable_mask = BIT(0),
2652 .halt_reg = 0x1601c,
2655 .enable_reg = 0x1601c,
2656 .enable_mask = BIT(0),
2670 .halt_reg = 0x16018,
2673 .enable_reg = 0x16018,
2674 .enable_mask = BIT(0),
2688 .halt_reg = 0x2c050,
2691 .enable_reg = 0x2c050,
2692 .enable_mask = BIT(0),
2706 .halt_reg = 0x30004,
2709 .enable_reg = 0x30004,
2710 .enable_mask = BIT(0),
2724 .halt_reg = 0x2c090,
2727 .enable_reg = 0x2c090,
2728 .enable_mask = BIT(0),
2742 .halt_reg = 0x2c048,
2745 .enable_reg = 0x2c048,
2746 .enable_mask = BIT(0),
2760 .halt_reg = 0x2c054,
2762 .enable_reg = 0x2c054,
2763 .enable_mask = BIT(0),
2777 .halt_reg = 0x2c05c,
2780 .enable_reg = 0x2c05c,
2781 .enable_mask = BIT(0),
2795 .halt_reg = 0x2c078,
2798 .enable_reg = 0x2c078,
2799 .enable_mask = BIT(0),
2813 .halt_reg = 0x2c058,
2816 .enable_reg = 0x2c058,
2817 .enable_mask = BIT(0),
2831 .halt_reg = 0x34018,
2834 .enable_reg = 0x34018,
2835 .enable_mask = BIT(0),
2849 .halt_reg = 0x3401c,
2852 .enable_reg = 0x3401c,
2853 .enable_mask = BIT(0),
2867 .halt_reg = 0x34020,
2870 .enable_reg = 0x34020,
2871 .enable_mask = BIT(0),
2885 .halt_reg = 0x17080,
2888 .enable_reg = 0x17080,
2889 .enable_mask = BIT(0),
2903 .reg = 0x2e010,
2904 .shift = 0,
3068 [GCC_ADSS_BCR] = { 0x1c000 },
3069 [GCC_ADSS_PWM_CLK_ARES] = { 0x1c00c, 2 },
3070 [GCC_AHB_CLK_ARES] = { 0x34024, 2 },
3071 [GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x38000 },
3072 [GCC_APC0_VOLTAGE_DROOP_DETECTOR_GPLL0_CLK_ARES] = { 0x3800c, 2 },
3073 [GCC_APSS_AHB_CLK_ARES] = { 0x24018, 2 },
3074 [GCC_APSS_AXI_CLK_ARES] = { 0x2401c, 2 },
3075 [GCC_BLSP1_AHB_CLK_ARES] = { 0x1008, 2 },
3076 [GCC_BLSP1_BCR] = { 0x1000 },
3077 [GCC_BLSP1_QUP1_BCR] = { 0x2000 },
3078 [GCC_BLSP1_QUP1_I2C_APPS_CLK_ARES] = { 0x2024, 2 },
3079 [GCC_BLSP1_QUP1_SPI_APPS_CLK_ARES] = { 0x2020, 2 },
3080 [GCC_BLSP1_QUP2_BCR] = { 0x3000 },
3081 [GCC_BLSP1_QUP2_I2C_APPS_CLK_ARES] = { 0x3024, 2 },
3082 [GCC_BLSP1_QUP2_SPI_APPS_CLK_ARES] = { 0x3020, 2 },
3083 [GCC_BLSP1_QUP3_BCR] = { 0x4000 },
3084 [GCC_BLSP1_QUP3_I2C_APPS_CLK_ARES] = { 0x4024, 2 },
3085 [GCC_BLSP1_QUP3_SPI_APPS_CLK_ARES] = { 0x4020, 2 },
3086 [GCC_BLSP1_SLEEP_CLK_ARES] = { 0x1010, 2 },
3087 [GCC_BLSP1_UART1_APPS_CLK_ARES] = { 0x2040, 2 },
3088 [GCC_BLSP1_UART1_BCR] = { 0x2028 },
3089 [GCC_BLSP1_UART2_APPS_CLK_ARES] = { 0x3040, 2 },
3090 [GCC_BLSP1_UART2_BCR] = { 0x3028 },
3091 [GCC_BLSP1_UART3_APPS_CLK_ARES] = { 0x4054, 2 },
3092 [GCC_BLSP1_UART3_BCR] = { 0x4028 },
3093 [GCC_CE_BCR] = { 0x18008 },
3094 [GCC_CMN_BLK_BCR] = { 0x3a000 },
3095 [GCC_CMN_LDO0_BCR] = { 0x1d000 },
3096 [GCC_CMN_LDO1_BCR] = { 0x1d008 },
3097 [GCC_DCC_BCR] = { 0x35000 },
3098 [GCC_GP1_CLK_ARES] = { 0x8018, 2 },
3099 [GCC_GP2_CLK_ARES] = { 0x9018, 2 },
3100 [GCC_LPASS_BCR] = { 0x27000 },
3101 [GCC_LPASS_CORE_AXIM_CLK_ARES] = { 0x27018, 2 },
3102 [GCC_LPASS_SWAY_CLK_ARES] = { 0x27014, 2 },
3103 [GCC_MDIOM_BCR] = { 0x12000 },
3104 [GCC_MDIOS_BCR] = { 0x12008 },
3105 [GCC_NSS_BCR] = { 0x17000 },
3106 [GCC_NSS_TS_CLK_ARES] = { 0x17018, 2 },
3107 [GCC_NSSCC_CLK_ARES] = { 0x17034, 2 },
3108 [GCC_NSSCFG_CLK_ARES] = { 0x1702c, 2 },
3109 [GCC_NSSNOC_ATB_CLK_ARES] = { 0x17014, 2 },
3110 [GCC_NSSNOC_NSSCC_CLK_ARES] = { 0x17030, 2 },
3111 [GCC_NSSNOC_QOSGEN_REF_CLK_ARES] = { 0x1701c, 2 },
3112 [GCC_NSSNOC_SNOC_1_CLK_ARES] = { 0x1707c, 2 },
3113 [GCC_NSSNOC_SNOC_CLK_ARES] = { 0x17028, 2 },
3114 [GCC_NSSNOC_TIMEOUT_REF_CLK_ARES] = { 0x17020, 2 },
3115 [GCC_NSSNOC_XO_DCD_CLK_ARES] = { 0x17074, 2 },
3116 [GCC_PCIE3X1_0_AHB_CLK_ARES] = { 0x29030, 2 },
3117 [GCC_PCIE3X1_0_AUX_CLK_ARES] = { 0x29070, 2 },
3118 [GCC_PCIE3X1_0_AXI_M_CLK_ARES] = { 0x29038, 2 },
3119 [GCC_PCIE3X1_0_AXI_S_BRIDGE_CLK_ARES] = { 0x29048, 2 },
3120 [GCC_PCIE3X1_0_AXI_S_CLK_ARES] = { 0x29040, 2 },
3121 [GCC_PCIE3X1_0_BCR] = { 0x29000 },
3122 [GCC_PCIE3X1_0_LINK_DOWN_BCR] = { 0x29054 },
3123 [GCC_PCIE3X1_0_PHY_BCR] = { 0x29060 },
3124 [GCC_PCIE3X1_0_PHY_PHY_BCR] = { 0x2905c },
3125 [GCC_PCIE3X1_1_AHB_CLK_ARES] = { 0x2a00c, 2 },
3126 [GCC_PCIE3X1_1_AUX_CLK_ARES] = { 0x2a070, 2 },
3127 [GCC_PCIE3X1_1_AXI_M_CLK_ARES] = { 0x2a014, 2 },
3128 [GCC_PCIE3X1_1_AXI_S_BRIDGE_CLK_ARES] = { 0x2a024, 2 },
3129 [GCC_PCIE3X1_1_AXI_S_CLK_ARES] = { 0x2a01c, 2 },
3130 [GCC_PCIE3X1_1_BCR] = { 0x2a000 },
3131 [GCC_PCIE3X1_1_LINK_DOWN_BCR] = { 0x2a028 },
3132 [GCC_PCIE3X1_1_PHY_BCR] = { 0x2a030 },
3133 [GCC_PCIE3X1_1_PHY_PHY_BCR] = { 0x2a02c },
3134 [GCC_PCIE3X1_PHY_AHB_CLK_ARES] = { 0x29078, 2 },
3135 [GCC_PCIE3X2_AHB_CLK_ARES] = { 0x28030, 2 },
3136 [GCC_PCIE3X2_AUX_CLK_ARES] = { 0x28070, 2 },
3137 [GCC_PCIE3X2_AXI_M_CLK_ARES] = { 0x28038, 2 },
3138 [GCC_PCIE3X2_AXI_S_BRIDGE_CLK_ARES] = { 0x28048, 2 },
3139 [GCC_PCIE3X2_AXI_S_CLK_ARES] = { 0x28040, 2 },
3140 [GCC_PCIE3X2_BCR] = { 0x28000 },
3141 [GCC_PCIE3X2_LINK_DOWN_BCR] = { 0x28054 },
3142 [GCC_PCIE3X2_PHY_AHB_CLK_ARES] = { 0x28080, 2 },
3143 [GCC_PCIE3X2_PHY_BCR] = { 0x28060 },
3144 [GCC_PCIE3X2PHY_PHY_BCR] = { 0x2805c },
3145 [GCC_PCNOC_BCR] = { 0x31000 },
3146 [GCC_PCNOC_LPASS_CLK_ARES] = { 0x31020, 2 },
3147 [GCC_PRNG_AHB_CLK_ARES] = { 0x13024, 2 },
3148 [GCC_PRNG_BCR] = { 0x13020 },
3149 [GCC_Q6_AHB_CLK_ARES] = { 0x25014, 2 },
3150 [GCC_Q6_AHB_S_CLK_ARES] = { 0x25018, 2 },
3151 [GCC_Q6_AXIM_CLK_ARES] = { 0x2500c, 2 },
3152 [GCC_Q6_AXIS_CLK_ARES] = { 0x25010, 2 },
3153 [GCC_Q6_TSCTR_1TO2_CLK_ARES] = { 0x25020, 2 },
3154 [GCC_Q6SS_ATBM_CLK_ARES] = { 0x2501c, 2 },
3155 [GCC_Q6SS_PCLKDBG_CLK_ARES] = { 0x25024, 2 },
3156 [GCC_Q6SS_TRIG_CLK_ARES] = { 0x250a0, 2 },
3157 [GCC_QDSS_APB2JTAG_CLK_ARES] = { 0x2d060, 2 },
3158 [GCC_QDSS_AT_CLK_ARES] = { 0x2d038, 2 },
3159 [GCC_QDSS_BCR] = { 0x2d000 },
3160 [GCC_QDSS_CFG_AHB_CLK_ARES] = { 0x2d06c, 2 },
3161 [GCC_QDSS_DAP_AHB_CLK_ARES] = { 0x2d068, 2 },
3162 [GCC_QDSS_DAP_CLK_ARES] = { 0x2d05c, 2 },
3163 [GCC_QDSS_ETR_USB_CLK_ARES] = { 0x2d064, 2 },
3164 [GCC_QDSS_EUD_AT_CLK_ARES] = { 0x2d070, 2 },
3165 [GCC_QDSS_STM_CLK_ARES] = { 0x2d040, 2 },
3166 [GCC_QDSS_TRACECLKIN_CLK_ARES] = { 0x2d044, 2 },
3167 [GCC_QDSS_TS_CLK_ARES] = { 0x2d078, 2 },
3168 [GCC_QDSS_TSCTR_DIV16_CLK_ARES] = { 0x2d058, 2 },
3169 [GCC_QDSS_TSCTR_DIV2_CLK_ARES] = { 0x2d048, 2 },
3170 [GCC_QDSS_TSCTR_DIV3_CLK_ARES] = { 0x2d04c, 2 },
3171 [GCC_QDSS_TSCTR_DIV4_CLK_ARES] = { 0x2d050, 2 },
3172 [GCC_QDSS_TSCTR_DIV8_CLK_ARES] = { 0x2d054, 2 },
3173 [GCC_QPIC_AHB_CLK_ARES] = { 0x32010, 2 },
3174 [GCC_QPIC_CLK_ARES] = { 0x32014, 2 },
3175 [GCC_QPIC_BCR] = { 0x32000 },
3176 [GCC_QPIC_IO_MACRO_CLK_ARES] = { 0x3200c, 2 },
3177 [GCC_QPIC_SLEEP_CLK_ARES] = { 0x3201c, 2 },
3178 [GCC_QUSB2_0_PHY_BCR] = { 0x2c068 },
3179 [GCC_SDCC1_AHB_CLK_ARES] = { 0x33034, 2 },
3180 [GCC_SDCC1_APPS_CLK_ARES] = { 0x3302c, 2 },
3181 [GCC_SDCC_BCR] = { 0x33000 },
3182 [GCC_SNOC_BCR] = { 0x2e000 },
3183 [GCC_SNOC_LPASS_CFG_CLK_ARES] = { 0x2e028, 2 },
3184 [GCC_SNOC_NSSNOC_1_CLK_ARES] = { 0x17090, 2 },
3185 [GCC_SNOC_NSSNOC_CLK_ARES] = { 0x17084, 2 },
3186 [GCC_SYS_NOC_QDSS_STM_AXI_CLK_ARES] = { 0x2e034, 2 },
3187 [GCC_SYS_NOC_WCSS_AHB_CLK_ARES] = { 0x2e030, 2 },
3188 [GCC_UNIPHY0_AHB_CLK_ARES] = { 0x16010, 2 },
3189 [GCC_UNIPHY0_BCR] = { 0x16000 },
3190 [GCC_UNIPHY0_SYS_CLK_ARES] = { 0x1600c, 2 },
3191 [GCC_UNIPHY1_AHB_CLK_ARES] = { 0x1601c, 2 },
3192 [GCC_UNIPHY1_BCR] = { 0x16014 },
3193 [GCC_UNIPHY1_SYS_CLK_ARES] = { 0x16018, 2 },
3194 [GCC_USB0_AUX_CLK_ARES] = { 0x2c050, 2 },
3195 [GCC_USB0_EUD_AT_CLK_ARES] = { 0x30004, 2 },
3196 [GCC_USB0_LFPS_CLK_ARES] = { 0x2c090, 2 },
3197 [GCC_USB0_MASTER_CLK_ARES] = { 0x2c048, 2 },
3198 [GCC_USB0_MOCK_UTMI_CLK_ARES] = { 0x2c054, 2 },
3199 [GCC_USB0_PHY_BCR] = { 0x2c06c },
3200 [GCC_USB0_PHY_CFG_AHB_CLK_ARES] = { 0x2c05c, 2 },
3201 [GCC_USB0_SLEEP_CLK_ARES] = { 0x2c058, 2 },
3202 [GCC_USB3PHY_0_PHY_BCR] = { 0x2c070 },
3203 [GCC_USB_BCR] = { 0x2c000 },
3204 [GCC_WCSS_AXIM_CLK_ARES] = { 0x2505c, 2 },
3205 [GCC_WCSS_AXIS_CLK_ARES] = { 0x25060, 2 },
3206 [GCC_WCSS_BCR] = { 0x18004 },
3207 [GCC_WCSS_DBG_IFC_APB_BDG_CLK_ARES] = { 0x25048, 2 },
3208 [GCC_WCSS_DBG_IFC_APB_CLK_ARES] = { 0x25038, 2 },
3209 [GCC_WCSS_DBG_IFC_ATB_BDG_CLK_ARES] = { 0x2504c, 2 },
3210 [GCC_WCSS_DBG_IFC_ATB_CLK_ARES] = { 0x2503c, 2 },
3211 [GCC_WCSS_DBG_IFC_NTS_BDG_CLK_ARES] = { 0x25050, 2 },
3212 [GCC_WCSS_DBG_IFC_NTS_CLK_ARES] = { 0x25040, 2 },
3213 [GCC_WCSS_ECAHB_CLK_ARES] = { 0x25058, 2 },
3214 [GCC_WCSS_MST_ASYNC_BDG_CLK_ARES] = { 0x2e0b0, 2 },
3215 [GCC_WCSS_Q6_BCR] = { 0x18000 },
3216 [GCC_WCSS_SLV_ASYNC_BDG_CLK_ARES] = { 0x2e0b4, 2 },
3217 [GCC_XO_CLK_ARES] = { 0x34018, 2 },
3218 [GCC_XO_DIV4_CLK_ARES] = { 0x3401c, 2 },
3219 [GCC_Q6SS_DBG_ARES] = { 0x25094 },
3220 [GCC_WCSS_DBG_BDG_ARES] = { 0x25098, 0 },
3221 [GCC_WCSS_DBG_ARES] = { 0x25098, 1 },
3222 [GCC_WCSS_AXI_S_ARES] = { 0x25098, 2 },
3223 [GCC_WCSS_AXI_M_ARES] = { 0x25098, 3 },
3224 [GCC_WCSSAON_ARES] = { 0x2509C },
3225 [GCC_PCIE3X2_PIPE_ARES] = { 0x28058, 0 },
3226 [GCC_PCIE3X2_CORE_STICKY_ARES] = { 0x28058, 1 },
3227 [GCC_PCIE3X2_AXI_S_STICKY_ARES] = { 0x28058, 2 },
3228 [GCC_PCIE3X2_AXI_M_STICKY_ARES] = { 0x28058, 3 },
3229 [GCC_PCIE3X1_0_PIPE_ARES] = { 0x29058, 0 },
3230 [GCC_PCIE3X1_0_CORE_STICKY_ARES] = { 0x29058, 1 },
3231 [GCC_PCIE3X1_0_AXI_S_STICKY_ARES] = { 0x29058, 2 },
3232 [GCC_PCIE3X1_0_AXI_M_STICKY_ARES] = { 0x29058, 3 },
3233 [GCC_PCIE3X1_1_PIPE_ARES] = { 0x2a058, 0 },
3234 [GCC_PCIE3X1_1_CORE_STICKY_ARES] = { 0x2a058, 1 },
3235 [GCC_PCIE3X1_1_AXI_S_STICKY_ARES] = { 0x2a058, 2 },
3236 [GCC_PCIE3X1_1_AXI_M_STICKY_ARES] = { 0x2a058, 3 },
3237 [GCC_IM_SLEEP_CLK_ARES] = { 0x34020, 2 },
3238 [GCC_NSSNOC_PCNOC_1_CLK_ARES] = { 0x17080, 2 },
3239 [GCC_UNIPHY0_XPCS_ARES] = { 0x16050 },
3240 [GCC_UNIPHY1_XPCS_ARES] = { 0x16060 },
3265 .max_register = 0x3f024,