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/linux/Documentation/devicetree/bindings/bus/
H A Dti-sysc.yaml31 pattern: "^target-module(@[0-9a-f]+)?$"
157 default: 0
158 minimum: 0
195 reg = <0x2b400 0x4>,
196 <0x2b404 0x4>,
197 <0x2b408 0x4>;
199 clocks = <&l3_init_clkctrl OMAP4_USB_OTG_HS_CLKCTRL 0>;
214 ranges = <0 0x2b000 0x1000>;
/linux/drivers/net/wireless/mediatek/mt76/mt7615/
H A Dmmio.c15 [MT_TOP_CFG_BASE] = 0x01000,
16 [MT_HW_BASE] = 0x01000,
17 [MT_PCIE_REMAP_2] = 0x02504,
18 [MT_ARB_BASE] = 0x20c00,
19 [MT_HIF_BASE] = 0x04000,
20 [MT_CSR_BASE] = 0x07000,
21 [MT_PLE_BASE] = 0x08000,
22 [MT_PSE_BASE] = 0x0c000,
23 [MT_CFG_BASE] = 0x20200,
24 [MT_AGG_BASE] = 0x20a00,
[all …]
/linux/arch/powerpc/boot/dts/fsl/
H A Dmpc8536si-post.dtsi39 interrupts = <19 2 0 0>;
42 /* controller at 0x8000 */
46 interrupts = <24 0x2 0 0>;
47 bus-range = <0 0xff>;
53 /* controller at 0x9000 */
59 bus-range = <0 255>;
61 interrupts = <25 2 0 0>;
63 pcie@0 {
64 reg = <0 0 0 0 0>;
69 interrupts = <25 2 0 0>;
[all …]
/linux/sound/pci/au88x0/
H A Dau88x0_eq.c31 #define VORTEX_EQ_BASE 0x2b000
32 #define VORTEX_EQ_DEST (VORTEX_EQ_BASE + 0x410)
33 #define VORTEX_EQ_SOURCE (VORTEX_EQ_BASE + 0x430)
34 #define VORTEX_EQ_CTRL (VORTEX_EQ_BASE + 0x440)
36 #define VORTEX_BAND_COEFF_SIZE 0x30
41 hwwrite(vortex->mmio, 0x2b3c4, gain); in vortex_EqHw_SetTimeConsts()
42 hwwrite(vortex->mmio, 0x2b3c8, level); in vortex_EqHw_SetTimeConsts()
57 int i = 0, n /*esp2c */; in vortex_EqHw_SetLeftCoefs()
59 for (n = 0; n < eqhw->this04; n++) { in vortex_EqHw_SetLeftCoefs()
60 hwwrite(vortex->mmio, 0x2b000 + n * 0x30, coefs[i + 0]); in vortex_EqHw_SetLeftCoefs()
[all …]
/linux/drivers/clk/qcom/
H A Dgcc-sdx55.c33 { 249600000, 2000000000, 0 },
37 .offset = 0x0,
42 .enable_reg = 0x6d000,
43 .enable_mask = BIT(0),
56 { 0x0, 1 },
57 { 0x1, 2 },
58 { 0x3, 4 },
59 { 0x7, 8 },
64 .offset = 0x0,
81 .offset = 0x76000,
[all …]
H A Dgcc-msm8916.c45 .l_reg = 0x21004,
46 .m_reg = 0x21008,
47 .n_reg = 0x2100c,
48 .config_reg = 0x21010,
49 .mode_reg = 0x21000,
50 .status_reg = 0x2101c,
63 .enable_reg = 0x45000,
64 .enable_mask = BIT(0),
76 .l_reg = 0x20004,
77 .m_reg = 0x20008,
[all …]
H A Dgcc-msm8996.c49 .offset = 0x00000,
52 .enable_reg = 0x52000,
53 .enable_mask = BIT(0),
79 .offset = 0x00000,
94 .enable_reg = 0x5200c,
95 .enable_mask = BIT(0),
111 .enable_reg = 0x5200c,
126 .offset = 0x77000,
129 .enable_reg = 0x52000,
143 .offset = 0x77000,
[all …]
H A Dgcc-msm8998.c27 #define GCC_MMSS_MISC 0x0902C
28 #define GCC_GPU_MISC 0x71028
31 { 250000000, 2000000000, 0 },
36 .offset = 0x0,
41 .enable_reg = 0x52000,
42 .enable_mask = BIT(0),
55 .offset = 0x0,
68 .offset = 0x0,
81 .offset = 0x0,
94 .offset = 0x0,
[all …]
H A Dgcc-msm8939.c53 .l_reg = 0x21004,
54 .m_reg = 0x21008,
55 .n_reg = 0x2100c,
56 .config_reg = 0x21010,
57 .mode_reg = 0x21000,
58 .status_reg = 0x2101c,
71 .enable_reg = 0x45000,
72 .enable_mask = BIT(0),
84 .l_reg = 0x20004,
85 .m_reg = 0x20008,
[all …]
H A Dgcc-ipq8074.c52 .offset = 0x21000,
55 .enable_reg = 0x0b000,
56 .enable_mask = BIT(0),
82 .offset = 0x21000,
95 .offset = 0x4a000,
98 .enable_reg = 0x0b000,
114 .offset = 0x4a000,
127 .offset = 0x24000,
130 .enable_reg = 0x0b000,
146 .offset = 0x24000,
[all …]
H A Dgcc-x1e80100.c52 .offset = 0x0,
55 .enable_reg = 0x52030,
56 .enable_mask = BIT(0),
69 { 0x1, 2 },
74 .offset = 0x0,
91 .offset = 0x4000,
94 .enable_reg = 0x52030,
108 .offset = 0x7000,
111 .enable_reg = 0x52030,
125 .offset = 0x8000,
[all …]
/linux/arch/arm/boot/dts/broadcom/
H A Dbcm-nsp.dtsi54 #size-cells = <0>;
56 cpu0: cpu@0 {
60 reg = <0x0>;
68 secondary-boot-reg = <0xffff0fec>;
69 reg = <0x1>;
82 ranges = <0x00000000 0x19000000 0x00023000>;
86 a9pll: arm_clk@0 {
87 #clock-cells = <0>;
90 reg = <0x00000 0x1000>;
95 reg = <0x20200 0x100>;
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dipq6018.dtsi23 #clock-cells = <0>;
29 #clock-cells = <0>;
35 #size-cells = <0>;
37 cpu0: cpu@0 {
40 reg = <0x0>;
53 reg = <0x1>;
65 reg = <0x2>;
77 reg = <0x3>;
95 qcom,dload-mode = <&tcsr 0x6100>;
107 opp-supported-hw = <0xf>;
[all …]
H A Dipq9574.dtsi26 #clock-cells = <0>;
31 #clock-cells = <0>;
37 #clock-cells = <0>;
42 #clock-cells = <0>;
48 #size-cells = <0>;
50 cpu0: cpu@0 {
53 reg = <0x0>;
66 reg = <0x1>;
79 reg = <0x2>;
92 reg = <0x3>;
[all …]
H A Dmsm8996.dtsi30 #clock-cells = <0>;
37 #clock-cells = <0>;
45 #size-cells = <0>;
47 cpu0: cpu@0 {
50 reg = <0x0 0x0>;
54 clocks = <&kryocc 0>;
69 reg = <0x0 0x1>;
73 clocks = <&kryocc 0>;
83 reg = <0x0 0x100>;
102 reg = <0x0 0x101>;
[all …]
/linux/drivers/net/ethernet/marvell/octeontx2/af/
H A Drvu_reg.h12 #define RVU_AF_MSIXTR_BASE (0x10)
13 #define RVU_AF_ECO (0x20)
14 #define RVU_AF_BLK_RST (0x30)
15 #define RVU_AF_PF_BAR4_ADDR (0x40)
16 #define RVU_AF_RAS (0x100)
17 #define RVU_AF_RAS_W1S (0x108)
18 #define RVU_AF_RAS_ENA_W1S (0x110)
19 #define RVU_AF_RAS_ENA_W1C (0x118)
20 #define RVU_AF_GEN_INT (0x120)
21 #define RVU_AF_GEN_INT_W1S (0x128)
[all …]
/linux/drivers/interconnect/qcom/
H A Dsm8650.c29 .port_offsets = { 0xc000 },
31 .urg_fwd = 0,
32 .prio_fwd_disable = 0,
47 .port_offsets = { 0xd000 },
49 .urg_fwd = 0,
50 .prio_fwd_disable = 0,
74 .port_offsets = { 0xe000 },
76 .urg_fwd = 0,
77 .prio_fwd_disable = 0,
92 .port_offsets = { 0xf000 },
[all …]
/linux/arch/arm/boot/dts/ti/omap/
H A Domap4-l4.dtsi2 &l4_cfg { /* 0x4a000000 */
5 clocks = <&l4_cfg_clkctrl OMAP4_L4_CFG_CLKCTRL 0>;
7 reg = <0x4a000000 0x800>,
8 <0x4a000800 0x800>,
9 <0x4a001000 0x1000>;
13 ranges = <0x00000000 0x4a000000 0x080000>, /* segment 0 */
14 <0x00080000 0x4a080000 0x080000>, /* segment 1 */
15 <0x00100000 0x4a100000 0x080000>, /* segment 2 */
16 <0x00180000 0x4a180000 0x080000>, /* segment 3 */
17 <0x00200000 0x4a200000 0x080000>, /* segment 4 */
[all …]
/linux/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_dump.h22 #define DRV_DUMP_XSTORM_WAITP_ADDRESS 0x2b8a80
23 #define DRV_DUMP_TSTORM_WAITP_ADDRESS 0x1b8a80
24 #define DRV_DUMP_USTORM_WAITP_ADDRESS 0x338a80
25 #define DRV_DUMP_CSTORM_WAITP_ADDRESS 0x238a80
45 #define BNX2X_DUMP_VERSION 0x61111111
65 static const u32 page_vals_e2[] = {0, 128};
68 {0x58000, 4608, DUMP_CHIP_E2, 0x30}
74 static const u32 page_vals_e3[] = {0, 128};
77 {0x58000, 4608, DUMP_CHIP_E3A0 | DUMP_CHIP_E3B0, 0x30}
81 { 0x2000, 1, 0x1f, 0xfff},
[all …]