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/linux/arch/arm/mach-s3c/
H A Dmap-s3c64xx.h22 #define S3C64XX_PA_XM0CSN0 (0x10000000)
23 #define S3C64XX_PA_XM0CSN1 (0x18000000)
24 #define S3C64XX_PA_XM0CSN2 (0x20000000)
25 #define S3C64XX_PA_XM0CSN3 (0x28000000)
26 #define S3C64XX_PA_XM0CSN4 (0x30000000)
27 #define S3C64XX_PA_XM0CSN5 (0x38000000)
30 #define S3C64XX_PA_HSMMC(x) (0x7C200000 + ((x) * 0x100000))
31 #define S3C64XX_PA_HSMMC0 S3C64XX_PA_HSMMC(0)
35 #define S3C_PA_UART (0x7F005000)
36 #define S3C_PA_UART0 (S3C_PA_UART + 0x00)
[all …]
/linux/arch/arm/boot/dts/airoha/
H A Den7523.dtsi20 reg = <0x84000000 0xA00000>;
25 reg = <0x84B00000 0x100000>;
30 reg = <0x85000000 0x1A00000>;
35 reg = <0x86B00000 0x100000>;
40 reg = <0x86D00000 0x100000>;
51 #size-cells = <0>;
64 cpu0: cpu@0 {
67 reg = <0x0>;
76 reg = <0x1>;
91 reg = <0x1fa20000 0x400>,
[all …]
/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Driscv,imsics.yaml36 XLEN-1 > (HART Index MSB) 12 0
39 |xxxxxx|Group Index|xxxxxxxxxxx|HART Index|Guest Index| 0 |
62 const: 0
67 const: 0
95 minimum: 0
97 default: 0
102 minimum: 0
109 minimum: 0
111 default: 0
117 minimum: 0
[all …]
/linux/arch/sh/boards/mach-rsk/
H A Ddevices-rsk7264.c24 [0] = {
25 .start = 0x28000000,
26 .end = 0x280000ff,
/linux/arch/arm64/boot/dts/broadcom/
H A Dbcm2712-rpi-5-b.dts20 memory@0 {
22 reg = <0 0 0 0x28000000>;
35 <3300000 0>;
/linux/Documentation/devicetree/bindings/net/
H A Dtoshiba,visconti-dwmac.yaml64 reg = <0 0x28000000 0 0x10000>;
76 #address-cells = <0x1>;
77 #size-cells = <0x0>;
82 reg = <0x1>;
/linux/arch/sparc/include/asm/
H A Dfbio.h10 #define CG6_FBC 0x70000000
11 #define CG6_TEC 0x70001000
12 #define CG6_BTREGS 0x70002000
13 #define CG6_FHC 0x70004000
14 #define CG6_THC 0x70005000
15 #define CG6_ROM 0x70006000
16 #define CG6_RAM 0x70016000
17 #define CG6_DHC 0x80000000
19 #define CG3_MMAP_OFFSET 0x4000000
22 #define TCX_RAM8BIT 0x00000000
[all …]
/linux/Documentation/devicetree/bindings/clock/
H A Dqcom,lcc.yaml117 reg = <0x28000000 0x1000>;
/linux/Documentation/devicetree/bindings/arm/
H A Darm,coresight-stm.yaml90 reg = <0x20100000 0x1000>,
91 <0x28000000 0x180000>;
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
H A Dnv40.c33 u32 tiles = DIV_ROUND_UP(size, 0x80); in nv40_fb_tile_comp()
34 u32 tags = round_up(tiles / fb->ram->parts, 0x100); in nv40_fb_tile_comp()
36 !nvkm_mm_head(&fb->tags.mm, 0, 1, tags, tags, 1, &tile->tag)) { in nv40_fb_tile_comp()
37 tile->zcomp = 0x28000000; /* Z24S8_SPLIT_GRAD */ in nv40_fb_tile_comp()
41 tile->zcomp |= 0x40000000; in nv40_fb_tile_comp()
49 nvkm_mask(fb->subdev.device, 0x10033c, 0x00008000, 0x00000000); in nv40_fb_init()
/linux/arch/arm/configs/
H A Dlpc18xx_defconfig21 CONFIG_DRAM_BASE=0x28000000
22 CONFIG_DRAM_SIZE=0x02000000
23 CONFIG_FLASH_MEM_BASE=0x1b000000
24 CONFIG_FLASH_SIZE=0x00080000
/linux/Documentation/devicetree/bindings/pci/
H A Dmediatek-pcie.txt32 where N starting from 0 to one less than the number of root ports.
80 reg = <0 0x1a000000 0 0x1000>;
88 reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */
89 <0 0x1a142000 0 0x1000>, /* Port0 registers */
90 <0 0x1a143000 0 0x1000>, /* Port1 registers */
91 <0 0x1a144000 0 0x1000>; /* Port2 registers */
96 interrupt-map-mask = <0xf800 0 0 0>;
97 interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
98 <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
99 <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
[all …]
H A Dnvidia,tegra20-pcie.txt27 - cell 0 specifies the bus and device numbers of the root port:
30 - cell 1 denotes the upper 32 address bits and should be 0
45 - 0x81000000: I/O memory region
46 - 0x82000000: non-prefetchable memory region
47 - 0xc2000000: prefetchable memory region
73 - pinctrl-0: phandle for the default/active state of pin configurations.
104 - If lanes 0 to 3 are used:
150 - Root port 0 uses 4 lanes, root port 1 is unused.
158 "pcie-N": where N ranges from 0 to the value specified in nvidia,num-lanes.
171 reg = <0x80003000 0x00000800 /* PADS registers */
[all …]
H A Dnvidia,tegra194-pcie.yaml85 - const: p2u-0
123 0: C0
132 0 : C0
260 bus@0 {
263 ranges = <0x0 0x0 0x0 0x8 0x0>;
268 reg = <0x0 0x14180000 0x0 0x00020000>, /* appl registers (128K) */
269 <0x0 0x38000000 0x0 0x00040000>, /* configuration space (256K) */
270 <0x0 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
271 <0x0 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */
278 linux,pci-domain = <0>;
[all …]
/linux/arch/arm/boot/dts/nxp/lpc/
H A Dlpc4337-ciaa.dts35 reg = <0x28000000 0x0800000>; /* 8 MB */
173 pinctrl-0 = <&i2c0_pins>;
178 reg = <0x50>;
183 reg = <0x51>;
188 reg = <0x54>;
196 pinctrl-0 = <&enet_rmii_pins>;
206 pinctrl-0 = <&ssp_pins>;
214 pinctrl-0 = <&uart2_pins>;
220 pinctrl-0 = <&uart3_pins>;
H A Dlpc4350-hitex-eval.dts38 reg = <0x28000000 0x800000>; /* 8 MB */
101 gpios = <&pca_gpio 0 GPIO_ACTIVE_LOW>;
346 pinctrl-0 = <&adc1_pins>;
352 pinctrl-0 = <&emc_pins>;
359 mpmc,cs = <0>;
362 mpmc,write-enable-delay = <0>;
363 mpmc,output-enable-delay = <0>;
367 flash@0,0 {
369 reg = <0 0 0x400000>;
374 partition@0 {
[all …]
/linux/lib/crypto/
H A Ddes.c31 0x00, 0x00, 0x40, 0x04, 0x10, 0x10, 0x50, 0x14,
32 0x04, 0x40, 0x44, 0x44, 0x14, 0x50, 0x54, 0x54,
33 0x02, 0x02, 0x42, 0x06, 0x12, 0x12, 0x52, 0x16,
34 0x06, 0x42, 0x46, 0x46, 0x16, 0x52, 0x56, 0x56,
35 0x80, 0x08, 0xc0, 0x0c, 0x90, 0x18, 0xd0, 0x1c,
36 0x84, 0x48, 0xc4, 0x4c, 0x94, 0x58, 0xd4, 0x5c,
37 0x82, 0x0a, 0xc2, 0x0e, 0x92, 0x1a, 0xd2, 0x1e,
38 0x86, 0x4a, 0xc6, 0x4e, 0x96, 0x5a, 0xd6, 0x5e,
39 0x20, 0x20, 0x60, 0x24, 0x30, 0x30, 0x70, 0x34,
40 0x24, 0x60, 0x64, 0x64, 0x34, 0x70, 0x74, 0x74,
[all …]
/linux/arch/arm/mach-versatile/
H A Dintegrator-hardware.h14 #define IO_BASE 0xF0000000 // VA of IO
15 #define IO_SIZE 0x0B000000 // How much?
19 #define IO_ADDRESS(x) (((x) & 0x000fffff) | (((x) >> 4) & 0x0ff00000) | IO_BASE)
25 #define INTEGRATOR_BOOT_ROM_LO 0x00000000
26 #define INTEGRATOR_BOOT_ROM_HI 0x20000000
40 #define INTEGRATOR_SSRAM_BASE 0x00000000
41 #define INTEGRATOR_SSRAM_ALIAS_BASE 0x10800000
44 #define INTEGRATOR_FLASH_BASE 0x24000000
47 #define INTEGRATOR_MBRD_SSRAM_BASE 0x28000000
53 #define INTEGRATOR_SDRAM_BASE 0x00040000
[all …]
/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra234.dtsi19 bus@0 {
24 ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
28 reg = <0x0 0x00100000 0x0 0xf000>,
29 <0x0 0x0010f000 0x0 0x1000>;
35 reg = <0x0 0x02080000 0x0 0x00121000>;
36 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
58 reg = <0x0 0x02200000 0x0 0x10000>,
59 <0x0 0x02210000 0x0 0x10000>;
112 gpio-ranges = <&pinmux 0 0 164>;
117 reg = <0x0 0x2430000 0x0 0x19100>;
[all …]
/linux/arch/arm64/boot/dts/renesas/
H A Dr9a09g011-v2mevk2.dts33 #size-cells = <0>;
35 port@0 {
36 reg = <0>;
57 reg = <0x0 0x58000000 0x0 0x28000000>;
62 reg = <0x1 0x80000000 0x0 0x80000000>;
90 gpios = <&pwc 0 GPIO_ACTIVE_HIGH>;
92 states = <3300000 0>, <1800000 1>;
102 phy0: ethernet-phy@0 {
105 reg = <0>;
110 pinctrl-0 = <&emmc_pins>;
[all …]
/linux/drivers/gpu/drm/etnaviv/
H A Dcmdstream.xml.h7 http://0x04.net/cgit/index.cgi/rules-ng-ng
8 git clone git://0x04.net/rules-ng-ng
42 #define FE_OPCODE_LOAD_STATE 0x00000001
43 #define FE_OPCODE_END 0x00000002
44 #define FE_OPCODE_NOP 0x00000003
45 #define FE_OPCODE_DRAW_2D 0x00000004
46 #define FE_OPCODE_DRAW_PRIMITIVES 0x00000005
47 #define FE_OPCODE_DRAW_INDEXED_PRIMITIVES 0x00000006
48 #define FE_OPCODE_WAIT 0x00000007
49 #define FE_OPCODE_LINK 0x00000008
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mn-tqma8mqnl.dtsi15 reg = <0x00000000 0x40000000 0 0x40000000>;
43 size = <0 0x28000000>;
45 alloc-ranges = <0 0x40000000 0 0x78000000>;
57 pinctrl-0 = <&pinctrl_flexspi>;
60 flash0: flash@0 {
62 reg = <0>;
78 pinctrl-0 = <&pinctrl_i2c1>;
86 reg = <0x1b>;
91 reg = <0x25>;
94 pinctrl-0 = <&pinctrl_pmic>;
[all …]
H A Dimx8mq-tqma8mq.dtsi15 reg = <0x00000000 0x40000000 0 0x40000000>;
36 pinctrl-0 = <&pinctrl_dvfs>;
43 states = <900000 0x1 1000000 0x0>;
56 size = <0 0x28000000>;
58 alloc-ranges = <0 0x40000000 0 0x78000000>;
95 pinctrl-0 = <&pinctrl_i2c1>;
104 reg = <0x8>;
199 reg = <0x1b>;
204 reg = <0x51>;
206 pinctrl-0 = <&pinctrl_rtc>;
[all …]
H A Dimx8mm-tqma8mqml.dtsi16 reg = <0x00000000 0x40000000 0 0x40000000>;
45 size = <0 0x28000000>;
47 alloc-ranges = <0 0x40000000 0 0x78000000>;
59 pinctrl-0 = <&pinctrl_flexspi>;
62 flash0: flash@0 {
64 reg = <0>;
87 pinctrl-0 = <&pinctrl_i2c1>;
95 reg = <0x1b>;
100 reg = <0x25>;
103 pinctrl-0 = <&pinctrl_pmic>;
[all …]
/linux/arch/m68k/include/asm/
H A Dfbio.h13 #define FBTYPE_SUN1BW 0 /* mono */
58 #define FBIOGTYPE _IOR('F', 0, struct fbtype)
61 int index; /* first element (0 origin) */
124 #define FB_WID_SHARED_8 0
196 #define FB_CLUT_WAIT 0x00000001 /* Not yet implemented */
225 #define CG6_FBC 0x70000000
226 #define CG6_TEC 0x70001000
227 #define CG6_BTREGS 0x70002000
228 #define CG6_FHC 0x70004000
229 #define CG6_THC 0x70005000
[all …]

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