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/freebsd/sys/contrib/device-tree/Bindings/nvmem/
H A Dqcom,qfprom.yaml102 reg = <0 0x00784000 0 0x8ff>,
103 <0 0x00780000 0 0x7a0>,
104 <0 0x00782000 0 0x100>,
105 <0 0x00786000 0 0x1fff>;
114 reg = <0x25b 0x1>;
127 reg = <0 0x00784000 0 0x8ff>;
132 reg = <0x1eb 0x1>;
/freebsd/share/misc/
H A Dusb_hid_usages12 0x00 Undefined
13 0x01 Pointer
14 0x02 Mouse
15 0x03 Reserved
16 0x04 Joystick
17 0x05 Game Pad
18 0x06 Keyboard
19 0x07 Keypad
20 0x08 Multi-axis Controller
21 0x09 Tablet PC System Controls
[all …]
/freebsd/sys/powerpc/include/
H A Dspr.h35 __asm __volatile("mtspr %0,%1" : : "K"(reg), "r"(val))
38 __asm __volatile("mfspr %0,%1" : "=r"(val) : "K"(reg)); \
48 mfmsr %0; \
49 insrdi %0,%5,1,0; \
50 mtmsrd %0; \
58 clrldi %0,%0,1; \
59 mtmsrd %0; \
66 mfmsr %0; \
[all...]
/freebsd/sys/gnu/dev/bwn/phy_n/
H A Dif_bwn_phy_n_regs.h34 #define BWN_NPHY_BBCFG BWN_PHY_N(0x001) /* BB config */
35 #define BWN_NPHY_BBCFG_RSTCCA 0x4000 /* Reset CCA */
36 #define BWN_NPHY_BBCFG_RSTRX 0x8000 /* Reset RX */
37 #define BWN_NPHY_CHANNEL BWN_PHY_N(0x005) /* Channel */
38 #define BWN_NPHY_TXERR BWN_PHY_N(0x007) /* TX error */
39 #define BWN_NPHY_BANDCTL BWN_PHY_N(0x009) /* Band control */
40 #define BWN_NPHY_BANDCTL_5GHZ 0x0001 /* Use the 5GHz band */
41 #define BWN_NPHY_4WI_ADDR BWN_PHY_N(0x00B) /* Four-wire bus address */
42 #define BWN_NPHY_4WI_DATAHI BWN_PHY_N(0x00C) /* Four-wire bus data high */
43 #define BWN_NPHY_4WI_DATALO BWN_PHY_N(0x00D) /* Four-wire bus data low */
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dqcm2290.dtsi32 #clock-cells = <0>;
38 #clock-cells = <0>;
44 #size-cells = <0>;
46 cpu0: cpu@0 {
49 reg = <0x0 0x0>;
50 clocks = <&cpufreq_hw 0>;
55 qcom,freq-domain = <&cpufreq_hw 0>;
68 reg = <0x0 0x1>;
69 clocks = <&cpufreq_hw 0>;
74 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dsm6115.dtsi34 #clock-cells = <0>;
39 #clock-cells = <0>;
45 #size-cells = <0>;
47 cpu0: cpu@0 {
50 reg = <0x0 0x0>;
51 clocks = <&cpufreq_hw 0>;
56 qcom,freq-domain = <&cpufreq_hw 0>;
69 reg = <0x0 0x1>;
70 clocks = <&cpufreq_hw 0>;
75 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dsc7180.dtsi67 #clock-cells = <0>;
73 #clock-cells = <0>;
79 #size-cells = <0>;
81 cpu0: cpu@0 {
84 reg = <0x0 0x0>;
85 clocks = <&cpufreq_hw 0>;
96 qcom,freq-domain = <&cpufreq_hw 0>;
113 reg = <0x0 0x100>;
114 clocks = <&cpufreq_hw 0>;
125 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DVOP3Instructions.td3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
14 let HasExtVOP3DPP = 0;
15 let HasExtDPP = 0;
28 let HasExtVOP3DPP = 0;
29 let HasExtDPP = 0;
44 let HasExtVOP3DPP = 0;
45 let HasExtDPP = 0;
49 let HasExtVOP3DPP = 0;
50 let HasExtDPP = 0;
60 let mayRaiseFPException = 0;
[all …]
/freebsd/sys/dev/usb/wlan/
H A Dif_urtw.c67 static SYSCTL_NODE(_hw_usb, OID_AUTO, urtw, CTLFLAG_RW | CTLFLAG_MPSAFE, 0,
70 int urtw_debug = 0;
71 SYSCTL_INT(_hw_usb_urtw, OID_AUTO, debug, CTLFLAG_RWTUN, &urtw_debug, 0,
74 URTW_DEBUG_XMIT = 0x00000001, /* basic xmit operation */
75 URTW_DEBUG_RECV = 0x00000002, /* basic recv operation */
76 URTW_DEBUG_RESET = 0x00000004, /* reset processing */
77 URTW_DEBUG_TX_PROC = 0x00000008, /* tx ISR proc */
78 URTW_DEBUG_RX_PROC = 0x00000010, /* rx ISR proc */
79 URTW_DEBUG_STATE = 0x00000020, /* 802.11 state transitions */
80 URTW_DEBUG_STAT = 0x00000040, /* statistic */
[all …]
/freebsd/crypto/heimdal/lib/wind/
H A Dnormalize_table.c9 {0xa0, 1, 0}, /* NO-BREAK SPACE */
10 {0xa8, 2, 1}, /* DIAERESIS */
11 {0xaa, 1, 3}, /* FEMININE ORDINAL INDICATOR */
12 {0xaf, 2, 4}, /* MACRON */
13 {0xb2, 1, 6}, /* SUPERSCRIPT TWO */
14 {0xb3, 1, 7}, /* SUPERSCRIPT THREE */
15 {0xb4, 2, 8}, /* ACUTE ACCENT */
16 {0xb5, 1, 10}, /* MICRO SIGN */
17 {0xb8, 2, 11}, /* CEDILLA */
18 {0xb9, 1, 13}, /* SUPERSCRIPT ONE */
[all …]
/freebsd/sys/dev/bnxt/bnxt_en/
H A Dhsi_struct_def.h71 * * 0x0-0xFFF8 - The function ID
72 * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors
73 * * 0xFFFD - Reserved for user-space HWRM interface
74 * * 0xFFFF - HWRM
104 #define CMD_DISCR_TLV_ENCAP UINT32_C(0x8000)
109 #define TLV_TYPE_HWRM_REQUEST UINT32_C(0x1)
111 #define TLV_TYPE_HWRM_RESPONSE UINT32_C(0x2)
113 #define TLV_TYPE_ROCE_SP_COMMAND UINT32_C(0x3)
115 #define TLV_TYPE_QUERY_ROCE_CC_GEN1 UINT32_C(0x4)
117 #define TLV_TYPE_MODIFY_ROCE_CC_GEN1 UINT32_C(0x5)
[all …]