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/linux/drivers/net/wireless/mediatek/mt76/mt7615/
H A Dmmio.c15 [MT_TOP_CFG_BASE] = 0x01000,
16 [MT_HW_BASE] = 0x01000,
17 [MT_PCIE_REMAP_2] = 0x02504,
18 [MT_ARB_BASE] = 0x20c00,
19 [MT_HIF_BASE] = 0x04000,
20 [MT_CSR_BASE] = 0x07000,
21 [MT_PLE_BASE] = 0x08000,
22 [MT_PSE_BASE] = 0x0c000,
23 [MT_CFG_BASE] = 0x20200,
24 [MT_AGG_BASE] = 0x20a00,
[all …]
/linux/Documentation/devicetree/bindings/remoteproc/
H A Dti,pru-rproc.yaml19 The K3 SoCs containing ICSSG v1.0 (eg: AM65x SR1.0) also have two Auxiliary
21 containing the revised ICSSG v1.1 (eg: J721E, AM65x SR2.0) have an extra two
46 - ti,am654-tx-pru # for Tx_PRUs in K3 AM65x SR2.0 SoCs
90 pattern: "^rtu@[0-9a-f]+$"
102 pattern: "^txpru@[0-9a-f]+"
106 pattern: "^pru@[0-9a-f]+$"
119 pruss_tm: target-module@300000 { /* 0x4a300000, ap 9 04.0 */
123 ranges = <0x0 0x300000 0x80000>;
125 pruss: pruss@0 {
127 reg = <0x0 0x80000>;
[all …]
/linux/arch/arm64/boot/dts/ti/
H A Dk3-am65-main.dtsi12 reg = <0x0 0x70000000 0x0 0x200000>;
15 ranges = <0x0 0x0 0x70000000 0x200000>;
17 atf-sram@0 {
18 reg = <0x0 0x20000>;
22 reg = <0xf0000 0x10000>;
26 reg = <0x100000 0x100000>;
37 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
38 <0x00 0x01880000 0x00 0x90000>, /* GICR */
39 <0x00 0x6f000000 0x00 0x2000>, /* GICC */
40 <0x00 0x6f010000 0x00 0x1000>, /* GICH */
[all …]
H A Dk3-am64-main.dtsi13 #clock-cells = <0>;
15 clock-frequency = <0>;
22 reg = <0x00 0x70000000 0x00 0x200000>;
25 ranges = <0x0 0x00 0x70000000 0x200000>;
28 reg = <0x1c0000 0x20000>;
32 reg = <0x1e0000 0x1c000>;
36 reg = <0x1fc000 0x4000>;
43 reg = <0x0 0x43000000 0x0 0x20000>;
46 ranges = <0x0 0x0 0x43000000 0x20000>;
51 reg = <0x00000014 0x4>;
[all …]
/linux/drivers/net/wireless/mediatek/mt76/mt7915/
H A Dmmio.c21 [INT_SOURCE_CSR] = 0xd7010,
22 [INT_MASK_CSR] = 0xd7014,
23 [INT1_SOURCE_CSR] = 0xd7088,
24 [INT1_MASK_CSR] = 0xd708c,
25 [INT_MCU_CMD_SOURCE] = 0xd51f0,
26 [INT_MCU_CMD_EVENT] = 0x3108,
27 [WFDMA0_ADDR] = 0xd4000,
28 [WFDMA0_PCIE1_ADDR] = 0xd8000,
29 [WFDMA_EXT_CSR_ADDR] = 0xd7000,
30 [CBTOP1_PHY_END] = 0x77ffffff,
[all …]
/linux/drivers/net/wireless/mediatek/mt76/mt7921/
H A Dpci.c17 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7961),
19 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7922),
21 { PCI_DEVICE(PCI_VENDOR_ID_ITTIM, 0x7922),
23 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x0608),
25 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x0616),
27 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7920),
66 { 0x820d0000, 0x30000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */ in __mt7921_reg_addr()
67 { 0x820ed000, 0x24800, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */ in __mt7921_reg_addr()
68 { 0x820e4000, 0x21000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */ in __mt7921_reg_addr()
69 { 0x820e7000, 0x21e00, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */ in __mt7921_reg_addr()
[all …]
/linux/drivers/net/wireless/mediatek/mt76/mt7996/
H A Dmmio.c21 [WF_AGG_BASE] = { { 0x820e2000, 0x820f2000, 0x830e2000 } },
22 [WF_ARB_BASE] = { { 0x820e3000, 0x820f3000, 0x830e3000 } },
23 [WF_TMAC_BASE] = { { 0x820e4000, 0x820f4000, 0x830e4000 } },
24 [WF_RMAC_BASE] = { { 0x820e5000, 0x820f5000, 0x830e5000 } },
25 [WF_DMA_BASE] = { { 0x820e7000, 0x820f7000, 0x830e7000 } },
26 [WF_WTBLOFF_BASE] = { { 0x820e9000, 0x820f9000, 0x830e9000 } },
27 [WF_ETBF_BASE] = { { 0x820ea000, 0x820fa000, 0x830ea000 } },
28 [WF_LPON_BASE] = { { 0x820eb000, 0x820fb000, 0x830eb000 } },
29 [WF_MIB_BASE] = { { 0x820ed000, 0x820fd000, 0x830ed000 } },
30 [WF_RATE_BASE] = { { 0x820ee000, 0x820fe000, 0x830ee000 } },
[all …]
/linux/drivers/dma/qcom/
H A Dgpi.c20 #define TRE_TYPE_DMA 0x10
21 #define TRE_TYPE_GO 0x20
22 #define TRE_TYPE_CONFIG0 0x22
25 #define TRE_FLAGS_CHAIN BIT(0)
33 #define TRE_SPI_C0_WORD_SZ GENMASK(4, 0)
42 #define TRE_C0_CLK_DIV GENMASK(11, 0)
46 #define TRE_SPI_GO_CMD GENMASK(4, 0)
51 #define TRE_RX_LEN GENMASK(23, 0)
54 #define TRE_I2C_C0_TLOW GENMASK(7, 0)
61 #define TRE_I2C_GO_CMD GENMASK(4, 0)
[all …]
/linux/drivers/net/ethernet/chelsio/cxgb4/
H A Dt4_hw.c54 * at the time it indicated completion is stored there. Returns 0 if the
66 return 0; in t4_wait_op_done_val()
68 if (--attempts == 0) in t4_wait_op_done_val()
167 /* Reset ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a in t4_hw_pci_read_cfg4()
169 * ENABLE is 0 so a simple register write is easier than a in t4_hw_pci_read_cfg4()
172 t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, 0); in t4_hw_pci_read_cfg4()
247 log->cursor = 0; in t4_record_mbox()
249 for (i = 0; i < size / 8; i++) in t4_record_mbox()
252 entry->cmd[i++] = 0; in t4_record_mbox()
277 * The return value is 0 on success or a negative errno on failure. A
[all …]