20 #define TRE_TYPE_DMA		0x10
21 #define TRE_TYPE_GO		0x20
22 #define TRE_TYPE_CONFIG0	0x22
25 #define TRE_FLAGS_CHAIN		BIT(0)
33 #define TRE_SPI_C0_WORD_SZ	GENMASK(4, 0)
42 #define TRE_C0_CLK_DIV		GENMASK(11, 0)
46 #define TRE_SPI_GO_CMD		GENMASK(4, 0)
51 #define TRE_RX_LEN		GENMASK(23, 0)
54 #define TRE_I2C_C0_TLOW		GENMASK(7, 0)
61 #define TRE_I2C_GO_CMD          GENMASK(4, 0)
66 #define TRE_DMA_LEN		GENMASK(23, 0)
69 #define GPII_n_CH_k_CNTXT_0_OFFS(n, k)	(0x20000 + (0x4000 * (n)) + (0x80 * (k)))
74 #define GPII_n_CH_k_CNTXT_0_PROTO	GENMASK(2, 0)
82 #define GPI_CHTYPE_DIR_IN	(0)
85 #define GPI_CHTYPE_PROTO_GPI	(0x2)
87 #define GPII_n_CH_k_DOORBELL_0_OFFS(n, k)	(0x22000 + (0x4000 * (n)) + (0x8 * (k)))
88 #define GPII_n_CH_CMD_OFFS(n)			(0x23008 + (0x4000 * (n)))
90 #define GPII_n_CH_CMD_CHID			GENMASK(7, 0)
95 #define GPII_n_CH_CMD_ALLOCATE		(0)
105 #define GPII_n_EV_CH_k_CNTXT_0_OFFS(n, k) (0x21000 + (0x4000 * (n)) + (0x80 * (k)))
109 #define GPII_n_EV_k_CNTXT_0_CHTYPE	GENMASK(3, 0)
117 #define GPI_CHTYPE_GPI_EV	(0x2)
120 	CNTXT_0_CONFIG = 0x0,
121 	CNTXT_1_R_LENGTH = 0x4,
122 	CNTXT_2_RING_BASE_LSB = 0x8,
123 	CNTXT_3_RING_BASE_MSB = 0xC,
124 	CNTXT_4_RING_RP_LSB = 0x10,
125 	CNTXT_5_RING_RP_MSB = 0x14,
126 	CNTXT_6_RING_WP_LSB = 0x18,
127 	CNTXT_7_RING_WP_MSB = 0x1C,
128 	CNTXT_8_RING_INT_MOD = 0x20,
129 	CNTXT_9_RING_INTVEC = 0x24,
130 	CNTXT_10_RING_MSI_LSB = 0x28,
131 	CNTXT_11_RING_MSI_MSB = 0x2C,
132 	CNTXT_12_RING_RP_UPDATE_LSB = 0x30,
133 	CNTXT_13_RING_RP_UPDATE_MSB = 0x34,
136 #define GPII_n_EV_CH_k_DOORBELL_0_OFFS(n, k)	(0x22100 + (0x4000 * (n)) + (0x8 * (k)))
137 #define GPII_n_EV_CH_CMD_OFFS(n)		(0x23010 + (0x4000 * (n)))
139 #define GPII_n_EV_CMD_CHID			GENMASK(7, 0)
144 #define GPII_n_EV_CH_CMD_ALLOCATE		(0x00)
145 #define GPII_n_EV_CH_CMD_RESET			(0x09)
146 #define GPII_n_EV_CH_CMD_DE_ALLOC		(0x0A)
148 #define GPII_n_CNTXT_TYPE_IRQ_OFFS(n)		(0x23080 + (0x4000 * (n)))
151 #define GPII_n_CNTXT_TYPE_IRQ_MSK_OFFS(n)	(0x23088 + (0x4000 * (n)))
152 #define GPII_n_CNTXT_TYPE_IRQ_MSK_BMSK		GENMASK(6, 0)
157 #define GPII_n_CNTXT_TYPE_IRQ_MSK_CH_CTRL	BIT(0)
159 #define GPII_n_CNTXT_SRC_GPII_CH_IRQ_OFFS(n)	(0x23090 + (0x4000 * (n)))
160 #define GPII_n_CNTXT_SRC_EV_CH_IRQ_OFFS(n)	(0x23094 + (0x4000 * (n)))
163 #define GPII_n_CNTXT_SRC_CH_IRQ_MSK_OFFS(n)	(0x23098 + (0x4000 * (n)))
164 #define GPII_n_CNTXT_SRC_CH_IRQ_MSK_BMSK	GENMASK(1, 0)
167 #define GPII_n_CNTXT_SRC_EV_CH_IRQ_MSK_OFFS(n)	(0x2309C + (0x4000 * (n)))
168 #define GPII_n_CNTXT_SRC_EV_CH_IRQ_MSK_BMSK	BIT(0)
170 #define GPII_n_CNTXT_SRC_CH_IRQ_CLR_OFFS(n)	(0x230A0 + (0x4000 * (n)))
171 #define GPII_n_CNTXT_SRC_EV_CH_IRQ_CLR_OFFS(n)	(0x230A4 + (0x4000 * (n)))
174 #define GPII_n_CNTXT_SRC_IEOB_IRQ_MSK_OFFS(n)	(0x230B8 + (0x4000 * (n)))
175 #define GPII_n_CNTXT_SRC_IEOB_IRQ_MSK_BMSK	BIT(0)
177 #define GPII_n_CNTXT_SRC_IEOB_IRQ_CLR_OFFS(n)	(0x230C0 + (0x4000 * (n)))
178 #define GPII_n_CNTXT_GLOB_IRQ_STTS_OFFS(n)	(0x23100 + (0x4000 * (n)))
179 #define GPI_GLOB_IRQ_ERROR_INT_MSK		BIT(0)
182 #define GPII_n_CNTXT_GLOB_IRQ_EN_OFFS(n)	(0x23108 + (0x4000 * (n)))
183 #define GPII_n_CNTXT_GLOB_IRQ_CLR_OFFS(n)	(0x23110 + (0x4000 * (n)))
184 #define GPII_n_CNTXT_GPII_IRQ_STTS_OFFS(n)	(0x23118 + (0x4000 * (n)))
187 #define GPII_n_CNTXT_GPII_IRQ_EN_OFFS(n)	(0x23120 + (0x4000 * (n)))
188 #define GPII_n_CNTXT_GPII_IRQ_EN_BMSK		GENMASK(3, 0)
190 #define GPII_n_CNTXT_GPII_IRQ_CLR_OFFS(n)	(0x23128 + (0x4000 * (n)))
193 #define GPII_n_CNTXT_INTSET_OFFS(n)		(0x23180 + (0x4000 * (n)))
194 #define GPII_n_CNTXT_INTSET_BMSK		BIT(0)
196 #define GPII_n_CNTXT_MSI_BASE_LSB_OFFS(n)	(0x23188 + (0x4000 * (n)))
197 #define GPII_n_CNTXT_MSI_BASE_MSB_OFFS(n)	(0x2318C + (0x4000 * (n)))
198 #define GPII_n_CNTXT_SCRATCH_0_OFFS(n)		(0x23400 + (0x4000 * (n)))
199 #define GPII_n_CNTXT_SCRATCH_1_OFFS(n)		(0x23404 + (0x4000 * (n)))
201 #define GPII_n_ERROR_LOG_OFFS(n)		(0x23200 + (0x4000 * (n)))
204 #define GPII_n_CH_k_QOS_OFFS(n, k)		(0x2005C + (0x4000 * (n)) + (0x80 * (k)))
207 #define GPII_n_CH_k_SCRATCH_0_OFFS(n, k)	(0x20060 + (0x4000 * (n)) + (0x80 * (k)))
208 #define GPII_n_CH_k_SCRATCH_0_SEID		GENMASK(2, 0)
215 #define GPII_n_CH_k_SCRATCH_1_OFFS(n, k)	(0x20064 + (0x4000 * (n)) + (0x80 * (k)))
216 #define GPII_n_CH_k_SCRATCH_2_OFFS(n, k)	(0x20068 + (0x4000 * (n)) + (0x80 * (k)))
217 #define GPII_n_CH_k_SCRATCH_3_OFFS(n, k)	(0x2006C + (0x4000 * (n)) + (0x80 * (k)))
233 #define GPI_TX_CHAN		(0)
275 	XFER_COMPLETE_EV_TYPE = 0x22,
276 	IMMEDIATE_DATA_EV_TYPE = 0x30,
277 	QUP_NOTIF_EV_TYPE = 0x31,
278 	STALE_EV_TYPE = 0xFF,
294 	DEFAULT_EV_CH_STATE = 0,
309 	DEFAULT_CH_STATE = 0x0,
311 	CH_STATE_ALLOCATED = 0x1,
312 	CH_STATE_STARTED = 0x2,
313 	CH_STATE_STOPPED = 0x3,
314 	CH_STATE_STOP_IN_PROC = 0x4,
315 	CH_STATE_ERROR = 0xf,
596 		       GPII_n_CNTXT_TYPE_IRQ_MSK_BMSK, 0);  in gpi_disable_interrupts()
598 		       GPII_n_CNTXT_SRC_IEOB_IRQ_MSK_BMSK, 0);  in gpi_disable_interrupts()
600 		       GPII_n_CNTXT_SRC_CH_IRQ_MSK_BMSK, 0);  in gpi_disable_interrupts()
602 		       GPII_n_CNTXT_SRC_EV_CH_IRQ_MSK_BMSK, 0);  in gpi_disable_interrupts()
604 		       GPII_n_CNTXT_GPII_IRQ_EN_BMSK, 0);  in gpi_disable_interrupts()
606 		       GPII_n_CNTXT_GPII_IRQ_EN_BMSK, 0);  in gpi_disable_interrupts()
608 		       GPII_n_CNTXT_INTSET_BMSK, 0);  in gpi_disable_interrupts()
610 	gpii->cntxt_type_irq_msk = 0;  in gpi_disable_interrupts()
629 		if (ret < 0) {  in gpi_config_interrupts()
664 		gpi_update_reg(gpii, GPII_n_CNTXT_MSI_BASE_LSB_OFFS(gpii->gpii_id), U32_MAX, 0);  in gpi_config_interrupts()
665 		gpi_update_reg(gpii, GPII_n_CNTXT_MSI_BASE_MSB_OFFS(gpii->gpii_id), U32_MAX, 0);  in gpi_config_interrupts()
666 		gpi_update_reg(gpii, GPII_n_CNTXT_SCRATCH_0_OFFS(gpii->gpii_id), U32_MAX, 0);  in gpi_config_interrupts()
667 		gpi_update_reg(gpii, GPII_n_CNTXT_SCRATCH_1_OFFS(gpii->gpii_id), U32_MAX, 0);  in gpi_config_interrupts()
670 		gpi_update_reg(gpii, GPII_n_ERROR_LOG_OFFS(gpii->gpii_id), U32_MAX, 0);  in gpi_config_interrupts()
676 	return 0;  in gpi_config_interrupts()
702 				     GPII_n_EV_CMD(gpi_cmd_info[gpi_cmd].opcode, 0);  in gpi_send_cmd()
714 		return 0;  in gpi_send_cmd()
717 		return 0;  in gpi_send_cmd()
720 		return 0;  in gpi_send_cmd()
749 	gpi_write_reg(gpii, gpii->ieob_clr_reg, BIT(0));  in gpi_process_ieob()
751 	gpi_config_interrupts(gpii, MASK_IEOB_SETTINGS, 0);  in gpi_process_ieob()
768 	for (chid = 0; chid < MAX_CHANNELS_PER_GPII; chid++) {  in gpi_process_ch_ctrl_irq()
804 	dev_dbg(gpii->gpi_dev->dev, "irq_stts:0x%x\n", irq_stts);  in gpi_process_gen_err_irq()
823 		dev_err(gpii->gpi_dev->dev, "invalid error status:0x%x\n", irq_stts);  in gpi_process_glob_err_irq()
828 	gpi_write_reg(gpii, gpii->regs + offset, 0);  in gpi_process_glob_err_irq()
907 			dev_err(gpii->gpi_dev->dev, "Unhandled interrupt status:0x%x\n", type);  in gpi_handle_irq()
955 			gpi_ere->dword[0], gpi_ere->dword[1],  in gpi_process_imed_data_event()
960 			gpi_tre->dword[0], gpi_tre->dword[1],  in gpi_process_imed_data_event()
1034 			gpi_ere->dword[0], gpi_ere->dword[1],  in gpi_process_xfer_compl_event()
1104 				chid, type, gpi_event->gpi_ere.dword[0],  in gpi_process_events()
1127 					"not supported event type:0x%x\n", type);  in gpi_process_events()
1134 		gpi_write_reg(gpii, gpii->ieob_clr_reg, BIT(0));  in gpi_process_events()
1222 	return 0;  in gpi_reset_chan()
1242 	return 0;  in gpi_start_chan()
1257 	return 0;  in gpi_stop_chan()
1280 		      GPII_n_CH_k_CNTXT_0(ring->el_size, 0, chan->dir, GPI_CHTYPE_PROTO_GPI));  in gpi_alloc_chan()
1289 	gpi_write_reg(gpii, gpii->regs + GPII_n_CH_k_SCRATCH_1_OFFS(id, chid), 0);  in gpi_alloc_chan()
1290 	gpi_write_reg(gpii, gpii->regs + GPII_n_CH_k_SCRATCH_2_OFFS(id, chid), 0);  in gpi_alloc_chan()
1291 	gpi_write_reg(gpii, gpii->regs + GPII_n_CH_k_SCRATCH_3_OFFS(id, chid), 0);  in gpi_alloc_chan()
1296 	return 0;  in gpi_alloc_chan()
1321 	gpi_write_reg(gpii, base + CNTXT_8_RING_INT_MOD, 0);  in gpi_alloc_ev_chan()
1322 	gpi_write_reg(gpii, base + CNTXT_10_RING_MSI_LSB, 0);  in gpi_alloc_ev_chan()
1323 	gpi_write_reg(gpii, base + CNTXT_11_RING_MSI_MSB, 0);  in gpi_alloc_ev_chan()
1324 	gpi_write_reg(gpii, base + CNTXT_8_RING_INT_MOD, 0);  in gpi_alloc_ev_chan()
1325 	gpi_write_reg(gpii, base + CNTXT_12_RING_RP_UPDATE_LSB, 0);  in gpi_alloc_ev_chan()
1326 	gpi_write_reg(gpii, base + CNTXT_13_RING_RP_UPDATE_MSB, 0);  in gpi_alloc_ev_chan()
1340 	return 0;  in gpi_alloc_ev_chan()
1346 	int elements = 0;  in gpi_ring_num_elements_avail()
1360 	if (gpi_ring_num_elements_avail(ring) <= 0)  in gpi_ring_add_element()
1371 	return 0;  in gpi_ring_add_element()
1395 	memset(ring, 0, sizeof(*ring));  in gpi_free_ring()
1433 	memset(ring->base, 0, ring->len);  in gpi_alloc_ring()
1444 	return 0;  in gpi_alloc_ring()
1472 	int ret = 0;  in gpi_terminate_all()
1480 	schid = (gchan->protocol == QCOM_GPI_UART) ? gchan->chid : 0;  in gpi_terminate_all()
1546 		return 0;  in gpi_pause()
1550 	for (i = 0; i < MAX_CHANNELS_PER_GPII; i++) {  in gpi_pause()
1568 	return 0;  in gpi_pause()
1582 		return 0;  in gpi_resume()
1588 	for (i = 0; i < MAX_CHANNELS_PER_GPII; i++) {  in gpi_resume()
1602 	return 0;  in gpi_resume()
1627 	return 0;  in gpi_peripheral_config()
1635 	unsigned int tre_idx = 0;  in gpi_create_i2c_tre()
1645 		tre->dword[0] = u32_encode_bits(i2c->low_count, TRE_I2C_C0_TLOW);  in gpi_create_i2c_tre()
1646 		tre->dword[0] |= u32_encode_bits(i2c->high_count, TRE_I2C_C0_THIGH);  in gpi_create_i2c_tre()
1647 		tre->dword[0] |= u32_encode_bits(i2c->cycle_count, TRE_I2C_C0_TCYL);  in gpi_create_i2c_tre()
1648 		tre->dword[0] |= u32_encode_bits(i2c->pack_enable, TRE_I2C_C0_TX_PACK);  in gpi_create_i2c_tre()
1649 		tre->dword[0] |= u32_encode_bits(i2c->pack_enable, TRE_I2C_C0_RX_PACK);  in gpi_create_i2c_tre()
1651 		tre->dword[1] = 0;  in gpi_create_i2c_tre()
1665 			tre->dword[0] = u32_encode_bits(I2C_READ, TRE_I2C_GO_CMD);  in gpi_create_i2c_tre()
1667 			tre->dword[0] = u32_encode_bits(i2c->op, TRE_I2C_GO_CMD);  in gpi_create_i2c_tre()
1669 		tre->dword[0] |= u32_encode_bits(i2c->addr, TRE_I2C_GO_ADDR);  in gpi_create_i2c_tre()
1670 		tre->dword[0] |= u32_encode_bits(i2c->stretch, TRE_I2C_GO_STRETCH);  in gpi_create_i2c_tre()
1672 		tre->dword[1] = 0;  in gpi_create_i2c_tre()
1689 		tre->dword[0] = lower_32_bits(address);  in gpi_create_i2c_tre()
1698 	for (i = 0; i < tre_idx; i++)  in gpi_create_i2c_tre()
1699 		dev_dbg(dev, "TRE:%d %x:%x:%x:%x\n", i, desc->tre[i].dword[0],  in gpi_create_i2c_tre()
1710 	unsigned int tre_idx = 0;  in gpi_create_spi_tre()
1720 		tre->dword[0] = u32_encode_bits(spi->word_len, TRE_SPI_C0_WORD_SZ);  in gpi_create_spi_tre()
1721 		tre->dword[0] |= u32_encode_bits(spi->loopback_en, TRE_SPI_C0_LOOPBACK);  in gpi_create_spi_tre()
1722 		tre->dword[0] |= u32_encode_bits(spi->clock_pol_high, TRE_SPI_C0_CPOL);  in gpi_create_spi_tre()
1723 		tre->dword[0] |= u32_encode_bits(spi->data_pol_high, TRE_SPI_C0_CPHA);  in gpi_create_spi_tre()
1724 		tre->dword[0] |= u32_encode_bits(spi->pack_en, TRE_SPI_C0_TX_PACK);  in gpi_create_spi_tre()
1725 		tre->dword[0] |= u32_encode_bits(spi->pack_en, TRE_SPI_C0_RX_PACK);  in gpi_create_spi_tre()
1727 		tre->dword[1] = 0;  in gpi_create_spi_tre()
1741 		tre->dword[0] = u32_encode_bits(spi->fragmentation, TRE_SPI_GO_FRAG);  in gpi_create_spi_tre()
1742 		tre->dword[0] |= u32_encode_bits(spi->cs, TRE_SPI_GO_CS);  in gpi_create_spi_tre()
1743 		tre->dword[0] |= u32_encode_bits(spi->cmd, TRE_SPI_GO_CMD);  in gpi_create_spi_tre()
1745 		tre->dword[1] = 0;  in gpi_create_spi_tre()
1766 	tre->dword[0] = lower_32_bits(address);  in gpi_create_spi_tre()
1775 	for (i = 0; i < tre_idx; i++)  in gpi_create_spi_tre()
1776 		dev_dbg(dev, "TRE:%d %x:%x:%x:%x\n", i, desc->tre[i].dword[0],  in gpi_create_spi_tre()
1793 	u32 nr, nr_tre = 0;  in gpi_prep_slave_sg()
1873 	for (i = 0; i < gpi_desc->num_tre; i++) {  in gpi_issue_pending()
1888 	int i = 0, ret = 0;  in gpi_ch_init()
1893 	for (i = 0; i < MAX_CHANNELS_PER_GPII; i++)  in gpi_ch_init()
1898 	if (gpii->gchan[0].protocol != gpii->gchan[1].protocol) {  in gpi_ch_init()
1900 			gpii->gchan[0].protocol, gpii->gchan[1].protocol);  in gpi_ch_init()
1916 	ret = gpi_config_interrupts(gpii, DEFAULT_IRQ_SETTINGS, 0);  in gpi_ch_init()
1930 	for (i = 0; i < MAX_CHANNELS_PER_GPII; i++) {  in gpi_ch_init()
1939 	for (i = 0; i < MAX_CHANNELS_PER_GPII; i++) {  in gpi_ch_init()
1949 	for (i = i - 1; i >= 0; i--) {  in gpi_ch_init()
1955 	for (i = i - 1; i >= 0; i--)  in gpi_ch_init()
2003 	for (i = 0; i < MAX_CHANNELS_PER_GPII; i++)  in gpi_free_chan_resources()
2067 	for (gpii = 0; gpii < gpi_dev->max_gpii; gpii++) {  in gpi_find_avail_gpii()
2081 	for (gpii = 0; gpii < gpi_dev->max_gpii; gpii++) {  in gpi_find_avail_gpii()
2116 	chid = args->args[0];  in gpi_of_dma_xlate()
2126 	if (gpii < 0) {  in gpi_of_dma_xlate()
2156 	gpi_dev->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &gpi_dev->res);  in gpi_probe()
2193 	for (i = 0; i < gpi_dev->max_gpii; i++) {  in gpi_probe()
2201 		gpii->ev_cntxt_base_reg = gpi_dev->ee_base + GPII_n_EV_CH_k_CNTXT_0_OFFS(i, 0);  in gpi_probe()
2202 		gpii->ev_cntxt_db_reg = gpi_dev->ee_base + GPII_n_EV_CH_k_DOORBELL_0_OFFS(i, 0);  in gpi_probe()
2209 		if (ret < 0)  in gpi_probe()
2214 		for (chan = 0; chan < MAX_CHANNELS_PER_GPII; chan++) {  in gpi_probe()
2281 	{ .compatible = "qcom,sdm845-gpi-dma", .data = (void *)0x0 },
2282 	{ .compatible = "qcom,sm6350-gpi-dma", .data = (void *)0x10000 },
2285 	 * qcom,sdm845-gpi-dma (for ee_offset = 0x0) or qcom,sm6350-gpi-dma
2286 	 * (for ee_offset = 0x10000).
2288 	{ .compatible = "qcom,sc7280-gpi-dma", .data = (void *)0x10000 },
2289 	{ .compatible = "qcom,sm8150-gpi-dma", .data = (void *)0x0 },
2290 	{ .compatible = "qcom,sm8250-gpi-dma", .data = (void *)0x0 },
2291 	{ .compatible = "qcom,sm8350-gpi-dma", .data = (void *)0x10000 },
2292 	{ .compatible = "qcom,sm8450-gpi-dma", .data = (void *)0x10000 },