/freebsd/sys/contrib/device-tree/Bindings/pinctrl/ |
H A D | fsl,imx8mp-pinctrl.yaml | 75 reg = <0x30330000 0x10000>; 79 <0x228 0x488 0x5F0 0x0 0x6 0x49>, 80 <0x228 0x488 0x000 0x0 0x0 0x49>;
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/freebsd/sys/contrib/device-tree/include/dt-bindings/clock/ |
H A D | am4.h | 8 #define AM4_CLKCTRL_OFFSET 0x20 12 #define AM4_L3S_TSC_CLKCTRL_OFFSET 0x120 14 #define AM4_L3S_TSC_ADC_TSC_CLKCTRL AM4_L3S_TSC_CLKCTRL_INDEX(0x120) 17 #define AM4_L4_WKUP_AON_CLKCTRL_OFFSET 0x228 19 #define AM4_L4_WKUP_AON_WKUP_M3_CLKCTRL AM4_L4_WKUP_AON_CLKCTRL_INDEX(0x228) 20 #define AM4_L4_WKUP_AON_COUNTER_32K_CLKCTRL AM4_L4_WKUP_AON_CLKCTRL_INDEX(0x230) 23 #define AM4_L4_WKUP_CLKCTRL_OFFSET 0x220 25 #define AM4_L4_WKUP_L4_WKUP_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x220) 26 #define AM4_L4_WKUP_TIMER1_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x328) 27 #define AM4_L4_WKUP_WD_TIMER2_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x338) [all …]
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/freebsd/sys/contrib/device-tree/Bindings/arm/altera/ |
H A D | socfpga-system.txt | 11 reg = <0xffd08000 0x1000>; 12 cpu1-start-addr = <0xffd080c4>; 24 reg = <0xffd12000 0x228>;
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/freebsd/sys/contrib/device-tree/Bindings/remoteproc/ |
H A D | st-rproc.txt | 29 reg = <0x42000000 0x01000000>; 40 st,syscfg = <&syscfg_core 0x228>;
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/freebsd/sys/dev/rtwn/rtl8821a/ |
H A D | r21a_reg.h | 37 #define R21A_DWBCN1_CTRL 0x228 40 #define R21A_MAC_PHY_CRYSTALCAP_M 0x00fff000 44 #define R21A_DWBCN1_CTRL_SEL_EN 0x00020000 45 #define R21A_DWBCN1_CTRL_SEL_BCN1 0x00100000
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/freebsd/sys/arm64/rockchip/ |
H A D | rk_pinctrl.c | 150 RK_GPIO(0, "gpio0"), 164 RK_IOMUX(0, 0, 0x0084, 2), 165 RK_IOMUX(0, 1, 0x0088, 2), 166 RK_IOMUX(0, 2, 0x008C, 2), 168 RK_IOMUX(1, 3, 0x000C, 2), 169 RK_IOMUX(2, 0, 0x0010, 2), 170 RK_IOMUX(2, 1, 0x0014, 2), 171 RK_IOMUX(2, 2, 0x0018, 2), 172 RK_IOMUX(2, 3, 0x001C, 2), 173 RK_IOMUX(3, 0, 0x0020, 2), [all …]
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/freebsd/sys/contrib/device-tree/src/arm64/freescale/ |
H A D | imx8mq-pinfunc.h | 15 #define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0… 16 #define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0… 17 #define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0… 18 #define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0… 19 #define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0… 20 #define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0… 21 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0… 22 #define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0… 23 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0… 24 #define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0… [all …]
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H A D | imx8mm-pinfunc.h | 14 #define MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0… 15 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0… 16 #define MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0… 17 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0… 18 #define MX8MM_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0… 19 #define MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0… 20 #define MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0… 21 #define MX8MM_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0… 22 #define MX8MM_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0… 23 #define MX8MM_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0… [all …]
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H A D | imx8mn-pinfunc.h | 14 …ne MX8MN_IOMUXC_BOOT_MODE2_CCMSRCGPCMIX_BOOT_MODE2 0x020 0x25C 0x000 0x0 0x0 15 …ne MX8MN_IOMUXC_BOOT_MODE2_I2C1_SCL 0x020 0x25C 0x55C 0x1 0x3 16 …ne MX8MN_IOMUXC_BOOT_MODE3_CCMSRCGPCMIX_BOOT_MODE3 0x024 0x260 0x000 0x0 0x0 17 …ne MX8MN_IOMUXC_BOOT_MODE3_I2C1_SDA 0x024 0x260 0x56C 0x1 0x3 18 …ne MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0 19 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x000 0x1 0x0 20 …ne MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0 21 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0 22 …ne MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0 23 …ne MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0 [all …]
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H A D | imx8mp-pinfunc.h | 13 #define MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x014 0x274 0x000 0x0 0x0 14 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT 0x014 0x274 0x000 0x1 0x0 15 #define MX8MP_IOMUXC_GPIO1_IO00__ISP_FL_TRIG_0 0x014 0x274 0x5D4 0x3 0x0 16 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1 0x014 0x274 0x000 0x6 0x0 17 #define MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x018 0x278 0x000 0x0 0x0 18 #define MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x018 0x278 0x000 0x1 0x0 19 #define MX8MP_IOMUXC_GPIO1_IO01__ISP_SHUTTER_TRIG_0 0x018 0x278 0x5DC 0x3 0x0 20 #define MX8MP_IOMUXC_GPIO1_IO01__CCM_EXT_CLK2 0x018 0x278 0x000 0x6 0x0 21 #define MX8MP_IOMUXC_GPIO1_IO02__GPIO1_IO02 0x01C 0x27C 0x000 0x0 0x0 22 #define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x01C 0x27C 0x000 0x1 0x0 [all …]
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/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/ |
H A D | imx50-pinfunc.h | 13 #define MX50_PAD_KEY_COL0__KPP_COL_0 0x020 0x2cc 0x000 0x0 0x0 14 #define MX50_PAD_KEY_COL0__GPIO4_0 0x020 0x2cc 0x000 0x1 0x0 15 #define MX50_PAD_KEY_COL0__EIM_NANDF_CLE 0x020 0x2cc 0x000 0x2 0x0 16 #define MX50_PAD_KEY_COL0__CTI_TRIGIN7 0x020 0x2cc 0x000 0x6 0x0 17 #define MX50_PAD_KEY_COL0__USBPHY1_TXREADY 0x020 0x2cc 0x000 0x7 0x0 18 #define MX50_PAD_KEY_ROW0__KPP_ROW_0 0x024 0x2d0 0x000 0x0 0x0 19 #define MX50_PAD_KEY_ROW0__GPIO4_1 0x024 0x2d0 0x000 0x1 0x0 20 #define MX50_PAD_KEY_ROW0__EIM_NANDF_ALE 0x024 0x2d0 0x000 0x2 0x0 21 #define MX50_PAD_KEY_ROW0__CTI_TRIGIN_ACK7 0x024 0x2d0 0x000 0x6 0x0 22 #define MX50_PAD_KEY_ROW0__USBPHY1_RXVALID 0x024 0x2d0 0x000 0x7 0x0 [all …]
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H A D | imxrt1050-pinfunc.h | 10 #define IMX_PAD_SION 0x40000000 17 #define MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00 0x014 0x204 0x000 0x0 0x0 18 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A 0x014 0x204 0x494 0x1 0x0 19 #define MXRT1050_IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x014 0x204 0x500 0x2 0x1 20 #define MXRT1050_IOMUXC_GPIO_EMC_00_XBAR_INOUT2 0x014 0x204 0x60C 0x3 0x0 21 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXIO1_D00 0x014 0x204 0x000 0x4 0x0 22 #define MXRT1050_IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x014 0x204 0x000 0x5 0x0 24 #define MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01 0x018 0x208 0x000 0x0 0x0 25 #define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B 0x018 0x208 0x000 0x1 0x0 26 #define MXRT1050_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x018 0x208 0x4FC 0x2 0x1 [all …]
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H A D | imxrt1170-pinfunc.h | 10 #define IMX_PAD_SION 0x40000000 17 #define IOMUXC_GPIO_LPSR_00_FLEXCAN3_TX 0x000 0x040 0x0 0x0 0x0 18 #define IOMUXC_GPIO_LPSR_00_MIC_CLK 0x000 0x040 0x0 0x1 0x0 19 #define IOMUXC_GPIO_LPSR_00_MQS_RIGHT 0x000 0x040 0x0 0x2 0x0 20 #define IOMUXC_GPIO_LPSR_00_ARM_CM4_EVENTO 0x000 0x040 0x0 0x3 0x0 21 #define IOMUXC_GPIO_LPSR_00_GPIO_MUX6_IO00 0x000 0x040 0x0 0x5 0x0 22 #define IOMUXC_GPIO_LPSR_00_LPUART12_TXD 0x000 0x040 0x0B0 0x6 0x0 23 #define IOMUXC_GPIO_LPSR_00_SAI4_MCLK 0x000 0x040 0x0C8 0x7 0x0 24 #define IOMUXC_GPIO_LPSR_00_GPIO12_IO00 0x000 0x040 0x0 0xA 0x0 26 #define IOMUXC_GPIO_LPSR_01_FLEXCAN3_RX 0x004 0x044 0x080 0x0 0x0 [all …]
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H A D | imx6dl-pinfunc.h | 13 #define MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x04c 0x360 0x000 0x0 0x0 14 #define MX6QDL_PAD_CSI0_DAT10__AUD3_RXC 0x04c 0x360 0x000 0x1 0x0 15 #define MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x04c 0x360 0x7f8 0x2 0x0 16 #define MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x04c 0x360 0x000 0x3 0x0 17 #define MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x04c 0x360 0x8fc 0x3 0x0 18 #define MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x04c 0x360 0x000 0x5 0x0 19 #define MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x04c 0x360 0x000 0x7 0x0 20 #define MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x050 0x364 0x000 0x0 0x0 21 #define MX6QDL_PAD_CSI0_DAT11__AUD3_RXFS 0x050 0x364 0x000 0x1 0x0 22 #define MX6QDL_PAD_CSI0_DAT11__ECSPI2_SS0 0x050 0x364 0x800 0x2 0x0 [all …]
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H A D | imx6sl-pinfunc.h | 13 #define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x04c 0x2a4 0x000 0x0 0x0 14 #define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0 15 #define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x0 16 #define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0 17 #define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0 18 #define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x0 19 #define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x04c 0x2a4 0x7f4 0x6 0x0 20 #define MX6SL_PAD_AUD_RXC__AUD3_RXC 0x050 0x2a8 0x000 0x0 0x0 21 #define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0 22 #define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0 [all …]
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H A D | imx6q-pinfunc.h | 13 #define MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x04c 0x360 0x000 0x0 0x0 14 #define MX6QDL_PAD_SD2_DAT1__ECSPI5_SS0 0x04c 0x360 0x834 0x1 0x0 15 #define MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0x04c 0x360 0x000 0x2 0x0 16 #define MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x04c 0x360 0x7c8 0x3 0x0 17 #define MX6QDL_PAD_SD2_DAT1__KEY_COL7 0x04c 0x360 0x8f0 0x4 0x0 18 #define MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x04c 0x360 0x000 0x5 0x0 19 #define MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x050 0x364 0x000 0x0 0x0 20 #define MX6QDL_PAD_SD2_DAT2__ECSPI5_SS1 0x050 0x364 0x838 0x1 0x0 21 #define MX6QDL_PAD_SD2_DAT2__EIM_CS3_B 0x050 0x364 0x000 0x2 0x0 22 #define MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x050 0x364 0x7b8 0x3 0x0 [all …]
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H A D | imx35-pinfunc.h | 13 #define MX35_PAD_CAPTURE__GPT_CAPIN1 0x004 0x328 0x000 0x0 0x0 14 #define MX35_PAD_CAPTURE__GPT_CMPOUT2 0x004 0x328 0x000 0x1 0x0 15 #define MX35_PAD_CAPTURE__CSPI2_SS1 0x004 0x328 0x7f4 0x2 0x0 16 #define MX35_PAD_CAPTURE__EPIT1_EPITO 0x004 0x328 0x000 0x3 0x0 17 #define MX35_PAD_CAPTURE__CCM_CLK32K 0x004 0x328 0x7d0 0x4 0x0 18 #define MX35_PAD_CAPTURE__GPIO1_4 0x004 0x328 0x850 0x5 0x0 19 #define MX35_PAD_COMPARE__GPT_CMPOUT1 0x008 0x32c 0x000 0x0 0x0 20 #define MX35_PAD_COMPARE__GPT_CAPIN2 0x008 0x32c 0x000 0x1 0x0 21 #define MX35_PAD_COMPARE__GPT_CMPOUT3 0x008 0x32c 0x000 0x2 0x0 22 #define MX35_PAD_COMPARE__EPIT2_EPITO 0x008 0x32c 0x000 0x3 0x0 [all …]
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/freebsd/contrib/llvm-project/llvm/include/llvm/BinaryFormat/ELFRelocs/ |
H A D | AArch64.def | 7 // Null relocation: also 0x100 for ELF64 8 ELF_RELOC(R_AARCH64_NONE, 0) 10 ELF_RELOC(R_AARCH64_ABS64, 0x101) 11 ELF_RELOC(R_AARCH64_ABS32, 0x102) 12 ELF_RELOC(R_AARCH64_ABS16, 0x103) 13 ELF_RELOC(R_AARCH64_PREL64, 0x104) 14 ELF_RELOC(R_AARCH64_PREL32, 0x105) 15 ELF_RELOC(R_AARCH64_PREL16, 0x106) 17 ELF_RELOC(R_AARCH64_MOVW_UABS_G0, 0x107) 18 ELF_RELOC(R_AARCH64_MOVW_UABS_G0_NC, 0x108) [all …]
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/freebsd/tools/test/stress2/misc/ |
H A D | syzkaller51.sh | 7 # db_trace_self_wrapper() at db_trace_self_wrapper+0x2b/frame 0xfffffe00e49be680 8 # vpanic() at vpanic+0x17f/frame 0xfffffe00e49be6d0 9 # panic() at panic+0x43/frame 0xfffffe00e49be730 10 # sctp_handle_shutdown_complete() at sctp_handle_shutdown_complete+0xea/frame 0xfffffe00e49be750 11 # sctp_process_control() at sctp_process_control+0x1561/frame 0xfffffe00e49bea90 12 # sctp_common_input_processing() at sctp_common_input_processing+0x514/frame 0xfffffe00e49bec00 13 # sctp6_input_with_port() at sctp6_input_with_port+0x228/frame 0xfffffe00e49becf0 14 # sctp6_input() at sctp6_input+0xb/frame 0xfffffe00e49bed00 15 # ip6_input() at ip6_input+0xc2f/frame 0xfffffe00e49bede0 16 # swi_net() at swi_net+0x191/frame 0xfffffe00e49bee60 [all …]
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/freebsd/sys/contrib/device-tree/src/arm64/ti/ |
H A D | k3-am625-phyboard-lyra-rdk.dts | 33 #phy-cells = <0>; 54 pinctrl-0 = <&gpio_keys_pins_default>; 72 pinctrl-0 = <&leds_pins_default>, <&user_leds_pins_default>; 98 AM62X_IOPAD(0x1d4, PIN_INPUT, 7) /* (B15) UART0_RTSn.GPIO1_23 */ 104 AM62X_IOPAD(0x244, PIN_INPUT, 7) /* (C17) MMC1_SDWP.GPIO1_49 */ 110 AM62X_IOPAD(0x040, PIN_INPUT, 7) /* (N23) GPMC0_AD1.GPIO0_16 */ 116 AM62X_IOPAD(0x0b8, PIN_OUTPUT, 0) /* (U22) VOUT0_DATA0 */ 117 AM62X_IOPAD(0x0bc, PIN_OUTPUT, 0) /* (V2 [all...] |
H A D | k3-am62a7-sk.dts | 33 reg = <0x00000000 0x80000000 0x00000000 0x80000000>, 34 <0x00000008 0x80000000 0x00000000 0x80000000>; 43 reg = <0x00 0x9e78000 [all...] |
/freebsd/sys/contrib/device-tree/src/arm/hisilicon/ |
H A D | hi3620-hi4511.dts | 22 reg = <0x40000000 0x20000000>; 32 pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>; 39 pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func>; 46 pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>; 53 pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>; 60 pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>; 67 pinctrl-0 = <&board_pmx_pins>; 71 0x008 0x0 /* GPIO -- eFUSE_DOUT */ 72 0x100 0x0 /* USIM_CLK & USIM_DATA (IOMG63) */ 77 0x0f0 0x0 [all …]
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/freebsd/sys/dev/dwc/ |
H A D | dwc1000_reg.h | 37 #define MAC_CONFIGURATION 0x0 47 #define MAC_FRAME_FILTER 0x4 53 #define FRAME_FILTER_PR (1 << 0) /* All Incoming Frames */ 54 #define GMAC_MAC_HTHIGH 0x08 55 #define GMAC_MAC_HTLOW 0x0c 56 #define GMII_ADDRESS 0x10 57 #define GMII_ADDRESS_PA_MASK 0x1f /* Phy device */ 59 #define GMII_ADDRESS_GR_MASK 0x1f /* Phy register */ 61 #define GMII_ADDRESS_CR_MASK 0xf 64 #define GMII_ADDRESS_GB (1 << 0) /* Busy */ [all …]
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/freebsd/sys/contrib/device-tree/src/arm64/broadcom/stingray/ |
H A D | stingray-pinctrl.dtsi | 37 reg = <0x00140000 0x250>; 45 reg = <0x0014029c 0x26c>; 47 #size-cells = <0>; 49 pinctrl-single,function-mask = <0xf>; 51 &range 0 91 MODE_GPIO 61 0x038 MODE_NITRO /* tsio_0 */ 62 0x03c MODE_NITRO /* tsio_1 */ 68 0x0ac MODE_PNOR /* nand_ce1_n */ 69 0x0b0 MODE_PNOR /* nand_ce0_n */ 70 0x0b4 MODE_PNOR /* nand_we_n */ [all …]
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/freebsd/sys/dev/ffec/ |
H A D | if_ffecreg.h | 41 #define FEC_IER_REG 0x0004 42 #define FEC_IEM_REG 0x0008 61 #define FEC_RDAR_REG 0x0010 64 #define FEC_TDAR_REG 0x0014 67 #define FEC_ECR_REG 0x0024 76 #define FEC_ECR_RESET (1 << 0) 78 #define FEC_MMFR_REG 0x0040 80 #define FEC_MMFR_ST_VALUE (0x01 << FEC_MMFR_ST_SHIFT) 82 #define FEC_MMFR_OP_WRITE (0x01 << FEC_MMFR_OP_SHIFT) 83 #define FEC_MMFR_OP_READ (0x02 << FEC_MMFR_OP_SHIFT) [all …]
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