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Searched +full:0 +full:x2200000 (Results 1 – 18 of 18) sorted by relevance

/freebsd/sys/contrib/device-tree/src/arm/marvell/
H A Darmada-385-linksys-caiman.dts18 wan_amber@0 {
20 reg = <0x0>;
25 reg = <0x1>;
30 reg = <0x2>;
35 reg = <0x3>;
40 reg = <0x5>;
45 reg = <0x6>;
50 reg = <0x7>;
55 reg = <0x8>;
60 reg = <0x9>;
[all …]
H A Darmada-385-linksys-cobra.dts18 wan_amber@0 {
20 reg = <0x0>;
25 reg = <0x1>;
30 reg = <0x2>;
35 reg = <0x3>;
40 reg = <0x5>;
45 reg = <0x6>;
50 reg = <0x7>;
55 reg = <0x8>;
60 reg = <0x9>;
[all …]
H A Darmada-385-linksys-shelby.dts18 wan_amber@0 {
20 reg = <0x0>;
25 reg = <0x1>;
30 reg = <0x2>;
35 reg = <0x3>;
40 reg = <0x5>;
45 reg = <0x6>;
50 reg = <0x7>;
55 reg = <0x8>;
60 reg = <0x9>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/watchdog/
H A Dti,rti-wdt.yaml42 PON_REASON_SOF_NUM(0xBBBBCCCC), PON_REASON_MAGIC_NUM(0xDDDDDDDD),
43 and PON_REASON_EOF_NUM(0xCCCCBBBB), are pre-stored at the first
48 specific memory address(0xa220000) should be set. More please
66 * starting from 0xa2200000 by RTI Watchdog Firmware, then make it
72 * reg = <0x00 0xa2200000 0x00 0x1000>;
81 reg = <0x220000
[all...]
/freebsd/sys/contrib/device-tree/Bindings/pinctrl/
H A Dbrcm,bcm2835-gpio.txt17 - bit 0 specifies polarity (0 for normal, 1 for inverted)
26 bits[3:0] trigger type and level flags:
66 are the integer GPIO IDs; 0==GPIO0, 1==GPIO1, ... 53==GPIO53.
70 0: GPIO in
79 0: none
91 reg = <0x2200000 0xb4>;
/freebsd/sys/contrib/device-tree/Bindings/gpio/
H A Dnvidia,tegra186-gpio.txt109 - Bit 0 specifies polarity
110 - 0: Active-high (normal).
123 - Bits [3:0] indicate trigger type and level:
138 <0x0 0x2200000 0x0 0x10000>,
139 <0x0 0x2210000 0x0 0x10000>;
141 <0 47 IRQ_TYPE_LEVEL_HIGH>,
142 <0 50 IRQ_TYPE_LEVEL_HIGH>,
143 <0 53 IRQ_TYPE_LEVEL_HIGH>,
144 <0 56 IRQ_TYPE_LEVEL_HIGH>,
145 <0 59 IRQ_TYPE_LEVEL_HIGH>,
[all …]
H A Dnvidia,tegra186-gpio.yaml122 - Bit 0 specifies polarity
123 - 0: Active-high (normal).
137 - Bits [3:0] indicate trigger type and level:
190 reg = <0x2200000 0x10000>,
191 <0x2210000 0x10000>;
192 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>,
193 <0 50 IRQ_TYPE_LEVEL_HIGH>,
194 <0 53 IRQ_TYPE_LEVEL_HIGH>,
195 <0 56 IRQ_TYPE_LEVEL_HIGH>,
196 <0 59 IRQ_TYPE_LEVEL_HIGH>,
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/xilinx/
H A Dzynqmp-sm-k26-revA.dts50 memory@0 {
52 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
61 reg = <0x0 0x7ff00000 0x0 0x100000>;
95 io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,
110 pwms = <&ttc0 2 40000 0>;
144 &qspi { /* MIO 0-5 - U143 */
146 spi_flash: flash@0 { /* MT25QU512A */
148 reg = <0>;
158 partition@0 {
160 reg = <0x0 0x80000>; /* 512KB */
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dmsm8994-sony-xperia-kitakami.dtsi16 * We support MSM8994 v2 (0x20000) and v2.1 (0x20001).
17 * The V1 chip (0x0 and 0x10000) is significantly different
21 qcom,msm-id = <207 0x20000>, <207 0x20001>;
23 qcom,pmic-id = <0x10009 0x1000a 0x00 0x00>;
25 qcom,board-id = <8 0>;
34 button-0 {
75 reg = <0 0x1fe00000 0 0x200000>;
76 console-size = <0x100000>;
77 record-size = <0x10000>;
78 ftrace-size = <0x10000>;
[all …]
H A Dsdm670-google-sargo.dts44 reg = <0 0x9c000000 0 (1080 * 2220 * 4)>;
55 #clock-cells = <0>;
61 #clock-cells = <0>;
71 pinctrl-0 = <&vol_up_pin>;
85 reg = <0 0x8b000000 0 0x9800000>;
90 reg = <0 0x94800000 0 0x500000>;
95 reg = <0 0x94d00000 0 0x100000>;
100 reg = <0 0x94e00000 0 0x800000>;
105 reg = <0 0x95600000 0 0x200000>;
110 reg = <0 0x95800000 0 0x2200000>;
[all …]
H A Dmsm8994.dtsi29 #clock-cells = <0>;
36 #clock-cells = <0>;
44 #size-cells = <0>;
46 CPU0: cpu@0 {
49 reg = <0x0 0x0>;
62 reg = <0x0 0x1>;
70 reg = <0x0 0x2>;
78 reg = <0x0 0x3>;
86 reg = <0x0 0x100>;
99 reg = <0x0 0x101>;
[all …]
/freebsd/sys/sys/
H A Dkernel.h96 SI_SUB_DUMMY = 0x0000000, /* not executed; for linker */
97 SI_SUB_TUNABLES = 0x0700000, /* establish tunable values */
98 SI_SUB_COPYRIGHT = 0x0800001, /* first use of console */
99 SI_SUB_VM = 0x1000000, /* virtual memory system init */
100 SI_SUB_COUNTER = 0x1100000, /* counter(9) is initialized */
101 SI_SUB_KMEM = 0x1800000, /* kernel memory */
102 SI_SUB_HYPERVISOR = 0x1A40000, /*
107 SI_SUB_WITNESS = 0x1A80000, /* witness initialization */
108 SI_SUB_MTX_POOL_DYNAMIC = 0x1AC0000, /* dynamic mutex pool */
109 SI_SUB_LOCK = 0x1B00000, /* various locks */
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/ti/
H A Dk3-j7200-main.dtsi10 #clock-cells = <0>;
18 reg = <0x00 0x70000000 0x00 0x100000>;
21 ranges = <0x00 0x00 0x70000000 0x100000>;
23 atf-sram@0 {
24 reg = <0x00 0x20000>;
30 reg = <0x00 0x00100000 0x00 0x1c000>;
33 ranges = <0x00 0x00 0x00100000 0x1c000>;
37 reg = <0x4080 0x20>;
39 mux-reg-masks = <0x0 0x3>, <0x4 0x3>, /* SERDES0 lane0/1 select */
40 <0x8 0x3>, <0xc 0x3>; /* SERDES0 lane2/3 select */
[all …]
H A Dk3-j721s2-main.dtsi13 #clock-cells = <0>;
15 clock-frequency = <0>;
22 reg = <0x0 0x70000000 0x0 0x400000>;
25 ranges = <0x0 0x0 0x70000000 0x400000>;
27 atf-sram@0 {
28 reg = <0x0 0x20000>;
32 reg = <0x1f0000 0x10000>;
36 reg = <0x200000 0x200000>;
42 reg = <0x00 0x00104000 0x00 0x18000>;
45 ranges = <0x00 0x00 0x00104000 0x18000>;
[all …]
H A Dk3-j721e-main.dtsi15 #clock-cells = <0>;
17 clock-frequency = <0>;
21 #clock-cells = <0>;
23 clock-frequency = <0>;
30 reg = <0x0 0x70000000 0x0 0x800000>;
33 ranges = <0x0 0x0 0x70000000 0x800000>;
35 atf-sram@0 {
36 reg = <0x0 0x20000>;
42 reg = <0 0x00100000 0 0x1c000>; /* excludes pinctrl region */
45 ranges = <0x0 0x0 0x00100000 0x1c000>;
[all …]
H A Dk3-j784s4-main.dtsi16 #clock-cells = <0>;
26 reg = <0x00 0x70000000 0x00 0x800000>;
29 ranges = <0x00 0x00 0x70000000 0x800000>;
31 atf-sram@0 {
32 reg = <0x00 0x20000>;
36 reg = <0x1f0000 0x10000>;
40 reg = <0x200000 0x200000>;
46 reg = <0x00 0x00100000 0x00 0x1c000>;
49 ranges = <0x00 0x00 0x00100000 0x1c000>;
53 reg = <0x4034 0x4>;
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/nvidia/
H A Dtegra186.dtsi20 reg = <0x0 0x00100000 0x0 0xf000>,
21 <0x0 0x0010f000 0x0 0x1000>;
27 reg = <0x0 0x220000
[all...]
H A Dtegra194.dtsi20 bus@0 {
25 ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
29 reg = <0x0 0x00100000 0x
[all...]