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Searched +full:0 +full:x2100 (Results 1 – 25 of 138) sorted by relevance

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/linux/Documentation/devicetree/bindings/pinctrl/
H A Dingenic,pinctrl.yaml18 which the pin is associated and N is an integer from 0 to 31 identifying the
22 pins. The X2000 and the X2100 contains 5 GPIO ports, PA to PE, for a total of
47 - ingenic,x2100-pinctrl
65 const: 0
68 "^gpio@[0-9]$":
86 - ingenic,x2100-gpio
170 reg = <0x10010000 0x600>;
173 #size-cells = <0>;
175 gpio@0 {
177 reg = <0>;
[all …]
/linux/arch/arm/mach-mv78xx0/
H A Dmv78xx0.h17 * f0800000 PCIe #0 I/O space
29 * fee00000 f0800000 64K PCIe #0 I/O space
39 #define MV78XX0_CORE0_REGS_PHYS_BASE 0xf1020000
40 #define MV78XX0_CORE1_REGS_PHYS_BASE 0xf1024000
41 #define MV78XX0_CORE_REGS_VIRT_BASE IOMEM(0xfe400000)
42 #define MV78XX0_CORE_REGS_PHYS_BASE 0xfe400000
45 #define MV78XX0_PCIE_IO_PHYS_BASE(i) (0xf0800000 + ((i) << 20))
48 #define MV78XX0_REGS_PHYS_BASE 0xf1000000
49 #define MV78XX0_REGS_VIRT_BASE IOMEM(0xfec00000)
52 #define MV78XX0_SRAM_PHYS_BASE (0xf2200000)
[all …]
/linux/drivers/isdn/hardware/mISDN/
H A Dhfc_pci.h16 #define HFCPCI_BTRANS_THRESMASK 0x00
19 #define PCI_ENA_MEMIO 0x02
20 #define PCI_ENA_MASTER 0x04
23 #define HCFPCI_C_I 0x08
24 #define HFCPCI_TRxR 0x0C
25 #define HFCPCI_MON1_D 0x28
26 #define HFCPCI_MON2_D 0x2C
29 #define HFCPCI_B1_SSL 0x80
30 #define HFCPCI_B2_SSL 0x84
31 #define HFCPCI_AUX1_SSL 0x88
[all …]
/linux/arch/mips/generic/
H A Dboard-ingenic.c28 return "X2100"; in ingenic_get_system_type()
64 #define INGENIC_CGU_BASE 0x10000000
77 if (offset < 0) in ingenic_force_12M_ext()
94 cgu = ioremap(INGENIC_CGU_BASE, 0x4); in ingenic_force_12M_ext()
114 if (!fdt_node_check_compatible(fdt, 0, "qi,lb60") && in ingenic_fixup_fdt()
115 fdt_path_offset(fdt, "/memory") < 0) in ingenic_fixup_fdt()
116 early_init_dt_add_memory_arch(0, SZ_32M); in ingenic_fixup_fdt()
153 { .compatible = "ingenic,x2100", .data = (void *)MACH_INGENIC_X2100 },
181 return 0; in ingenic_pm_enter()
197 return 0; in ingenic_pm_init()
/linux/arch/arm/mach-orion5x/
H A Dorion5x.h36 #define ORION5X_REGS_PHYS_BASE 0xf1000000
37 #define ORION5X_REGS_VIRT_BASE IOMEM(0xfec00000)
40 #define ORION5X_PCIE_IO_PHYS_BASE 0xf2000000
41 #define ORION5X_PCIE_IO_BUS_BASE 0x00000000
44 #define ORION5X_PCI_IO_PHYS_BASE 0xf2100000
45 #define ORION5X_PCI_IO_BUS_BASE 0x00010000
48 #define ORION5X_SRAM_PHYS_BASE (0xf2200000)
52 #define ORION5X_PCIE_WA_PHYS_BASE 0xf0000000
53 #define ORION5X_PCIE_WA_VIRT_BASE IOMEM(0xfd000000)
56 #define ORION5X_PCIE_MEM_PHYS_BASE 0xe0000000
[all …]
/linux/Documentation/devicetree/bindings/powerpc/fsl/
H A Ddiu.txt20 reg = <0x2c000 100>;
28 reg = <0x2100 0x100>;
29 interrupts = <64 0x8>;
/linux/arch/mips/boot/dts/realtek/
H A Drtl83xx.dtsi14 #address-cells = <0>;
23 ranges = <0x0 0x18000000 0x10000>;
27 reg = <0x2000 0x100>;
44 reg = <0x2100 0x100>;
/linux/sound/soc/codecs/
H A Drt5514.h15 #define RT5514_DEVICE_ID 0x10ec5514
17 #define RT5514_RESET 0x2000
18 #define RT5514_PWR_ANA1 0x2004
19 #define RT5514_PWR_ANA2 0x2008
20 #define RT5514_I2S_CTRL1 0x2010
21 #define RT5514_I2S_CTRL2 0x2014
22 #define RT5514_VAD_CTRL6 0x2030
23 #define RT5514_EXT_VAD_CTRL 0x206c
24 #define RT5514_DIG_IO_CTRL 0x2070
25 #define RT5514_PAD_CTRL1 0x2080
[all …]
/linux/drivers/scsi/arm/
H A Dcumana_1.c39 #define CTRL 0x16fc
40 #define STAT 0x2004
41 #define L(v) (((v)<<16)|((v) & 0x0000ffff))
42 #define H(v) (((v)>>16)|((v) & 0xffff0000))
49 u8 __iomem *dma = hostdata->pdma_io + 0x2000; in cumanascsi_pwrite()
51 if(!len) return 0; in cumanascsi_pwrite()
53 writeb(0x02, base + CTRL); in cumanascsi_pwrite()
60 if(status & 0x80) in cumanascsi_pwrite()
62 if(!(status & 0x40)) in cumanascsi_pwrite()
73 if(len == 0) in cumanascsi_pwrite()
[all …]
/linux/drivers/phy/broadcom/
H A Dphy-bcm-ns2-pcie.c11 #define BLK_ADDR_REG_OFFSET 0x1f
12 #define PLL_AFE1_100MHZ_BLK 0x2100
13 #define PLL_CLK_AMP_OFFSET 0x03
14 #define PLL_CLK_AMP_2P05V 0x2b18
31 return 0; in ns2_pci_phy_init()
66 return 0; in ns2_pci_phy_probe()
/linux/arch/arm64/boot/dts/broadcom/stingray/
H A Dstingray-pcie.dtsi8 reg = <0 0x60400000 0 0x1000>;
11 bus-range = <0x0 0x1>;
16 ranges = <0x83000000 0 0x10000000 0 0x10000000 0 0x20000000>;
20 msi-map = <0x100 &gic_its 0x2000 0x1>, /* PF0 */
21 <0x108 &gic_its 0x2040 0x8>, /* PF0-VF0-7 */
22 <0x101 &gic_its 0x2080 0x1>, /* PF1 */
23 <0x110 &gic_its 0x20c8 0x8>, /* PF1-VF8-15 */
24 <0x102 &gic_its 0x2100 0x1>, /* PF2 */
25 <0x118 &gic_its 0x2150 0x8>, /* PF2-VF16-23 */
26 <0x103 &gic_its 0x2180 0x1>, /* PF3 */
[all …]
/linux/arch/arm64/boot/dts/amlogic/
H A Damlogic-a4-common.dtsi27 #clock-cells = <0>;
38 reg = <0x0 0xfff01000 0 0x1000>,
39 <0x0 0xfff02000 0 0x2000>,
40 <0x0 0xfff04000 0 0x2000>,
41 <0x0 0xfff06000 0 0x2000>;
43 #address-cells = <0>;
50 reg = <0x0 0xfe000000 0x0 0x480000>;
53 ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>;
57 reg = <0x0 0x2100 0x0 0x10>;
64 reg = <0x0 0x7a000 0x0 0x18>;
[all …]
H A Damlogic-t7.dtsi16 #address-cells = <0x2>;
17 #size-cells = <0x0>;
54 reg = <0x0 0x100>;
61 reg = <0x0 0x101>;
68 reg = <0x0 0x102>;
75 reg = <0x0 0x103>;
79 cpu0: cpu@0 {
82 reg = <0x0 0x0>;
89 reg = <0x0 0x1>;
96 reg = <0x0 0x2>;
[all …]
/linux/include/video/
H A Dtrident.h4 #define TRIDENTFB_DEBUG 0
20 #define CYBER9320 0x9320
21 #define CYBER9388 0x9388
22 #define CYBER9382 0x9382 /* the real PCI id for this is 9660 */
23 #define CYBER9385 0x9385 /* ditto */
24 #define CYBER9397 0x9397
25 #define CYBER9397DVD 0x939A
26 #define CYBER9520 0x9520
27 #define CYBER9525DVD 0x9525
28 #define TGUI9440 0x9440
[all …]
/linux/arch/arm/boot/dts/ti/omap/
H A Domap3-overo-common-dvi.dtsi13 OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */
14 OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */
15 OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */
16 OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */
17 OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */
18 OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */
19 OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */
20 OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */
21 OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */
22 OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */
[all …]
H A Domap3-thunder.dts17 OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */
18 OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */
19 OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */
20 OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */
21 OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */
22 OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */
23 OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */
24 OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */
25 OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */
26 OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */
[all …]
H A Domap3-ha-lcd.dts16 pinctrl-0 = <
29 OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT_PULLUP | MUX_MODE4) /* gpio_136, Touchscreen IRQ */
35 OMAP3_CORE1_IOPAD(0x212c, PIN_OUTPUT_PULLUP | MUX_MODE4) /* gpio_110, Touchscreen Wake */
41 OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */
42 OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */
43 OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */
44 OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */
45 OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */
46 OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */
47 OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */
[all …]
H A Domap3-overo-common-lcd43.dtsi13 OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */
14 OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */
15 OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */
16 OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */
17 OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */
18 OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */
19 OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */
20 OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */
21 OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */
22 OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */
[all …]
H A Domap3-overo-common-lcd35.dtsi13 OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */
14 OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */
15 OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */
16 OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */
17 OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */
18 OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */
19 OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */
20 OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */
21 OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */
22 OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */
[all …]
/linux/drivers/ufs/host/
H A Dufs-mediatek.h15 #define MTK_MCQ_INVALID_IRQ 0xFFFF
18 #define EHS_EN BIT(0)
29 #define REG_UFS_XOUFS_CTRL 0x140
30 #define REG_UFS_REFCLK_CTRL 0x144
31 #define REG_UFS_MMIO_OPT_CTRL_0 0x160
32 #define REG_UFS_EXTREG 0x2100
33 #define REG_UFS_MPHYCTRL 0x2200
34 #define REG_UFS_MTK_IP_VER 0x2240
35 #define REG_UFS_REJECT_MON 0x22AC
36 #define REG_UFS_DEBUG_SEL 0x22C0
[all …]
/linux/include/linux/soc/pxa/
H A Dcpu.h18 * PXA210 B0 0x69052922 0x2926C013
19 * PXA210 B1 0x69052923 0x3926C013
20 * PXA210 B2 0x69052924 0x4926C013
21 * PXA210 C0 0x69052D25 0x5926C013
23 * PXA250 A0 0x69052100 0x09264013
24 * PXA250 A1 0x69052101 0x19264013
25 * PXA250 B0 0x69052902 0x29264013
26 * PXA250 B1 0x69052903 0x39264013
27 * PXA250 B2 0x69052904 0x49264013
28 * PXA250 C0 0x69052D05 0x59264013
[all …]
/linux/drivers/mfd/
H A Dsi476x-prop.c25 for (i = 0; i < size; i++) in si476x_core_element_is_in_array()
38 for (i = 0; i < size; i++) in si476x_core_element_is_in_range()
49 0x0000, in si476x_core_is_valid_property_a10()
50 0x0500, 0x0501, in si476x_core_is_valid_property_a10()
51 0x0600, in si476x_core_is_valid_property_a10()
52 0x0709, 0x070C, 0x070D, 0x70E, 0x710, in si476x_core_is_valid_property_a10()
53 0x0718, in si476x_core_is_valid_property_a10()
54 0x1207, 0x1208, in si476x_core_is_valid_property_a10()
55 0x2007, in si476x_core_is_valid_property_a10()
56 0x2300, in si476x_core_is_valid_property_a10()
[all …]
/linux/drivers/infiniband/hw/mlx5/
H A Ddata_direct.c24 { PCI_VDEVICE(MELLANOX, 0x2100) }, /* ConnectX-8 Data Direct */
25 { 0, }
43 if (start < 0) { in mlx5_data_direct_vpd_get_vuid()
50 ret = dev->vuid ? 0 : -ENOMEM; in mlx5_data_direct_vpd_get_vuid()
78 return 0; in mlx5_data_direct_set_dma_caps()
95 if (strcmp(dev->vuid, vuid) == 0) { in mlx5_data_direct_ib_reg()
106 return 0; in mlx5_data_direct_ib_reg()
133 if (strcmp(dev->vuid, reg->vuid) == 0) in mlx5_data_direct_dev_reg()
152 if (strcmp(dev->vuid, reg->vuid) == 0) in mlx5_data_direct_dev_unreg()
192 return 0; in mlx5_data_direct_probe()
/linux/arch/mips/include/asm/
H A Dcpu.h16 register 15, select 0) is defined in this (backwards compatible) way:
24 that bits 16-23 have been 0 for all MIPS processors before the MIPS32/64
28 #define PRID_OPT_MASK 0xff000000
34 #define PRID_COMP_MASK 0xff0000
36 #define PRID_COMP_LEGACY 0x000000
37 #define PRID_COMP_MIPS 0x010000
38 #define PRID_COMP_BROADCOM 0x020000
39 #define PRID_COMP_ALCHEMY 0x030000
40 #define PRID_COMP_SIBYTE 0x040000
41 #define PRID_COMP_SANDCRAFT 0x050000
[all …]
/linux/drivers/media/radio/si4713/
H A Dsi4713.h25 #define SI4713_PRODUCT_NUMBER 0x0D
41 #define SI4713_PWUP_FUNC_TX 0x02
42 #define SI4713_PWUP_FUNC_PATCH 0x0F
43 #define SI4713_PWUP_OPMOD_ANALOG 0x50
44 #define SI4713_PWUP_OPMOD_DIGITAL 0x0F
47 #define SI4713_CMD_POWER_UP 0x01
50 #define SI4713_CMD_GET_REV 0x10
53 #define SI4713_CMD_POWER_DOWN 0x11
57 #define SI4713_CMD_SET_PROPERTY 0x12
61 #define SI4713_CMD_GET_PROPERTY 0x13
[all …]

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