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Searched +full:0 +full:x20108 (Results 1 – 12 of 12) sorted by relevance

/linux/Documentation/devicetree/bindings/watchdog/
H A Dmarvell,orion-wdt.yaml96 reg = <0x20300 0x28>, <0x20108 0x4>;
/linux/arch/arm/boot/dts/marvell/
H A Dorion5x.dtsi24 reg = <MBUS_ID(0xf0, 0x01) 0x1046C 0x4>;
25 ranges = <0 MBUS_ID(0x01, 0x0f) 0 0xffffffff>;
28 clocks = <&core_clk 0>;
34 reg = <MBUS_ID(0xf0, 0x01) 0x1045C 0x4>;
35 ranges = <0 MBUS_ID(0x01, 0x1e) 0 0xffffffff>;
38 clocks = <&core_clk 0>;
44 reg = <MBUS_ID(0xf0, 0x01) 0x10460 0x4>;
45 ranges = <0 MBUS_ID(0x01, 0x1d) 0 0xffffffff>;
48 clocks = <&core_clk 0>;
54 reg = <MBUS_ID(0xf0, 0x01) 0x10464 0x4>;
[all …]
H A Dkirkwood.dtsi15 #size-cells = <0>;
17 cpu@0 {
20 reg = <0>;
37 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 /* internal-regs */
38 MBUS_ID(0x01, 0x2f) 0 0xf4000000 0x10000 /* nand flash */
39 MBUS_ID(0x03, 0x01) 0 0xf5000000 0x10000 /* crypto sram */
42 pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256 MiB memory space */
43 pcie-io-aperture = <0xf2000000 0x100000>; /* 1 MiB I/O space */
48 cle = <0>;
52 reg = <MBUS_ID(0x01, 0x2f) 0 0x400>;
[all …]
H A Ddove.dtsi22 #size-cells = <0>;
24 cpu0: cpu@0 {
28 reg = <0>;
34 marvell,tauros2-cache-features = <0>;
46 #size-cells = <0>;
51 pinctrl-0 = <&pmx_i2cmux_0>;
55 i2c0: i2c@0 {
56 reg = <0>;
58 #size-cells = <0>;
65 #size-cells = <0>;
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/pcie/
H A Dpcie_6_1_0_offset.h28 // base address: 0x11a08000
29 …O_HWDID 0x2270800
30 …e regDXIO_HWDID_BASE_IDX 0
31 …O_LINKAGE_LANEGRP 0x2270802
32 …e regDXIO_LINKAGE_LANEGRP_BASE_IDX 0
33 …O_LINKAGE_KPDMX 0x2270803
34 …e regDXIO_LINKAGE_KPDMX_BASE_IDX 0
35 …O_LINKAGE_KPMX 0x2270804
36 …O_LINKAGE_KPFIFO 0x2270805
37 …O_LINKAGE_KPNP 0x2270806
[all …]
/linux/drivers/watchdog/
H A Dorion_wdt.c27 #define ORION_RSTOUT_MASK_OFFSET 0x20108
35 #define TIMER_CTRL 0x0000
40 #define TIMER_A370_STATUS 0x0004
44 #define TIMER1_VAL_OFF 0x001c
46 #define WDT_MAX_CYCLE_COUNT 0xffffffff
94 return 0; in orion_wdt_clock_init()
117 return 0; in armada370_wdt_clock_init()
138 return 0; in armada375_wdt_clock_init()
157 return 0; in armada375_wdt_clock_init()
180 return 0; in armadaxp_wdt_clock_init()
[all …]
/linux/arch/arm64/boot/dts/apple/
H A Ds5l8960x-pmgr.dtsi11 reg = <0x20000 4>;
12 #power-domain-cells = <0>;
13 #reset-cells = <0>;
20 reg = <0x20008 4>;
21 #power-domain-cells = <0>;
22 #reset-cells = <0>;
29 reg = <0x200f0 4>;
30 #power-domain-cells = <0>;
31 #reset-cells = <0>;
38 reg = <0x200f8 4>;
[all …]
H A Dt7001-pmgr.dtsi11 reg = <0x20000 4>;
12 #power-domain-cells = <0>;
13 #reset-cells = <0>;
20 reg = <0x20008 4>;
21 #power-domain-cells = <0>;
22 #reset-cells = <0>;
29 reg = <0x20010 4>;
30 #power-domain-cells = <0>;
31 #reset-cells = <0>;
38 reg = <0x20040 4>;
[all …]
H A Dt7000-pmgr.dtsi10 reg = <0x20000 4>;
11 #power-domain-cells = <0>;
12 #reset-cells = <0>;
19 reg = <0x20008 4>;
20 #power-domain-cells = <0>;
21 #reset-cells = <0>;
28 reg = <0x20040 4>;
29 #power-domain-cells = <0>;
30 #reset-cells = <0>;
37 reg = <0x201f8 4>;
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/nbio/
H A Dnbio_6_1_offset.h27 // base address: 0x0
28 …PSWUSCFG0_VENDOR_ID 0x0000
29 …PSWUSCFG0_DEVICE_ID 0x0002
30 …PSWUSCFG0_COMMAND 0x0004
31 …PSWUSCFG0_STATUS 0x0006
32 …PSWUSCFG0_REVISION_ID 0x0008
33 …PSWUSCFG0_PROG_INTERFACE 0x0009
34 …PSWUSCFG0_SUB_CLASS 0x000a
35 …PSWUSCFG0_BASE_CLASS 0x000b
36 …PSWUSCFG0_CACHE_LINE 0x000c
[all …]
H A Dnbio_7_0_offset.h27 // base address: 0x0
28 …NB_NBCFG0_NB_VENDOR_ID 0x0000
29 …NB_NBCFG0_NB_DEVICE_ID 0x0002
30 …NB_NBCFG0_NB_COMMAND 0x0004
31 …NB_NBCFG0_NB_STATUS 0x0006
32 …NB_NBCFG0_NB_REVISION_ID 0x0008
33 …NB_NBCFG0_NB_REGPROG_INF 0x0009
34 …NB_NBCFG0_NB_SUB_CLASS 0x000a
35 …NB_NBCFG0_NB_BASE_CODE 0x000b
36 …NB_NBCFG0_NB_CACHE_LINE 0x000c
[all …]
/linux/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_reg.h26 #define ATC_ATC_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
27 #define ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS (0x1<<2)
28 #define ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU (0x1<<5)
29 #define ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT (0x1<<3)
30 #define ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR (0x1<<4)
31 #define ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND (0x1<<1)
33 #define ATC_REG_ATC_INIT_ARRAY 0x1100b8
35 #define ATC_REG_ATC_INIT_DONE 0x1100bc
36 /* [RC 6] Interrupt register #0 read clear */
37 #define ATC_REG_ATC_INT_STS_CLR 0x1101c0
[all …]