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/linux/drivers/media/platform/ti/vpe/
H A Dcsc.h13 #define CSC_CSC00 0x00
14 #define CSC_A0_MASK 0x1fff
15 #define CSC_A0_SHIFT 0
16 #define CSC_B0_MASK 0x1fff
19 #define CSC_CSC01 0x04
20 #define CSC_C0_MASK 0x1fff
21 #define CSC_C0_SHIFT 0
22 #define CSC_A1_MASK 0x1fff
25 #define CSC_CSC02 0x08
26 #define CSC_B1_MASK 0x1fff
[all …]
/linux/drivers/gpu/drm/meson/
H A Dmeson_viu.c46 VIU_MATRIX_OSD_EOTF = 0,
51 VIU_LUT_OSD_EOTF = 0,
63 0, 0, 0, /* pre offset */
67 0, 0, 0, /* 10'/11'/12' */
68 0, 0, 0, /* 20'/21'/22' */
70 0, 0, 0 /* mode, right_shift, clip_en */
85 writel(((m[0] & 0xfff) << 16) | (m[1] & 0xfff), in meson_viu_set_g12a_osd1_matrix()
87 writel(m[2] & 0xfff, in meson_viu_set_g12a_osd1_matrix()
89 writel(((m[3] & 0x1fff) << 16) | (m[4] & 0x1fff), in meson_viu_set_g12a_osd1_matrix()
91 writel(((m[5] & 0x1fff) << 16) | (m[6] & 0x1fff), in meson_viu_set_g12a_osd1_matrix()
[all …]
/linux/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_dump.h22 #define DRV_DUMP_XSTORM_WAITP_ADDRESS 0x2b8a80
23 #define DRV_DUMP_TSTORM_WAITP_ADDRESS 0x1b8a80
24 #define DRV_DUMP_USTORM_WAITP_ADDRESS 0x338a80
25 #define DRV_DUMP_CSTORM_WAITP_ADDRESS 0x238a80
45 #define BNX2X_DUMP_VERSION 0x61111111
65 static const u32 page_vals_e2[] = {0, 128};
68 {0x58000, 4608, DUMP_CHIP_E2, 0x30}
74 static const u32 page_vals_e3[] = {0, 128};
77 {0x58000, 4608, DUMP_CHIP_E3A0 | DUMP_CHIP_E3B0, 0x30}
81 { 0x2000, 1, 0x1f, 0xfff},
[all …]
/linux/drivers/mfd/
H A Dwm8350-regmap.c23 { 0xFFFF, 0xFFFF, 0x0000 }, /* R0 - Reset/ID */
24 { 0x7CFF, 0x0C00, 0x0000 }, /* R1 - ID */
25 { 0x007F, 0x0000, 0x0000 }, /* R2 - ROM Mask ID */
26 { 0xBE3B, 0xBE3B, 0x8000 }, /* R3 - System Control 1 */
27 { 0xFEF7, 0xFEF7, 0xF800 }, /* R4 - System Control 2 */
28 { 0x80FF, 0x80FF, 0x8000 }, /* R5 - System Hibernate */
29 { 0xFB0E, 0xFB0E, 0x0000 }, /* R6 - Interface Control */
30 { 0x0000, 0x0000, 0x0000 }, /* R7 */
31 { 0xE537, 0xE537, 0xFFFF }, /* R8 - Power mgmt (1) */
32 { 0x0FF3, 0x0FF3, 0xFFFF }, /* R9 - Power mgmt (2) */
[all …]
/linux/drivers/media/rc/img-ir/
H A Dimg-ir-sanyo.c31 addr = (raw >> 0) & 0x1fff; in img_ir_sanyo_scancode()
32 addr_inv = (raw >> 13) & 0x1fff; in img_ir_sanyo_scancode()
33 data = (raw >> 26) & 0xff; in img_ir_sanyo_scancode()
34 data_inv = (raw >> 34) & 0xff; in img_ir_sanyo_scancode()
36 if ((data_inv ^ data) != 0xff) in img_ir_sanyo_scancode()
39 if ((addr_inv ^ addr) != 0x1fff) in img_ir_sanyo_scancode()
55 data = in->data & 0xff; in img_ir_sanyo_filter()
56 data_m = in->mask & 0xff; in img_ir_sanyo_filter()
57 data_inv = data ^ 0xff; in img_ir_sanyo_filter()
59 if (in->data & 0xff700000) in img_ir_sanyo_filter()
[all …]
/linux/drivers/gpu/drm/exynos/
H A Dregs-gsc.h14 #define GSC_ENABLE 0x00
16 #define GSC_ENABLE_PP_UPDATE_TIME_CURR (0 << 9)
21 #define GSC_ENABLE_NORM_MODE (0 << 7)
31 #define GSC_ENABLE_ON (1 << 0)
34 #define GSC_SW_RESET 0x04
35 #define GSC_SW_RESET_SRESET (1 << 0)
38 #define GSC_IRQ 0x08
43 #define GSC_IRQ_ENABLE (1 << 0)
46 #define GSC_IN_CON 0x10
63 #define GSC_IN_RGB_SD_NARROW (0 << 14)
[all …]
/linux/drivers/staging/sm750fb/
H A Dsm750_accel.h5 #define HW_ROP2_COPY 0xc
6 #define HW_ROP2_XOR 0x6
8 /* notes: below address are the offset value from de_base_address (0x100000) */
11 #define DE_BASE_ADDR_TYPE1 0x100000
13 #define DE_BASE_ADDR_TYPE2 0x8000
15 #define DE_BASE_ADDR_TYPE3 0
18 #define DE_PORT_ADDR_TYPE1 0x110000
20 #define DE_PORT_ADDR_TYPE2 0x100000
22 #define DE_PORT_ADDR_TYPE3 0x100000
24 #define DE_SOURCE 0x0
[all …]
/linux/arch/sh/kernel/cpu/sh4a/
H A Dclock-sh7722.c18 #define FRQCR 0xa4150000
19 #define VCLKCR 0xa4150004
20 #define SCLKACR 0xa4150008
21 #define SCLKBCR 0xa415000c
22 #define IRDACLKCR 0xa4150018
23 #define PLLCR 0xa4150024
24 #define MSTPCR0 0xa4150030
25 #define MSTPCR1 0xa4150034
26 #define MSTPCR2 0xa4150038
27 #define DLLFRQ 0xa4150050
[all …]
H A Dclock-sh7343.c16 #define FRQCR 0xa4150000
17 #define VCLKCR 0xa4150004
18 #define SCLKACR 0xa4150008
19 #define SCLKBCR 0xa415000c
20 #define PLLCR 0xa4150024
21 #define MSTPCR0 0xa4150030
22 #define MSTPCR1 0xa4150034
23 #define MSTPCR2 0xa4150038
24 #define DLLFRQ 0xa4150050
44 if (__raw_readl(PLLCR) & 0x1000) in dll_recalc()
[all …]
H A Dclock-sh7366.c16 #define FRQCR 0xa4150000
17 #define VCLKCR 0xa4150004
18 #define SCLKACR 0xa4150008
19 #define SCLKBCR 0xa415000c
20 #define PLLCR 0xa4150024
21 #define MSTPCR0 0xa4150030
22 #define MSTPCR1 0xa4150034
23 #define MSTPCR2 0xa4150038
24 #define DLLFRQ 0xa4150050
44 if (__raw_readl(PLLCR) & 0x1000) in dll_recalc()
[all …]
/linux/drivers/input/gameport/
H A Dfm801-gp.c18 #define PCI_VENDOR_ID_FORTEMEDIA 0x1319
19 #define PCI_DEVICE_ID_FM801_GP 0x0802
34 *buttons = (~w >> 14) & 0x03; in fm801_gp_cooked_read()
35 axes[0] = (w == 0xffff) ? -1 : ((w & 0x1fff) << 5); in fm801_gp_cooked_read()
37 axes[1] = (w == 0xffff) ? -1 : ((w & 0x1fff) << 5); in fm801_gp_cooked_read()
39 *buttons |= ((~w >> 14) & 0x03) << 2; in fm801_gp_cooked_read()
40 axes[2] = (w == 0xffff) ? -1 : ((w & 0x1fff) << 5); in fm801_gp_cooked_read()
42 axes[3] = (w == 0xffff) ? -1 : ((w & 0x1fff) << 5); in fm801_gp_cooked_read()
43 outw(0xff, gameport->io); /* reset */ in fm801_gp_cooked_read()
45 return 0; in fm801_gp_cooked_read()
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/therm/
H A Dgm107.c30 return 0; in gm107_fan_pwm_ctrl()
37 *divs = nvkm_rd32(device, 0x10eb20) & 0x1fff; in gm107_fan_pwm_get()
38 *duty = nvkm_rd32(device, 0x10eb24) & 0x1fff; in gm107_fan_pwm_get()
39 return 0; in gm107_fan_pwm_get()
46 nvkm_mask(device, 0x10eb10, 0x1fff, divs); /* keep the high bits */ in gm107_fan_pwm_set()
47 nvkm_wr32(device, 0x10eb14, duty | 0x80000000); in gm107_fan_pwm_set()
48 return 0; in gm107_fan_pwm_set()
H A Dgf119.c31 u32 gpio = nvkm_rd32(device, 0x00d610 + (line * 0x04)); in pwm_info()
33 switch (gpio & 0x000000c0) { in pwm_info()
34 case 0x00000000: /* normal mode, possibly pwm forced off by us */ in pwm_info()
35 case 0x00000040: /* nvio special */ in pwm_info()
36 switch (gpio & 0x0000001f) { in pwm_info()
37 case 0x00: return 2; in pwm_info()
38 case 0x19: return 1; in pwm_info()
39 case 0x1c: return 0; in pwm_info()
40 case 0x1e: return 2; in pwm_info()
57 u32 data = enable ? 0x00000040 : 0x00000000; in gf119_fan_pwm_ctrl()
[all …]
/linux/drivers/hid/
H A Dhid-uclogic-params-test.c29 .str_desc_size = 0,
35 .res = 0,
37 0x0E, 0x03,
38 0x70, 0xB2,
39 0x10, 0x77,
40 0x08,
41 0x00,
42 0xFF, 0x1F,
43 0x00, 0x00,
47 [UCLOGIC_RDESC_PEN_PH_ID_X_LM] = 0xB270,
[all …]
/linux/drivers/gpu/drm/arm/
H A Dmalidp_regs.h20 #define MALIDP_DE_IRQ_UNDERRUN (1 << 0)
34 #define MALIDP500_SE_IRQ_CONF_MODE (1 << 0)
50 #define MALIDP550_SE_IRQ_EOW (1 << 0)
54 #define MALIDP550_DC_IRQ_CONF_VALID (1 << 0)
67 #define MALIDP_CFG_VALID (1 << 0)
68 #define MALIDP_DISP_FUNC_GAMMA (1 << 0)
75 #define MALIDP_REG_STATUS 0x00000
76 #define MALIDP_REG_SETIRQ 0x00004
77 #define MALIDP_REG_MASKIRQ 0x00008
78 #define MALIDP_REG_CLEARIRQ 0x0000c
[all …]
/linux/drivers/gpu/drm/sun4i/
H A Dsun4i_tcon.h20 #define SUN4I_TCON_GCTL_REG 0x0
22 #define SUN4I_TCON_GCTL_IOMAP_MASK BIT(0)
23 #define SUN4I_TCON_GCTL_IOMAP_TCON1 (1 << 0)
24 #define SUN4I_TCON_GCTL_IOMAP_TCON0 (0 << 0)
26 #define SUN4I_TCON_GINT0_REG 0x4
34 #define SUN4I_TCON_GINT1_REG 0x8
36 #define SUN4I_TCON_FRM_CTL_REG 0x10
42 #define SUN4I_TCON0_FRM_SEED_PR_REG 0x14
43 #define SUN4I_TCON0_FRM_SEED_PG_REG 0x18
44 #define SUN4I_TCON0_FRM_SEED_PB_REG 0x1c
[all …]
/linux/drivers/media/common/b2c2/
H A Dflexcop-hw-filter.c30 v418.mac_address_418.MAC1 = mac[0]; in flexcop_set_mac_filter()
49 /* index_reg_310.extra_index_reg need to 0 or 7 to work */ in flexcop_pid_group_filter()
68 vpid.vregname.field = onoff ? pid : 0x1fff; \
78 Stream1_trans, 0); in flexcop_pid_Stream1_PID_ctrl()
85 Stream2_trans, 0); in flexcop_pid_Stream2_PID_ctrl()
91 pid_ctrl(pid_filter_304, PCR_PID, PCR_filter_sig, PCR_trans, 0); in flexcop_pid_PCR_PID_ctrl()
97 pid_ctrl(pid_filter_304, PMT_PID, PMT_filter_sig, PMT_trans, 0); in flexcop_pid_PMT_PID_ctrl()
103 pid_ctrl(pid_filter_308, EMM_PID, EMM_filter_sig, EMM_trans, 0); in flexcop_pid_EMM_PID_ctrl()
109 pid_ctrl(pid_filter_308, ECM_PID, ECM_filter_sig, ECM_trans, 0); in flexcop_pid_ECM_PID_ctrl()
115 if (pid == 0x2000) in flexcop_pid_control()
[all …]
/linux/include/video/
H A Dsamsung_fimd.h18 #define VIDCON0 0x00
21 #define VIDCON0_VIDOUT_MASK (0x7 << 26)
23 #define VIDCON0_VIDOUT_RGB (0x0 << 26)
24 #define VIDCON0_VIDOUT_TV (0x1 << 26)
25 #define VIDCON0_VIDOUT_I80_LDI0 (0x2 << 26)
26 #define VIDCON0_VIDOUT_I80_LDI1 (0x3 << 26)
27 #define VIDCON0_VIDOUT_WB_RGB (0x4 << 26)
28 #define VIDCON0_VIDOUT_WB_I80_LDI0 (0x6 << 26)
29 #define VIDCON0_VIDOUT_WB_I80_LDI1 (0x7 << 26)
31 #define VIDCON0_L1_DATA_MASK (0x7 << 23)
[all …]
/linux/drivers/media/platform/samsung/s5p-jpeg/
H A Djpeg-regs.h19 #define S5P_JPGMOD 0x00
20 #define S5P_PROC_MODE_MASK (0x1 << 3)
21 #define S5P_PROC_MODE_DECOMPR (0x1 << 3)
22 #define S5P_PROC_MODE_COMPR (0x0 << 3)
23 #define S5P_SUBSAMPLING_MODE_MASK 0x7
24 #define S5P_SUBSAMPLING_MODE_444 (0x0 << 0)
25 #define S5P_SUBSAMPLING_MODE_422 (0x1 << 0)
26 #define S5P_SUBSAMPLING_MODE_420 (0x2 << 0)
27 #define S5P_SUBSAMPLING_MODE_GRAY (0x3 << 0)
30 #define S5P_JPGOPR 0x04
[all …]
/linux/drivers/gpu/drm/rockchip/
H A Drockchip_vop_reg.c103 .scale_yrgb_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
104 .scale_yrgb_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
105 .scale_cbcr_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
106 .scale_cbcr_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 16),
110 .scale_yrgb_x = VOP_REG(RK3036_WIN1_SCL_FACTOR_YRGB, 0xffff, 0x0),
111 .scale_yrgb_y = VOP_REG(RK3036_WIN1_SCL_FACTOR_YRGB, 0xffff, 16),
119 .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 0),
120 .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 3),
121 .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 15),
122 .act_info = VOP_REG(RK3036_WIN0_ACT_INFO, 0x1fff1fff, 0),
[all …]
/linux/drivers/media/platform/samsung/s3c-camif/
H A Dcamif-regs.h19 * id = 0 - codec (FIMC C), 1 - preview (FIMC P).
23 #define S3C_CAMIF_REG_CISRCFMT 0x00
25 #define CISRCFMT_ITU656_8BIT (0 << 31)
26 #define CISRCFMT_ORDER422_YCBYCR (0 << 14)
31 #define CISRCFMT_SIZE_CAM_MASK (0x1fff << 16 | 0x1fff)
34 #define S3C_CAMIF_REG_CIWDOFST 0x04
43 #define CIWDOFST_OFST_MASK (0x7ff << 16 | 0x7ff)
46 #define S3C_CAMIF_REG_CIWDOFST2 0x14
47 #define CIWDOFST2_OFST2_MASK (0xfff << 16 | 0xfff)
50 #define S3C_CAMIF_REG_CIGCTRL 0x08
[all …]
/linux/include/linux/mfd/
H A Dmxs-lradc.h24 #define LRADC_CTRL0 0x00
51 #define LRADC_CTRL1 0x10
54 #define LRADC_CTRL1_MX28_LRADC_IRQ_EN_MASK (0x1fff << 16)
55 #define LRADC_CTRL1_MX23_LRADC_IRQ_EN_MASK (0x01ff << 16)
59 #define LRADC_CTRL1_MX28_LRADC_IRQ_MASK 0x1fff
60 #define LRADC_CTRL1_MX23_LRADC_IRQ_MASK 0x01ff
61 #define LRADC_CTRL1_LRADC_IRQ_OFFSET 0
63 #define LRADC_CTRL2 0x20
67 #define LRADC_STATUS 0x40
68 #define LRADC_STATUS_TOUCH_DETECT_RAW BIT(0)
[all …]
/linux/drivers/media/platform/samsung/exynos4-is/
H A Dfimc-lite-reg.h14 #define FLITE_REG_CISRCSIZE 0x00
15 #define FLITE_REG_CISRCSIZE_ORDER422_IN_YCBYCR (0 << 14)
19 #define FLITE_REG_CISRCSIZE_ORDER422_MASK (0x3 << 14)
20 #define FLITE_REG_CISRCSIZE_SIZE_CAM_MASK (0x3fff << 16 | 0x3fff)
23 #define FLITE_REG_CIGCTRL 0x04
24 #define FLITE_REG_CIGCTRL_YUV422_1P (0x1e << 24)
25 #define FLITE_REG_CIGCTRL_RAW8 (0x2a << 24)
26 #define FLITE_REG_CIGCTRL_RAW10 (0x2b << 24)
27 #define FLITE_REG_CIGCTRL_RAW12 (0x2c << 24)
28 #define FLITE_REG_CIGCTRL_RAW14 (0x2d << 24)
[all …]
/linux/drivers/net/wireless/realtek/rtl818x/rtl8180/
H A Drtl8225.c29 bangdata = (data << 4) | (addr & 0xf); in rtl8225_write()
31 reg80 = rtl818x_ioread16(priv, &priv->map->RFPinsOutput) & 0xfff3; in rtl8225_write()
34 rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, reg82 | 0x7); in rtl8225_write()
37 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, reg84 | 0x7 | 0x400); in rtl8225_write()
48 for (i = 15; i >= 0; i--) { in rtl8225_write()
69 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, reg84 | 0x400); in rtl8225_write()
70 rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, 0x1FFF); in rtl8225_write()
81 reg84 = rtl818x_ioread16(priv, &priv->map->RFPinsSelect) | 0x400; in rtl8225_read()
83 reg80 &= ~0xF; in rtl8225_read()
85 rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, reg82 | 0x000F); in rtl8225_read()
[all …]
/linux/drivers/media/platform/ti/omap3isp/
H A Dispreg.h21 #define ISP_REVISION (0x000)
22 #define ISP_SYSCONFIG (0x004)
23 #define ISP_SYSSTATUS (0x008)
24 #define ISP_IRQ0ENABLE (0x00C)
25 #define ISP_IRQ0STATUS (0x010)
26 #define ISP_IRQ1ENABLE (0x014)
27 #define ISP_IRQ1STATUS (0x018)
28 #define ISP_TCTRL_GRESET_LENGTH (0x030)
29 #define ISP_TCTRL_PSTRB_REPLAY (0x034)
30 #define ISP_CTRL (0x040)
[all …]

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