Home
last modified time | relevance | path

Searched +full:0 +full:x1f004 (Results 1 – 15 of 15) sorted by relevance

/linux/drivers/gpu/drm/radeon/
H A Dtrinityd.h30 #define CG_CGTT_LOCAL_0 0x0
31 #define CG_CGTT_LOCAL_1 0x1
34 #define SMU_SCLK_DPM_STATE_0_CNTL_0 0x1f000
35 # define STATE_VALID(x) ((x) << 0)
36 # define STATE_VALID_MASK (0xff << 0)
37 # define STATE_VALID_SHIFT 0
39 # define CLK_DIVIDER_MASK (0xff << 8)
42 # define VID_MASK (0xff << 16)
45 # define LVRT_MASK (0xff << 24)
47 #define SMU_SCLK_DPM_STATE_0_CNTL_1 0x1f004
[all …]
/linux/drivers/clk/qcom/
H A Dgcc-sdx65.c36 .offset = 0x0,
39 .enable_reg = 0x6d000,
40 .enable_mask = BIT(0),
53 { 0x1, 2 },
58 .offset = 0x0,
73 { P_BI_TCXO, 0 },
91 { P_BI_TCXO, 0 },
105 { P_BI_TCXO, 0 },
119 { P_PCIE_PIPE_CLK, 0 },
129 { P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK, 0 },
[all …]
H A Dgcc-nord.c46 .offset = 0x0,
49 .enable_reg = 0x9d020,
50 .enable_mask = BIT(0),
63 { 0x1, 2 },
68 .offset = 0x0,
85 { P_BI_TCXO, 0 },
97 { P_BI_TCXO, 0 },
107 { P_BI_TCXO, 0 },
121 { P_BI_TCXO, 0 },
131 .reg = 0x49094,
[all …]
H A Dgcc-sdm660.c51 .offset = 0x0,
54 .enable_reg = 0x52000,
55 .enable_mask = BIT(0),
81 .offset = 0x00000,
94 .offset = 0x1000,
97 .enable_reg = 0x52000,
124 .offset = 0x1000,
137 .offset = 0x77000,
140 .enable_reg = 0x52000,
154 .offset = 0x77000,
[all …]
H A Dgcc-qcm2290.c46 { 500000000, 1250000000, 0 },
58 .offset = 0x0,
61 .enable_reg = 0x79000,
62 .enable_mask = BIT(0),
75 { 0x1, 2 },
80 .offset = 0x0,
95 .offset = 0x1000,
98 .enable_reg = 0x79000,
113 .l = 0x3c,
114 .alpha = 0x0,
[all …]
H A Dgcc-sm6115.c50 { 500000000, 1250000000, 0 },
58 .offset = 0x0,
63 .enable_reg = 0x79000,
64 .enable_mask = BIT(0),
77 { 0x1, 2 },
82 .offset = 0x0,
97 { 0x0, 1 },
102 .offset = 0x0,
118 .l = 0x3c,
119 .vco_val = 0x1 << 20,
[all …]
H A Dgcc-msm8996.c49 .offset = 0x00000,
52 .enable_reg = 0x52000,
53 .enable_mask = BIT(0),
79 .offset = 0x00000,
94 .enable_reg = 0x5200c,
95 .enable_mask = BIT(0),
111 .enable_reg = 0x5200c,
126 .offset = 0x77000,
129 .enable_reg = 0x52000,
143 .offset = 0x77000,
[all …]
H A Dgcc-msm8998.c27 #define GCC_MMSS_MISC 0x0902C
28 #define GCC_GPU_MISC 0x71028
31 { 250000000, 2000000000, 0 },
36 .offset = 0x0,
41 .enable_reg = 0x52000,
42 .enable_mask = BIT(0),
55 .offset = 0x0,
68 .offset = 0x0,
81 .offset = 0x0,
94 .offset = 0x0,
[all …]
H A Dgcc-sm6375.c54 { 249600000, 2000000000, 0 },
58 { 595200000, 3600000000UL, 0 },
62 .offset = 0x0,
65 .enable_reg = 0x79000,
66 .enable_mask = BIT(0),
79 { 0x1, 2 },
84 .offset = 0x0,
101 { 0x3, 3 },
106 .offset = 0x0,
123 .offset = 0x1000,
[all …]
H A Dgcc-shikra.c67 { 500000000, 1250000000, 0 },
79 .offset = 0x0,
82 .enable_reg = 0x79000,
83 .enable_mask = BIT(0),
96 { 0x1, 2 },
101 .offset = 0x0,
119 .l = 0x3c,
120 .alpha = 0x0,
123 .main_output_mask = BIT(0),
124 .config_ctl_val = 0x4001055b,
[all …]
H A Dgcc-qcs8300.c59 .offset = 0x0,
62 .enable_reg = 0x4b028,
63 .enable_mask = BIT(0),
76 { 0x1, 2 },
81 .offset = 0x0,
98 .offset = 0x1000,
101 .enable_reg = 0x4b028,
115 .offset = 0x4000,
118 .enable_reg = 0x4b028,
132 .offset = 0x7000,
[all …]
H A Dgcc-sm6125.c42 .offset = 0x0,
45 .enable_reg = 0x79000,
46 .enable_mask = BIT(0),
85 .offset = 0x3000,
88 .enable_reg = 0x79000,
102 .offset = 0x4000,
105 .enable_reg = 0x79000,
119 .offset = 0x5000,
122 .enable_reg = 0x79000,
136 .offset = 0x6000,
[all …]
H A Dgcc-sa8775p.c73 .offset = 0x0,
76 .enable_reg = 0x4b028,
77 .enable_mask = BIT(0),
88 { 0x1, 2 },
93 .offset = 0x0,
110 .offset = 0x1000,
113 .enable_reg = 0x4b028,
125 .offset = 0x4000,
128 .enable_reg = 0x4b028,
140 .offset = 0x5000,
[all …]
/linux/drivers/gpu/drm/amd/include/asic_reg/nbif/
H A Dnbif_6_1_offset.h26 // base address: 0x0
27 … 0x0000 // duplicate
28 … 0x0002 // duplicate
29 … 0x0004 // duplicate
30 … 0x0006 // duplicate
31 … 0x0008 // duplicate
32 … 0x0009 // duplicate
33 … 0x000a // duplicate
34 … 0x000b // duplicate
35 … 0x000c // duplicate
[all …]
/linux/drivers/pinctrl/tegra/
H A Dpinctrl-tegra238.c1595 .mux_bit = 0, \
1608 #define drive_soc_gpio36_pt1 DRV_PINGROUP_ENTRY_Y(0x10004, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1609 #define drive_soc_gpio53_pt2 DRV_PINGROUP_ENTRY_Y(0x1000c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1610 #define drive_soc_gpio38_pt3 DRV_PINGROUP_ENTRY_Y(0x1001c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1611 #define drive_soc_gpio40_pt4 DRV_PINGROUP_ENTRY_Y(0x1002c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1612 #define drive_soc_gpio75_ps2 DRV_PINGROUP_ENTRY_Y(0x10034, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1613 #define drive_soc_gpio81_pt0 DRV_PINGROUP_ENTRY_Y(0x1003c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1614 #define drive_soc_gpio78_ps5 DRV_PINGROUP_ENTRY_Y(0x10044, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1615 #define drive_soc_gpio34_pt5 DRV_PINGROUP_ENTRY_Y(0x1004c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
1616 #define drive_gen7_i2c_scl_ps3 DRV_PINGROUP_ENTRY_Y(0x100a4, 12, 5, 20, 5, -1, -1, -1, -1, 0)
[all …]