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Searched +full:0 +full:x1e080000 (Results 1 – 4 of 4) sorted by relevance

/linux/arch/arm/boot/dts/broadcom/
H A Dbcm53016-dlink-dwl-8610ap.dts13 memory@0 {
16 reg = <0x00000000 0x08000000>,
17 <0x88000000 0x08000000>;
26 gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>;
66 * Flash memory at 0x1e000000-0x1fffffff
72 reg = <0x1e080000 0x00020000>;
112 trx@0 {
114 reg = <0x00000000 0x02800000>;
121 reg = <0x02800000 0x02800000>;
128 reg = <0x05000000 0x03000000>;
/linux/Documentation/devicetree/bindings/clock/
H A Dgoogle,gs101-clock.yaml157 - description: Connectivity Peripheral 0/1 bus clock (from CMU_TOP)
158 - description: Connectivity Peripheral 0/1 IP clock (from CMU_TOP)
175 reg = <0x1e080000 0x8000>;
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dimu_v12_0.c38 #define TRANSFER_RAM_MASK 0x001c0000
97 WREG32_SOC15(GC, 0, regGFX_IMU_I_RAM_ADDR, 0); in imu_v12_0_load_microcode()
99 for (i = 0; i < fw_size; i++) in imu_v12_0_load_microcode()
100 WREG32_SOC15(GC, 0, regGFX_IMU_I_RAM_DATA, le32_to_cpup(fw_data++)); in imu_v12_0_load_microcode()
102 WREG32_SOC15(GC, 0, regGFX_IMU_I_RAM_ADDR, adev->gfx.imu_fw_version); in imu_v12_0_load_microcode()
109 WREG32_SOC15(GC, 0, regGFX_IMU_D_RAM_ADDR, 0); in imu_v12_0_load_microcode()
111 for (i = 0; i < fw_size; i++) in imu_v12_0_load_microcode()
112 WREG32_SOC15(GC, 0, regGFX_IMU_D_RAM_DATA, le32_to_cpup(fw_data++)); in imu_v12_0_load_microcode()
114 WREG32_SOC15(GC, 0, regGFX_IMU_D_RAM_ADDR, adev->gfx.imu_fw_version); in imu_v12_0_load_microcode()
116 return 0; in imu_v12_0_load_microcode()
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/linux/drivers/clk/samsung/
H A Dclk-gs101.c31 /* Register Offset definitions for CMU_TOP (0x1e080000) */
32 #define PLL_LOCKTIME_PLL_SHARED0 0x0000
33 #define PLL_LOCKTIME_PLL_SHARED1 0x0004
34 #define PLL_LOCKTIME_PLL_SHARED2 0x0008
35 #define PLL_LOCKTIME_PLL_SHARED3 0x000c
36 #define PLL_LOCKTIME_PLL_SPARE 0x0010
37 #define PLL_CON0_PLL_SHARED0 0x0100
38 #define PLL_CON1_PLL_SHARED0 0x0104
39 #define PLL_CON2_PLL_SHARED0 0x0108
40 #define PLL_CON3_PLL_SHARED0 0x010c
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